Unified Coverage Report :: Module :: gpio_csr_assert_fpv

Module : gpio_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/gpio-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_gpio_csr_assert_0/gpio_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gpio_csr_assert	85.71						85.71

---

Module Instance : tb.dut.gpio_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : gpio_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	6	85.71
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	6	85.71

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	51646533	0	0	0
ctrl_en_input_filter_rd_A	51646533	73893	0	0
intr_ctrl_en_falling_rd_A	51646533	71870	0	0
intr_ctrl_en_lvlhigh_rd_A	51646533	71912	0	0
intr_ctrl_en_lvllow_rd_A	51646533	72801	0	0
intr_ctrl_en_rising_rd_A	51646533	72400	0	0
intr_enable_rd_A	51646533	71199	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51646533	0	0	0

ctrl_en_input_filter_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51646533	73893	0	0
T1	52163	389	0	0
T2	0	206	0	0
T3	0	397	0	0
T4	0	5	0	0
T5	0	276	0	0
T6	0	804	0	0
T7	0	13	0	0
T8	0	154	0	0
T9	0	2348	0	0
T10	0	311	0	0
T11	8167	0	0	0
T12	8857	0	0	0
T13	1740	0	0	0
T14	2122	0	0	0
T15	3204	0	0	0
T16	2591	0	0	0
T17	4655	0	0	0
T18	4766	0	0	0
T19	7008	0	0	0

intr_ctrl_en_falling_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51646533	71870	0	0
T1	52163	471	0	0
T2	0	166	0	0
T3	0	353	0	0
T5	0	305	0	0
T6	0	727	0	0
T7	0	2	0	0
T8	0	138	0	0
T9	0	2005	0	0
T10	0	435	0	0
T11	8167	0	0	0
T12	8857	0	0	0
T13	1740	0	0	0
T14	2122	0	0	0
T15	3204	0	0	0
T16	2591	0	0	0
T17	4655	0	0	0
T18	4766	0	0	0
T19	7008	0	0	0
T20	0	11	0	0

intr_ctrl_en_lvlhigh_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51646533	71912	0	0
T1	52163	367	0	0
T2	0	150	0	0
T3	0	344	0	0
T4	0	10	0	0
T5	0	298	0	0
T6	0	666	0	0
T7	0	5	0	0
T8	0	91	0	0
T9	0	2047	0	0
T11	8167	0	0	0
T12	8857	0	0	0
T13	1740	0	0	0
T14	2122	0	0	0
T15	3204	0	0	0
T16	2591	0	0	0
T17	4655	0	0	0
T18	4766	0	0	0
T19	7008	0	0	0
T21	0	6	0	0

intr_ctrl_en_lvllow_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51646533	72801	0	0
T1	52163	407	0	0
T2	0	203	0	0
T3	0	353	0	0
T5	0	253	0	0
T6	0	613	0	0
T8	0	144	0	0
T9	0	1940	0	0
T11	8167	0	0	0
T12	8857	0	0	0
T13	1740	0	0	0
T14	2122	0	0	0
T15	3204	0	0	0
T16	2591	0	0	0
T17	4655	0	0	0
T18	4766	0	0	0
T19	7008	0	0	0
T20	0	4	0	0
T21	0	10	0	0
T22	0	4	0	0

intr_ctrl_en_rising_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51646533	72400	0	0
T1	52163	335	0	0
T2	0	138	0	0
T3	0	340	0	0
T4	0	2	0	0
T5	0	317	0	0
T6	0	686	0	0
T8	0	139	0	0
T9	0	2177	0	0
T10	0	350	0	0
T11	8167	0	0	0
T12	8857	0	0	0
T13	1740	0	0	0
T14	2122	0	0	0
T15	3204	0	0	0
T16	2591	0	0	0
T17	4655	0	0	0
T18	4766	0	0	0
T19	7008	0	0	0
T20	0	2	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51646533	71199	0	0
T1	52163	499	0	0
T2	0	126	0	0
T3	0	203	0	0
T4	0	3	0	0
T5	0	257	0	0
T6	0	677	0	0
T7	0	10	0	0
T8	0	98	0	0
T11	8167	0	0	0
T12	8857	0	0	0
T13	1740	0	0	0
T14	2122	0	0	0
T15	3204	0	0	0
T16	2591	0	0	0
T17	4655	0	0	0
T18	4766	0	0	0
T19	7008	0	0	0
T20	0	5	0	0
T21	0	3	0	0