Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/gpio-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1367245	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4878411

1

T24

87

T25

164

T26

374

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2783184	1			T24	60		T25	38		T26	54
values[0x0]	1725952	1			T24	32		T25	60		T26	167
values[0x1]	1736520	1			T24	30		T25	86		T26	177

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1085942	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5159714

1

T24

92

T25

167

T26

384

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	17494	1			T25	8		T26	3		T28	3
valid_sources[0x01]	18998	1			T26	3		T32	2		T60	2
valid_sources[0x02]	17559	1			T24	1		T25	8		T29	10
valid_sources[0x03]	20745	1			T28	2		T29	4		T30	2
valid_sources[0x04]	19033	1			T24	4		T28	4		T30	2
valid_sources[0x05]	19700	1			T24	1		T28	1		T29	1
valid_sources[0x06]	19754	1			T30	1		T60	1		T34	2
valid_sources[0x07]	17954	1			T25	1		T28	2		T30	2
valid_sources[0x08]	17788	1			T28	6		T29	5		T60	3
valid_sources[0x09]	23574	1			T24	1		T26	2		T30	2
valid_sources[0x0a]	17553	1			T24	1		T25	2		T26	2
valid_sources[0x0b]	19164	1			T24	1		T28	1		T29	1
valid_sources[0x0c]	20614	1			T26	1		T29	3		T30	1
valid_sources[0x0d]	18165	1			T26	14		T28	1		T29	4
valid_sources[0x0e]	17970	1			T30	2		T60	2		T62	2
valid_sources[0x0f]	142881	1			T29	16		T60	1		T34	3
valid_sources[0x10]	18159	1			T24	2		T28	2		T60	2
valid_sources[0x11]	17500	1			T25	5		T28	1		T29	3
valid_sources[0x12]	19081	1			T30	1		T61	3		T63	5
valid_sources[0x13]	19464	1			T28	1		T30	2		T60	1
valid_sources[0x14]	19658	1			T24	1		T25	1		T32	1
valid_sources[0x15]	17655	1			T28	2		T29	1		T30	5
valid_sources[0x16]	41772	1			T24	1		T28	2		T30	5
valid_sources[0x17]	18138	1			T26	4		T28	1		T30	1
valid_sources[0x18]	20426	1			T28	3		T30	4		T32	2
valid_sources[0x19]	18574	1			T24	1		T30	1		T60	1
valid_sources[0x1a]	17422	1			T24	1		T28	3		T29	4
valid_sources[0x1b]	17495	1			T29	11		T30	2		T60	1
valid_sources[0x1c]	22630	1			T24	1		T28	1		T29	2
valid_sources[0x1d]	18020	1			T24	1		T30	3		T61	5
valid_sources[0x1e]	18409	1			T29	1		T30	2		T60	2
valid_sources[0x1f]	17434	1			T30	2		T61	14		T62	1
valid_sources[0x20]	20296	1			T30	1		T60	1		T62	7
valid_sources[0x21]	22202	1			T29	1		T30	1		T60	2
valid_sources[0x22]	17810	1			T26	2		T28	3		T30	1
valid_sources[0x23]	22226	1			T24	1		T26	11		T28	2
valid_sources[0x24]	17408	1			T29	5		T60	2		T62	5
valid_sources[0x25]	18532	1			T26	2		T28	2		T29	7
valid_sources[0x26]	23977	1			T30	3		T61	4		T64	3
valid_sources[0x27]	116871	1			T24	1		T28	2		T30	3
valid_sources[0x28]	17528	1			T30	3		T32	1		T61	1
valid_sources[0x29]	17988	1			T28	4		T30	1		T60	2
valid_sources[0x2a]	93752	1			T24	2		T28	1		T29	1
valid_sources[0x2b]	17651	1			T24	2		T29	6		T30	2
valid_sources[0x2c]	18112	1			T30	1		T62	2		T35	8
valid_sources[0x2d]	17879	1			T28	1		T30	1		T61	2
valid_sources[0x2e]	20965	1			T26	9		T29	2		T30	2
valid_sources[0x2f]	18237	1			T25	1		T60	1		T34	1
valid_sources[0x30]	17525	1			T26	3		T29	6		T30	4
valid_sources[0x31]	17909	1			T25	2		T28	3		T30	2
valid_sources[0x32]	17578	1			T28	1		T29	4		T61	2
valid_sources[0x33]	19730	1			T25	10		T28	1		T30	3
valid_sources[0x34]	18369	1			T25	3		T28	8		T60	2
valid_sources[0x35]	17767	1			T25	2		T29	2		T30	2
valid_sources[0x36]	17912	1			T24	1		T26	4		T29	3
valid_sources[0x37]	17976	1			T29	4		T30	2		T61	7
valid_sources[0x38]	20217	1			T24	4		T28	1		T30	2
valid_sources[0x39]	18189	1			T30	3		T34	2		T62	2
valid_sources[0x3a]	19292	1			T25	15		T28	2		T30	1
valid_sources[0x3b]	18081	1			T26	9		T34	2		T62	1
valid_sources[0x3c]	21839	1			T24	1		T28	1		T29	2
valid_sources[0x3d]	17702	1			T29	5		T30	4		T34	2
valid_sources[0x3e]	18418	1			T26	3		T60	1		T61	5
valid_sources[0x3f]	18221	1			T25	12		T29	8		T30	2
valid_sources[0x40]	70534	1			T62	1		T64	5		T35	7
valid_sources[0x41]	17460	1			T30	3		T61	7		T35	8
valid_sources[0x42]	18653	1			T60	1		T61	1		T34	3
valid_sources[0x43]	20166	1			T60	1		T61	4		T34	2
valid_sources[0x44]	17664	1			T24	1		T26	20		T28	1
valid_sources[0x45]	20892	1			T24	1		T28	2		T29	2
valid_sources[0x46]	61434	1			T60	4		T61	9		T63	5
valid_sources[0x47]	19551	1			T29	4		T30	3		T61	3
valid_sources[0x48]	19555	1			T24	1		T26	3		T30	1
valid_sources[0x49]	18225	1			T26	1		T30	1		T60	2
valid_sources[0x4a]	17377	1			T24	1		T60	3		T61	1
valid_sources[0x4b]	18584	1			T25	11		T30	1		T61	6
valid_sources[0x4c]	159024	1			T28	2		T29	7		T30	5
valid_sources[0x4d]	17870	1			T24	1		T26	10		T29	2
valid_sources[0x4e]	20753	1			T24	2		T25	13		T28	1
valid_sources[0x4f]	17894	1			T25	4		T28	4		T34	2
valid_sources[0x50]	17433	1			T26	51		T29	6		T61	1
valid_sources[0x51]	17949	1			T24	1		T28	3		T30	1
valid_sources[0x52]	18407	1			T62	3		T63	10		T35	4
valid_sources[0x53]	17608	1			T24	1		T28	1		T30	2
valid_sources[0x54]	17899	1			T26	2		T28	3		T29	6
valid_sources[0x55]	18108	1			T25	2		T26	11		T28	1
valid_sources[0x56]	18289	1			T24	3		T30	1		T60	1
valid_sources[0x57]	18195	1			T26	1		T30	1		T60	1
valid_sources[0x58]	20834	1			T29	14		T30	1		T60	1
valid_sources[0x59]	17941	1			T24	1		T25	9		T30	2
valid_sources[0x5a]	19657	1			T26	13		T28	2		T29	9
valid_sources[0x5b]	18198	1			T24	2		T28	6		T29	7
valid_sources[0x5c]	18642	1			T29	1		T61	3		T62	3
valid_sources[0x5d]	17862	1			T26	3		T28	1		T29	3
valid_sources[0x5e]	17177	1			T24	2		T29	6		T61	1
valid_sources[0x5f]	18193	1			T30	2		T61	2		T62	1
valid_sources[0x60]	19281	1			T24	1		T28	1		T30	1
valid_sources[0x61]	18797	1			T28	2		T29	1		T60	2
valid_sources[0x62]	18523	1			T30	3		T32	1		T60	4
valid_sources[0x63]	18467	1			T25	6		T29	1		T61	3
valid_sources[0x64]	17958	1			T26	1		T28	2		T29	6
valid_sources[0x65]	18219	1			T28	1		T29	2		T34	1
valid_sources[0x66]	17044	1			T61	4		T34	1		T62	3
valid_sources[0x67]	17443	1			T24	1		T28	3		T29	1
valid_sources[0x68]	19502	1			T29	9		T30	1		T61	3
valid_sources[0x69]	18085	1			T24	1		T30	2		T60	1
valid_sources[0x6a]	18441	1			T28	2		T30	1		T60	1
valid_sources[0x6b]	17632	1			T30	2		T61	2		T34	1
valid_sources[0x6c]	17514	1			T29	4		T30	3		T32	1
valid_sources[0x6d]	19297	1			T25	2		T28	3		T29	2
valid_sources[0x6e]	18160	1			T24	1		T28	1		T29	3
valid_sources[0x6f]	17589	1			T24	2		T26	5		T28	1
valid_sources[0x70]	18061	1			T24	1		T61	4		T62	1
valid_sources[0x71]	17780	1			T28	1		T60	4		T61	1
valid_sources[0x72]	18341	1			T28	1		T30	2		T60	2
valid_sources[0x73]	17904	1			T28	2		T30	2		T60	1
valid_sources[0x74]	16938	1			T24	1		T30	1		T62	1
valid_sources[0x75]	18338	1			T24	2		T26	1		T28	1
valid_sources[0x76]	17980	1			T26	6		T28	2		T30	2
valid_sources[0x77]	17476	1			T24	1		T25	17		T28	1
valid_sources[0x78]	18392	1			T24	1		T29	2		T30	1
valid_sources[0x79]	19185	1			T28	1		T62	2		T63	2
valid_sources[0x7a]	17684	1			T24	1		T28	2		T30	3
valid_sources[0x7b]	61876	1			T28	1		T30	2		T60	1
valid_sources[0x7c]	17412	1			T26	18		T60	1		T61	2
valid_sources[0x7d]	18739	1			T24	4		T60	1		T62	2
valid_sources[0x7e]	19323	1			T28	1		T61	3		T62	1
valid_sources[0x7f]	119489	1			T29	3		T60	3		T61	5
valid_sources[0x80]	18938	1			T28	1		T29	2		T30	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1431648

1

T24

25

T25

18

T26

30

values[0x0]

all_enables

biggest_size

1724231

1

T24

32

T25

60

T26

167

values[0x1]

all_enables

biggest_size

1722532

1

T24

30

T25

86

T26

177