Unified Coverage Report :: Module :: gpio_csr_assert_fpv

Module : gpio_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/gpio-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_gpio_csr_assert_0/gpio_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gpio_csr_assert	85.71						85.71

---

Module Instance : tb.dut.gpio_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : gpio_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	6	85.71
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	6	85.71

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	50996724	0	0	0
ctrl_en_input_filter_rd_A	50996724	55710	0	0
intr_ctrl_en_falling_rd_A	50996724	56180	0	0
intr_ctrl_en_lvlhigh_rd_A	50996724	55991	0	0
intr_ctrl_en_lvllow_rd_A	50996724	56996	0	0
intr_ctrl_en_rising_rd_A	50996724	57281	0	0
intr_enable_rd_A	50996724	55906	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50996724	0	0	0

ctrl_en_input_filter_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50996724	55710	0	0
T1	29435	97	0	0
T2	0	129	0	0
T3	0	4	0	0
T4	0	386	0	0
T5	0	6	0	0
T6	0	51	0	0
T7	0	341	0	0
T8	0	272	0	0
T9	0	33	0	0
T10	0	1878	0	0
T11	10604	0	0	0
T12	4726	0	0	0
T13	6881	0	0	0
T14	7082	0	0	0
T15	12778	0	0	0
T16	755	0	0	0
T17	9957	0	0	0
T18	6729	0	0	0
T19	1141	0	0	0

intr_ctrl_en_falling_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50996724	56180	0	0
T1	29435	139	0	0
T2	0	115	0	0
T3	0	3	0	0
T4	0	438	0	0
T5	0	3	0	0
T6	0	49	0	0
T7	0	284	0	0
T8	0	313	0	0
T11	10604	0	0	0
T12	4726	0	0	0
T13	6881	0	0	0
T14	7082	0	0	0
T15	12778	0	0	0
T16	755	0	0	0
T17	9957	0	0	0
T18	6729	0	0	0
T19	1141	0	0	0
T20	0	7	0	0
T21	0	4	0	0

intr_ctrl_en_lvlhigh_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50996724	55991	0	0
T1	29435	93	0	0
T2	0	139	0	0
T4	0	340	0	0
T6	0	48	0	0
T7	0	332	0	0
T8	0	253	0	0
T9	0	9	0	0
T10	0	2100	0	0
T11	10604	0	0	0
T12	4726	0	0	0
T13	6881	0	0	0
T14	7082	0	0	0
T15	12778	0	0	0
T16	755	0	0	0
T17	9957	0	0	0
T18	6729	0	0	0
T19	1141	0	0	0
T21	0	3	0	0
T22	0	214	0	0

intr_ctrl_en_lvllow_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50996724	56996	0	0
T1	29435	85	0	0
T2	0	154	0	0
T4	0	528	0	0
T5	0	1	0	0
T6	0	46	0	0
T7	0	315	0	0
T8	0	233	0	0
T11	10604	0	0	0
T12	4726	0	0	0
T13	6881	0	0	0
T14	7082	0	0	0
T15	12778	0	0	0
T16	755	0	0	0
T17	9957	0	0	0
T18	6729	0	0	0
T19	1141	0	0	0
T20	0	4	0	0
T21	0	8	0	0
T23	0	3	0	0

intr_ctrl_en_rising_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50996724	57281	0	0
T1	29435	164	0	0
T2	0	151	0	0
T4	0	356	0	0
T6	0	77	0	0
T7	0	337	0	0
T8	0	238	0	0
T9	0	25	0	0
T10	0	2101	0	0
T11	10604	0	0	0
T12	4726	0	0	0
T13	6881	0	0	0
T14	7082	0	0	0
T15	12778	0	0	0
T16	755	0	0	0
T17	9957	0	0	0
T18	6729	0	0	0
T19	1141	0	0	0
T21	0	9	0	0
T22	0	225	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50996724	55906	0	0
T1	29435	109	0	0
T2	0	142	0	0
T4	0	449	0	0
T6	0	51	0	0
T7	0	378	0	0
T8	0	185	0	0
T9	0	16	0	0
T10	0	1921	0	0
T11	10604	0	0	0
T12	4726	0	0	0
T13	6881	0	0	0
T14	7082	0	0	0
T15	12778	0	0	0
T16	755	0	0	0
T17	9957	0	0	0
T18	6729	0	0	0
T19	1141	0	0	0
T21	0	1	0	0
T23	0	7	0	0