Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/gpio-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1184013	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4125594

1

T33

312

T34

444

T35

322

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2398253	1			T33	58		T34	170		T35	77
values[0x0]	1451965	1			T33	149		T34	184		T35	150
values[0x1]	1459389	1			T33	133		T34	172		T35	134

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	942003	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

4367604

1

T33

314

T34

455

T35

326

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	16598	1			T33	3		T34	6		T36	3
valid_sources[0x01]	19315	1			T40	2		T41	3		T22	2
valid_sources[0x02]	17382	1			T33	2		T34	2		T36	2
valid_sources[0x03]	17435	1			T33	2		T34	5		T36	1
valid_sources[0x04]	15547	1			T34	3		T36	4		T40	3
valid_sources[0x05]	17285	1			T33	2		T34	2		T40	1
valid_sources[0x06]	21805	1			T33	4		T34	5		T36	3
valid_sources[0x07]	16294	1			T33	2		T34	1		T36	1
valid_sources[0x08]	18531	1			T34	1		T35	13		T36	1
valid_sources[0x09]	18715	1			T33	1		T34	3		T36	1
valid_sources[0x0a]	20947	1			T33	2		T34	2		T35	19
valid_sources[0x0b]	17375	1			T33	2		T34	2		T40	4
valid_sources[0x0c]	16591	1			T33	1		T34	3		T36	2
valid_sources[0x0d]	16670	1			T33	4		T36	1		T40	1
valid_sources[0x0e]	17050	1			T34	4		T36	4		T38	4
valid_sources[0x0f]	135130	1			T33	4		T34	1		T40	2
valid_sources[0x10]	15976	1			T33	3		T34	2		T36	4
valid_sources[0x11]	15474	1			T33	2		T34	2		T38	2
valid_sources[0x12]	17253	1			T33	3		T34	5		T36	3
valid_sources[0x13]	17163	1			T33	1		T34	1		T36	6
valid_sources[0x14]	17455	1			T33	2		T34	4		T36	1
valid_sources[0x15]	17501	1			T34	1		T38	4		T40	5
valid_sources[0x16]	17337	1			T33	1		T34	2		T38	2
valid_sources[0x17]	16030	1			T33	1		T34	4		T35	4
valid_sources[0x18]	19801	1			T33	3		T34	2		T36	8
valid_sources[0x19]	15758	1			T33	2		T34	1		T41	4
valid_sources[0x1a]	16919	1			T33	1		T34	2		T36	1
valid_sources[0x1b]	15975	1			T33	1		T34	1		T36	2
valid_sources[0x1c]	19145	1			T34	1		T40	3		T22	1
valid_sources[0x1d]	17240	1			T33	1		T36	4		T38	3
valid_sources[0x1e]	15853	1			T33	1		T34	3		T40	1
valid_sources[0x1f]	19734	1			T34	2		T36	5		T40	2
valid_sources[0x20]	16976	1			T34	3		T41	1		T22	1
valid_sources[0x21]	16742	1			T33	2		T38	2		T40	1
valid_sources[0x22]	16003	1			T34	2		T41	1		T31	1
valid_sources[0x23]	17917	1			T34	1		T38	5		T40	4
valid_sources[0x24]	15684	1			T33	3		T34	2		T36	1
valid_sources[0x25]	17843	1			T34	2		T36	2		T40	2
valid_sources[0x26]	15683	1			T33	2		T34	2		T36	9
valid_sources[0x27]	17490	1			T33	1		T34	1		T36	1
valid_sources[0x28]	16496	1			T33	1		T34	3		T40	3
valid_sources[0x29]	16839	1			T38	2		T40	1		T41	3
valid_sources[0x2a]	24714	1			T33	2		T34	2		T36	4
valid_sources[0x2b]	17545	1			T36	2		T40	3		T41	8
valid_sources[0x2c]	18423	1			T33	3		T34	1		T36	7
valid_sources[0x2d]	22337	1			T33	1		T36	1		T38	2
valid_sources[0x2e]	19198	1			T33	2		T34	2		T35	48
valid_sources[0x2f]	16023	1			T34	1		T36	2		T38	2
valid_sources[0x30]	17217	1			T34	6		T36	4		T38	2
valid_sources[0x31]	15767	1			T33	1		T34	2		T38	2
valid_sources[0x32]	18137	1			T33	1		T34	3		T36	3
valid_sources[0x33]	17037	1			T34	1		T35	16		T36	2
valid_sources[0x34]	161533	1			T33	5		T34	1		T36	1
valid_sources[0x35]	120910	1			T33	3		T34	4		T38	10
valid_sources[0x36]	15389	1			T33	6		T34	3		T38	2
valid_sources[0x37]	17605	1			T34	2		T36	1		T38	1
valid_sources[0x38]	16610	1			T33	1		T34	4		T40	2
valid_sources[0x39]	17421	1			T38	1		T40	2		T41	11
valid_sources[0x3a]	16144	1			T33	6		T34	2		T38	2
valid_sources[0x3b]	15904	1			T36	3		T41	4		T31	2
valid_sources[0x3c]	17806	1			T34	1		T36	1		T40	2
valid_sources[0x3d]	18431	1			T33	1		T34	3		T36	2
valid_sources[0x3e]	17287	1			T33	2		T34	1		T36	3
valid_sources[0x3f]	94264	1			T33	3		T34	2		T36	1
valid_sources[0x40]	17286	1			T33	1		T34	1		T36	2
valid_sources[0x41]	17458	1			T34	1		T40	7		T41	3
valid_sources[0x42]	15697	1			T34	2		T41	2		T31	3
valid_sources[0x43]	17228	1			T33	1		T34	3		T36	1
valid_sources[0x44]	18617	1			T34	2		T38	7		T40	5
valid_sources[0x45]	17043	1			T33	3		T34	2		T36	2
valid_sources[0x46]	17586	1			T33	1		T34	2		T38	1
valid_sources[0x47]	16360	1			T34	3		T36	1		T38	5
valid_sources[0x48]	16464	1			T33	1		T34	6		T38	1
valid_sources[0x49]	17716	1			T38	2		T40	5		T41	1
valid_sources[0x4a]	16155	1			T33	1		T34	2		T36	1
valid_sources[0x4b]	18545	1			T34	1		T35	12		T36	2
valid_sources[0x4c]	17324	1			T33	1		T34	4		T35	12
valid_sources[0x4d]	18955	1			T34	2		T38	1		T40	2
valid_sources[0x4e]	16870	1			T33	1		T34	2		T36	4
valid_sources[0x4f]	17084	1			T33	1		T35	7		T36	1
valid_sources[0x50]	17322	1			T34	3		T36	3		T40	2
valid_sources[0x51]	16235	1			T34	1		T36	1		T38	1
valid_sources[0x52]	18412	1			T33	1		T34	4		T36	2
valid_sources[0x53]	19949	1			T34	3		T38	3		T40	4
valid_sources[0x54]	18462	1			T34	1		T38	5		T40	3
valid_sources[0x55]	20161	1			T34	2		T35	6		T38	3
valid_sources[0x56]	21219	1			T34	1		T36	1		T40	6
valid_sources[0x57]	15808	1			T34	5		T38	1		T40	5
valid_sources[0x58]	19531	1			T33	3		T35	38		T36	1
valid_sources[0x59]	15578	1			T33	4		T34	5		T35	10
valid_sources[0x5a]	87675	1			T33	1		T34	3		T36	1
valid_sources[0x5b]	17316	1			T33	1		T36	1		T31	5
valid_sources[0x5c]	64080	1			T33	1		T34	3		T36	2
valid_sources[0x5d]	21651	1			T34	5		T38	2		T40	3
valid_sources[0x5e]	16354	1			T33	1		T34	3		T38	1
valid_sources[0x5f]	22075	1			T33	1		T38	1		T40	6
valid_sources[0x60]	18935	1			T33	2		T34	4		T40	4
valid_sources[0x61]	16132	1			T33	1		T34	3		T36	4
valid_sources[0x62]	15967	1			T33	2		T34	2		T36	7
valid_sources[0x63]	15362	1			T33	2		T38	2		T40	2
valid_sources[0x64]	15469	1			T33	1		T34	2		T40	2
valid_sources[0x65]	18823	1			T34	2		T36	1		T40	4
valid_sources[0x66]	18028	1			T34	1		T35	2		T38	7
valid_sources[0x67]	17022	1			T33	3		T34	4		T36	3
valid_sources[0x68]	16178	1			T33	2		T34	1		T38	1
valid_sources[0x69]	19290	1			T33	2		T35	21		T40	1
valid_sources[0x6a]	17839	1			T33	2		T34	1		T36	4
valid_sources[0x6b]	17717	1			T34	1		T38	7		T41	1
valid_sources[0x6c]	17375	1			T34	2		T40	4		T41	1
valid_sources[0x6d]	19352	1			T33	1		T34	4		T36	1
valid_sources[0x6e]	16496	1			T33	2		T34	2		T38	1
valid_sources[0x6f]	20399	1			T33	1		T34	3		T35	36
valid_sources[0x70]	15655	1			T33	1		T34	3		T36	1
valid_sources[0x71]	15690	1			T33	2		T36	2		T40	1
valid_sources[0x72]	20887	1			T33	5		T34	1		T35	13
valid_sources[0x73]	17825	1			T34	1		T40	2		T41	5
valid_sources[0x74]	108813	1			T33	2		T34	1		T36	2
valid_sources[0x75]	16857	1			T34	4		T36	1		T38	2
valid_sources[0x76]	15738	1			T33	6		T34	6		T36	1
valid_sources[0x77]	16592	1			T33	1		T34	2		T38	1
valid_sources[0x78]	19986	1			T33	2		T34	3		T38	1
valid_sources[0x79]	17672	1			T33	2		T34	2		T38	3
valid_sources[0x7a]	17789	1			T33	2		T34	2		T36	2
valid_sources[0x7b]	19784	1			T33	1		T34	2		T36	1
valid_sources[0x7c]	17262	1			T33	3		T34	4		T35	12
valid_sources[0x7d]	19563	1			T34	1		T36	1		T40	5
valid_sources[0x7e]	16139	1			T33	1		T34	4		T38	2
valid_sources[0x7f]	16935	1			T33	3		T35	9		T36	1
valid_sources[0x80]	20359	1			T34	4		T40	1		T41	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1224823

1

T33

30

T34

88

T35

38

values[0x0]

all_enables

biggest_size

1450693

1

T33

149

T34

184

T35

150

values[0x1]

all_enables

biggest_size

1450078

1

T33

133

T34

172

T35

134