Unified Coverage Report :: Module :: gpio_csr_assert_fpv

Module : gpio_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/gpio-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_gpio_csr_assert_0/gpio_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gpio_csr_assert	85.71						85.71

---

Module Instance : tb.dut.gpio_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : gpio_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	6	85.71
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	6	85.71

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	42267277	0	0	0
ctrl_en_input_filter_rd_A	42267277	29124	0	0
intr_ctrl_en_falling_rd_A	42267277	30508	0	0
intr_ctrl_en_lvlhigh_rd_A	42267277	29315	0	0
intr_ctrl_en_lvllow_rd_A	42267277	29212	0	0
intr_ctrl_en_rising_rd_A	42267277	29326	0	0
intr_enable_rd_A	42267277	29471	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	42267277	0	0	0

ctrl_en_input_filter_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	42267277	29124	0	0
T1	55125	506	0	0
T2	7132	8	0	0
T3	0	665	0	0
T4	0	221	0	0
T5	0	7	0	0
T6	0	235	0	0
T7	0	29	0	0
T8	0	3277	0	0
T9	0	75	0	0
T10	0	256	0	0
T11	5601	0	0	0
T12	2297	0	0	0
T13	46381	0	0	0
T14	2769	0	0	0
T15	9054	0	0	0
T16	14418	0	0	0
T17	7999	0	0	0
T18	55885	0	0	0

intr_ctrl_en_falling_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	42267277	30508	0	0
T1	55125	433	0	0
T2	7132	0	0	0
T3	0	644	0	0
T4	0	216	0	0
T6	0	232	0	0
T7	0	57	0	0
T8	0	3140	0	0
T9	0	80	0	0
T10	0	339	0	0
T11	5601	0	0	0
T12	2297	0	0	0
T13	46381	0	0	0
T14	2769	0	0	0
T15	9054	0	0	0
T16	14418	0	0	0
T17	7999	0	0	0
T18	55885	0	0	0
T19	0	3	0	0
T20	0	937	0	0

intr_ctrl_en_lvlhigh_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	42267277	29315	0	0
T1	55125	472	0	0
T2	7132	2	0	0
T3	0	566	0	0
T4	0	208	0	0
T5	0	8	0	0
T6	0	252	0	0
T7	0	25	0	0
T8	0	3022	0	0
T9	0	98	0	0
T11	5601	0	0	0
T12	2297	0	0	0
T13	46381	0	0	0
T14	2769	0	0	0
T15	9054	0	0	0
T16	14418	0	0	0
T17	7999	0	0	0
T18	55885	0	0	0
T21	0	8	0	0

intr_ctrl_en_lvllow_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	42267277	29212	0	0
T1	0	448	0	0
T3	0	522	0	0
T4	0	291	0	0
T5	0	9	0	0
T6	0	239	0	0
T7	0	25	0	0
T8	0	2862	0	0
T9	0	103	0	0
T21	0	4	0	0
T22	6433	4	0	0
T23	5526	0	0	0
T24	1227	0	0	0
T25	3071	0	0	0
T26	3929	0	0	0
T27	1152	0	0	0
T28	3725	0	0	0
T29	2870	0	0	0
T30	7800	0	0	0
T31	5438	0	0	0

intr_ctrl_en_rising_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	42267277	29326	0	0
T1	0	526	0	0
T2	0	8	0	0
T3	0	540	0	0
T4	0	242	0	0
T6	0	227	0	0
T7	0	33	0	0
T8	0	2872	0	0
T19	0	5	0	0
T22	6433	8	0	0
T23	5526	0	0	0
T24	1227	0	0	0
T25	3071	0	0	0
T26	3929	0	0	0
T27	1152	0	0	0
T28	3725	0	0	0
T29	2870	0	0	0
T30	7800	0	0	0
T31	5438	0	0	0
T32	0	3	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	42267277	29471	0	0
T1	0	456	0	0
T3	0	610	0	0
T4	0	154	0	0
T6	0	232	0	0
T7	0	28	0	0
T8	0	2906	0	0
T9	0	96	0	0
T10	0	279	0	0
T20	0	820	0	0
T22	6433	5	0	0
T23	5526	0	0	0
T24	1227	0	0	0
T25	3071	0	0	0
T26	3929	0	0	0
T27	1152	0	0	0
T28	3725	0	0	0
T29	2870	0	0	0
T30	7800	0	0	0
T31	5438	0	0	0