Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/gpio-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1355717	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4762194

1

T25

302

T26

94

T27

358

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2749140	1			T25	60		T26	98		T27	93
values[0x0]	1677978	1			T25	155		T26	17		T27	179
values[0x1]	1690793	1			T25	117		T26	29		T27	128

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1078585	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5039326

1

T25

308

T26

101

T27

369

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	18398	1			T26	1		T27	5		T31	8
valid_sources[0x01]	18636	1			T29	2		T31	2		T32	1
valid_sources[0x02]	18922	1			T12	2		T13	5		T15	5
valid_sources[0x03]	19747	1			T26	1		T27	7		T29	4
valid_sources[0x04]	18874	1			T31	10		T1	4		T12	1
valid_sources[0x05]	77624	1			T27	1		T29	4		T31	11
valid_sources[0x06]	19164	1			T28	9		T29	3		T12	4
valid_sources[0x07]	18187	1			T26	1		T29	7		T31	2
valid_sources[0x08]	18590	1			T29	2		T31	11		T1	3
valid_sources[0x09]	117484	1			T27	1		T29	3		T31	6
valid_sources[0x0a]	69261	1			T27	2		T29	1		T31	1
valid_sources[0x0b]	41730	1			T26	1		T27	1		T29	3
valid_sources[0x0c]	20010	1			T26	2		T29	1		T1	1
valid_sources[0x0d]	23555	1			T27	2		T29	1		T31	3
valid_sources[0x0e]	19042	1			T27	3		T29	1		T31	3
valid_sources[0x0f]	21628	1			T29	5		T12	1		T19	2
valid_sources[0x10]	20400	1			T26	2		T27	2		T29	2
valid_sources[0x11]	18575	1			T26	2		T29	4		T31	4
valid_sources[0x12]	21585	1			T26	1		T27	1		T29	3
valid_sources[0x13]	22903	1			T26	1		T27	2		T29	2
valid_sources[0x14]	21012	1			T26	1		T27	1		T29	3
valid_sources[0x15]	20061	1			T27	1		T1	16		T12	2
valid_sources[0x16]	18845	1			T26	1		T27	1		T29	3
valid_sources[0x17]	20838	1			T26	2		T27	1		T29	2
valid_sources[0x18]	18988	1			T26	1		T31	1		T1	8
valid_sources[0x19]	21256	1			T26	3		T27	4		T31	11
valid_sources[0x1a]	23942	1			T29	3		T31	3		T1	3
valid_sources[0x1b]	20016	1			T27	3		T31	11		T1	38
valid_sources[0x1c]	19461	1			T26	1		T27	1		T29	1
valid_sources[0x1d]	18600	1			T26	1		T27	7		T29	3
valid_sources[0x1e]	18865	1			T29	1		T1	4		T11	1
valid_sources[0x1f]	18695	1			T26	2		T27	3		T29	2
valid_sources[0x20]	20526	1			T29	1		T31	8		T32	8
valid_sources[0x21]	20701	1			T27	4		T29	2		T1	6
valid_sources[0x22]	19054	1			T26	1		T27	1		T29	1
valid_sources[0x23]	18524	1			T27	6		T29	2		T31	4
valid_sources[0x24]	19637	1			T26	2		T29	5		T1	15
valid_sources[0x25]	19320	1			T29	1		T1	5		T12	2
valid_sources[0x26]	19718	1			T27	1		T29	1		T12	2
valid_sources[0x27]	18258	1			T26	1		T29	1		T31	2
valid_sources[0x28]	20316	1			T29	2		T31	5		T32	1
valid_sources[0x29]	19383	1			T26	2		T29	1		T1	8
valid_sources[0x2a]	18274	1			T27	3		T31	6		T1	13
valid_sources[0x2b]	21614	1			T27	1		T29	1		T31	1
valid_sources[0x2c]	18119	1			T29	2		T31	1		T1	3
valid_sources[0x2d]	19968	1			T29	3		T31	3		T11	2
valid_sources[0x2e]	19002	1			T29	2		T12	2		T15	1
valid_sources[0x2f]	19397	1			T27	1		T29	1		T31	4
valid_sources[0x30]	18602	1			T27	1		T29	1		T1	15
valid_sources[0x31]	221479	1			T27	3		T29	2		T31	1
valid_sources[0x32]	20882	1			T26	2		T27	1		T29	4
valid_sources[0x33]	18331	1			T26	1		T27	3		T29	3
valid_sources[0x34]	18812	1			T29	1		T31	4		T1	9
valid_sources[0x35]	19035	1			T27	1		T29	4		T31	1
valid_sources[0x36]	18374	1			T27	3		T29	1		T31	3
valid_sources[0x37]	21204	1			T26	2		T29	2		T32	5
valid_sources[0x38]	22467	1			T27	1		T32	4		T16	2
valid_sources[0x39]	18377	1			T29	1		T31	2		T1	15
valid_sources[0x3a]	19007	1			T26	1		T29	5		T31	8
valid_sources[0x3b]	18887	1			T26	1		T27	1		T29	2
valid_sources[0x3c]	18725	1			T27	1		T29	1		T31	4
valid_sources[0x3d]	23507	1			T29	2		T31	6		T11	6
valid_sources[0x3e]	20360	1			T29	1		T31	5		T12	1
valid_sources[0x3f]	19135	1			T27	1		T29	5		T1	4
valid_sources[0x40]	20543	1			T26	1		T29	4		T31	8
valid_sources[0x41]	21309	1			T27	1		T29	3		T1	1
valid_sources[0x42]	18492	1			T27	6		T1	2		T12	2
valid_sources[0x43]	24000	1			T26	1		T27	3		T1	1
valid_sources[0x44]	20830	1			T29	3		T1	4		T12	2
valid_sources[0x45]	18233	1			T27	3		T29	2		T1	10
valid_sources[0x46]	19731	1			T26	2		T29	2		T1	5
valid_sources[0x47]	23100	1			T29	7		T34	1056		T12	2
valid_sources[0x48]	18325	1			T26	1		T29	6		T31	5
valid_sources[0x49]	21055	1			T26	4		T27	6		T31	1
valid_sources[0x4a]	19420	1			T27	5		T29	3		T1	12
valid_sources[0x4b]	18536	1			T29	3		T1	10		T11	1
valid_sources[0x4c]	17862	1			T27	2		T29	3		T1	8
valid_sources[0x4d]	39201	1			T26	1		T29	1		T31	6
valid_sources[0x4e]	20890	1			T26	1		T29	2		T31	13
valid_sources[0x4f]	19159	1			T26	1		T27	1		T29	6
valid_sources[0x50]	18821	1			T27	2		T29	1		T31	5
valid_sources[0x51]	24132	1			T27	3		T32	1		T33	24
valid_sources[0x52]	21210	1			T27	12		T29	1		T11	4
valid_sources[0x53]	26817	1			T29	1		T32	1		T11	2
valid_sources[0x54]	19306	1			T29	1		T31	6		T1	1
valid_sources[0x55]	19410	1			T26	1		T27	2		T29	4
valid_sources[0x56]	18436	1			T26	2		T29	1		T31	3
valid_sources[0x57]	18803	1			T26	1		T27	4		T29	2
valid_sources[0x58]	18524	1			T26	3		T27	6		T29	2
valid_sources[0x59]	18712	1			T27	3		T29	4		T31	1
valid_sources[0x5a]	18848	1			T27	3		T31	1		T1	1
valid_sources[0x5b]	19574	1			T29	3		T31	4		T12	1
valid_sources[0x5c]	18697	1			T26	2		T28	16		T29	5
valid_sources[0x5d]	18513	1			T26	1		T27	1		T29	2
valid_sources[0x5e]	19298	1			T27	5		T29	3		T31	2
valid_sources[0x5f]	20028	1			T29	2		T31	5		T32	9
valid_sources[0x60]	24249	1			T27	1		T29	2		T1	2
valid_sources[0x61]	18041	1			T26	1		T29	1		T31	1
valid_sources[0x62]	22279	1			T26	1		T12	3		T16	5
valid_sources[0x63]	18323	1			T29	2		T31	6		T32	4
valid_sources[0x64]	20513	1			T26	1		T29	3		T1	6
valid_sources[0x65]	19388	1			T29	3		T31	1		T1	12
valid_sources[0x66]	22363	1			T27	5		T29	2		T31	3
valid_sources[0x67]	20230	1			T29	1		T32	8		T1	23
valid_sources[0x68]	18015	1			T27	3		T29	1		T32	1
valid_sources[0x69]	18535	1			T27	1		T29	1		T31	1
valid_sources[0x6a]	19202	1			T26	4		T27	2		T29	3
valid_sources[0x6b]	18200	1			T26	1		T29	2		T31	1
valid_sources[0x6c]	21574	1			T26	1		T27	6		T29	4
valid_sources[0x6d]	18722	1			T26	1		T29	2		T12	1
valid_sources[0x6e]	61645	1			T27	6		T31	3		T12	1
valid_sources[0x6f]	18237	1			T31	1		T1	3		T11	1
valid_sources[0x70]	22800	1			T27	7		T29	2		T31	17
valid_sources[0x71]	21574	1			T26	1		T29	2		T31	1
valid_sources[0x72]	19322	1			T26	2		T27	1		T29	1
valid_sources[0x73]	18727	1			T29	3		T31	3		T1	16
valid_sources[0x74]	18463	1			T29	1		T1	1		T12	1
valid_sources[0x75]	19254	1			T26	1		T27	2		T29	1
valid_sources[0x76]	20564	1			T29	3		T31	2		T1	5
valid_sources[0x77]	22487	1			T26	1		T27	1		T31	6
valid_sources[0x78]	18667	1			T27	7		T29	3		T1	3
valid_sources[0x79]	18839	1			T26	1		T29	3		T31	1
valid_sources[0x7a]	20001	1			T26	2		T27	1		T29	3
valid_sources[0x7b]	21153	1			T29	1		T31	2		T1	9
valid_sources[0x7c]	18987	1			T29	1		T31	2		T32	2
valid_sources[0x7d]	23709	1			T26	1		T27	1		T29	2
valid_sources[0x7e]	19600	1			T26	1		T27	2		T29	3
valid_sources[0x7f]	19053	1			T26	1		T27	8		T29	2
valid_sources[0x80]	17817	1			T26	1		T27	7		T29	5

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1407103

1

T25

30

T26

48

T27

51

values[0x0]

all_enables

biggest_size

1676450

1

T25

155

T26

17

T27

179

values[0x1]

all_enables

biggest_size

1678641

1

T25

117

T26

29

T27

128