Unified Coverage Report :: Module :: gpio_csr_assert_fpv

Module : gpio_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/gpio-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_gpio_csr_assert_0/gpio_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gpio_csr_assert	85.71						85.71

---

Module Instance : tb.dut.gpio_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : gpio_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	6	85.71
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	6	85.71

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	48912300	0	0	0
ctrl_en_input_filter_rd_A	48912300	46753	0	0
intr_ctrl_en_falling_rd_A	48912300	48356	0	0
intr_ctrl_en_lvlhigh_rd_A	48912300	48478	0	0
intr_ctrl_en_lvllow_rd_A	48912300	47017	0	0
intr_ctrl_en_rising_rd_A	48912300	47856	0	0
intr_enable_rd_A	48912300	47513	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	48912300	0	0	0

ctrl_en_input_filter_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	48912300	46753	0	0
T1	16042	70	0	0
T2	0	704	0	0
T3	0	139	0	0
T4	0	24	0	0
T5	0	378	0	0
T6	0	840	0	0
T7	0	6	0	0
T8	0	4	0	0
T9	0	1095	0	0
T10	0	2224	0	0
T11	6974	0	0	0
T12	4330	0	0	0
T13	3844	0	0	0
T14	1708	0	0	0
T15	6005	0	0	0
T16	4883	0	0	0
T17	1856	0	0	0
T18	5516	0	0	0
T19	8752	0	0	0

intr_ctrl_en_falling_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	48912300	48356	0	0
T1	16042	60	0	0
T2	0	705	0	0
T3	0	194	0	0
T4	0	38	0	0
T5	0	341	0	0
T6	0	837	0	0
T8	0	4	0	0
T9	0	1428	0	0
T10	0	2267	0	0
T11	6974	0	0	0
T12	4330	0	0	0
T13	3844	0	0	0
T14	1708	0	0	0
T15	6005	0	0	0
T16	4883	0	0	0
T17	1856	0	0	0
T18	5516	0	0	0
T19	8752	0	0	0
T20	0	223	0	0

intr_ctrl_en_lvlhigh_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	48912300	48478	0	0
T1	16042	83	0	0
T2	0	788	0	0
T3	0	215	0	0
T4	0	52	0	0
T5	0	380	0	0
T6	0	838	0	0
T8	0	3	0	0
T9	0	1329	0	0
T10	0	2349	0	0
T11	6974	0	0	0
T12	4330	0	0	0
T13	3844	0	0	0
T14	1708	0	0	0
T15	6005	0	0	0
T16	4883	0	0	0
T17	1856	0	0	0
T18	5516	0	0	0
T19	8752	0	0	0
T20	0	195	0	0

intr_ctrl_en_lvllow_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	48912300	47017	0	0
T1	16042	65	0	0
T2	0	797	0	0
T3	0	168	0	0
T4	0	58	0	0
T5	0	365	0	0
T6	0	887	0	0
T9	0	1181	0	0
T11	6974	0	0	0
T12	4330	0	0	0
T13	3844	0	0	0
T14	1708	0	0	0
T15	6005	0	0	0
T16	4883	0	0	0
T17	1856	0	0	0
T18	5516	0	0	0
T19	8752	0	0	0
T21	0	4	0	0
T22	0	6	0	0
T23	0	13	0	0

intr_ctrl_en_rising_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	48912300	47856	0	0
T1	16042	65	0	0
T2	0	1022	0	0
T3	0	240	0	0
T4	0	31	0	0
T5	0	416	0	0
T6	0	763	0	0
T9	0	1236	0	0
T10	0	2403	0	0
T11	6974	0	0	0
T12	4330	0	0	0
T13	3844	0	0	0
T14	1708	0	0	0
T15	6005	0	0	0
T16	4883	0	0	0
T17	1856	0	0	0
T18	5516	0	0	0
T19	8752	0	0	0
T20	0	205	0	0
T24	0	1	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	48912300	47513	0	0
T1	16042	80	0	0
T2	0	737	0	0
T3	0	210	0	0
T4	0	51	0	0
T5	0	329	0	0
T6	0	899	0	0
T7	0	8	0	0
T9	0	1239	0	0
T10	0	2351	0	0
T11	6974	0	0	0
T12	4330	0	0	0
T13	3844	0	0	0
T14	1708	0	0	0
T15	6005	0	0	0
T16	4883	0	0	0
T17	1856	0	0	0
T18	5516	0	0	0
T19	8752	0	0	0
T20	0	235	0	0