Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/gpio-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1370405	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4842286

1

T41

91

T42

113

T43

109

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2783680	1			T41	77		T42	31		T43	23
values[0x0]	1708377	1			T41	34		T42	51		T43	48
values[0x1]	1720634	1			T41	26		T42	49		T43	52

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1089524	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5123167

1

T41

98

T42

117

T43

112

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	21008	1			T11	2		T18	1		T32	9
valid_sources[0x01]	24604	1			T43	2		T18	1		T39	2
valid_sources[0x02]	20733	1			T45	1		T1	1		T39	3
valid_sources[0x03]	20646	1			T18	3		T32	21		T33	3
valid_sources[0x04]	23480	1			T43	1		T18	4		T39	1
valid_sources[0x05]	20327	1			T18	1		T3	2		T22	2
valid_sources[0x06]	19558	1			T39	3		T3	6		T28	1
valid_sources[0x07]	22022	1			T46	1		T1	3		T32	10
valid_sources[0x08]	22045	1			T43	1		T11	1		T13	2
valid_sources[0x09]	26488	1			T18	2		T35	16		T39	1
valid_sources[0x0a]	21901	1			T11	1		T13	3		T18	2
valid_sources[0x0b]	22344	1			T18	2		T39	4		T3	2
valid_sources[0x0c]	21896	1			T18	1		T32	6		T39	4
valid_sources[0x0d]	19437	1			T1	3		T11	2		T39	4
valid_sources[0x0e]	19200	1			T43	2		T45	1		T11	1
valid_sources[0x0f]	19643	1			T1	1		T13	1		T32	1
valid_sources[0x10]	19110	1			T43	3		T17	1		T32	4
valid_sources[0x11]	21579	1			T43	2		T11	1		T13	1
valid_sources[0x12]	19463	1			T11	1		T18	1		T3	4
valid_sources[0x13]	19649	1			T43	3		T18	2		T32	9
valid_sources[0x14]	21136	1			T1	1		T11	2		T2	21
valid_sources[0x15]	21190	1			T43	1		T1	4		T39	2
valid_sources[0x16]	22531	1			T35	5		T39	2		T3	5
valid_sources[0x17]	21443	1			T33	6		T35	6		T39	4
valid_sources[0x18]	20775	1			T43	2		T44	7		T12	652
valid_sources[0x19]	19626	1			T43	1		T11	3		T13	5
valid_sources[0x1a]	20295	1			T43	2		T18	1		T39	1
valid_sources[0x1b]	23539	1			T43	1		T1	3		T13	1
valid_sources[0x1c]	20584	1			T11	2		T18	5		T35	10
valid_sources[0x1d]	19294	1			T43	1		T18	4		T39	2
valid_sources[0x1e]	20014	1			T1	1		T13	2		T39	3
valid_sources[0x1f]	20705	1			T13	4		T18	7		T32	5
valid_sources[0x20]	20443	1			T11	2		T18	2		T39	6
valid_sources[0x21]	20180	1			T1	1		T11	2		T13	1
valid_sources[0x22]	20572	1			T17	2		T18	1		T32	3
valid_sources[0x23]	23415	1			T43	1		T1	2		T13	5
valid_sources[0x24]	19494	1			T43	2		T1	1		T11	4
valid_sources[0x25]	20518	1			T46	24		T1	1		T18	4
valid_sources[0x26]	19579	1			T42	9		T11	1		T13	2
valid_sources[0x27]	20516	1			T43	1		T1	1		T18	4
valid_sources[0x28]	23657	1			T42	6		T1	1		T18	1
valid_sources[0x29]	19235	1			T43	1		T1	4		T11	3
valid_sources[0x2a]	21644	1			T11	1		T18	4		T3	7
valid_sources[0x2b]	19469	1			T42	1		T11	2		T18	10
valid_sources[0x2c]	19411	1			T42	1		T1	1		T11	3
valid_sources[0x2d]	141636	1			T13	2		T18	3		T39	3
valid_sources[0x2e]	21218	1			T11	4		T17	1		T18	7
valid_sources[0x2f]	21962	1			T44	1		T1	1		T11	6
valid_sources[0x30]	128795	1			T44	1		T18	2		T3	3
valid_sources[0x31]	20072	1			T11	2		T18	5		T39	3
valid_sources[0x32]	21878	1			T18	1		T32	20		T39	1
valid_sources[0x33]	20978	1			T43	4		T46	20		T11	1
valid_sources[0x34]	23962	1			T11	1		T18	2		T3	7
valid_sources[0x35]	19971	1			T18	3		T35	19		T39	4
valid_sources[0x36]	23648	1			T13	1		T32	1		T39	2
valid_sources[0x37]	19051	1			T11	1		T13	1		T18	3
valid_sources[0x38]	20159	1			T43	7		T16	183		T18	4
valid_sources[0x39]	20905	1			T46	12		T1	3		T11	2
valid_sources[0x3a]	20097	1			T18	1		T35	65		T39	5
valid_sources[0x3b]	20686	1			T43	1		T18	2		T39	2
valid_sources[0x3c]	19123	1			T11	4		T18	3		T39	2
valid_sources[0x3d]	20677	1			T46	7		T13	1		T18	2
valid_sources[0x3e]	19152	1			T45	1		T1	4		T11	2
valid_sources[0x3f]	19387	1			T44	2		T1	1		T13	4
valid_sources[0x40]	22414	1			T11	2		T17	1		T39	1
valid_sources[0x41]	20475	1			T1	1		T13	2		T18	2
valid_sources[0x42]	22578	1			T18	1		T33	2		T39	2
valid_sources[0x43]	19957	1			T43	2		T46	37		T1	2
valid_sources[0x44]	21488	1			T13	2		T17	1		T32	6
valid_sources[0x45]	22237	1			T43	1		T18	2		T39	3
valid_sources[0x46]	21214	1			T44	4		T1	1		T11	1
valid_sources[0x47]	22963	1			T1	1		T13	7		T18	2
valid_sources[0x48]	28550	1			T44	2		T1	1		T18	4
valid_sources[0x49]	24763	1			T42	1		T11	5		T13	1
valid_sources[0x4a]	20658	1			T42	5		T43	2		T39	2
valid_sources[0x4b]	19789	1			T1	1		T11	1		T18	1
valid_sources[0x4c]	20990	1			T1	4		T18	1		T32	8
valid_sources[0x4d]	22015	1			T18	11		T39	1		T3	1
valid_sources[0x4e]	23530	1			T1	3		T18	3		T39	7
valid_sources[0x4f]	20845	1			T11	3		T18	2		T39	3
valid_sources[0x50]	20602	1			T43	2		T11	1		T18	3
valid_sources[0x51]	19179	1			T43	1		T11	1		T39	5
valid_sources[0x52]	25124	1			T11	4		T18	1		T35	6
valid_sources[0x53]	21291	1			T11	4		T18	1		T39	4
valid_sources[0x54]	22797	1			T11	1		T18	1		T3	6
valid_sources[0x55]	21076	1			T13	1		T39	6		T3	12
valid_sources[0x56]	21798	1			T46	1		T18	1		T32	1
valid_sources[0x57]	20154	1			T11	2		T17	1		T18	2
valid_sources[0x58]	95011	1			T42	3		T11	5		T13	1
valid_sources[0x59]	21780	1			T43	2		T1	1		T13	1
valid_sources[0x5a]	20466	1			T43	1		T1	1		T39	2
valid_sources[0x5b]	20589	1			T1	2		T11	1		T18	2
valid_sources[0x5c]	18683	1			T44	24		T11	3		T18	2
valid_sources[0x5d]	25641	1			T46	5		T11	1		T18	1
valid_sources[0x5e]	23255	1			T18	1		T3	9		T28	4
valid_sources[0x5f]	26270	1			T18	1		T39	4		T3	12
valid_sources[0x60]	19857	1			T1	1		T11	1		T18	2
valid_sources[0x61]	22434	1			T11	1		T13	4		T17	1
valid_sources[0x62]	20008	1			T44	3		T1	1		T18	2
valid_sources[0x63]	20781	1			T11	1		T18	3		T2	12
valid_sources[0x64]	19582	1			T43	2		T11	1		T18	1
valid_sources[0x65]	21719	1			T44	12		T11	1		T18	3
valid_sources[0x66]	22046	1			T43	3		T46	9		T11	2
valid_sources[0x67]	20381	1			T43	1		T1	2		T11	1
valid_sources[0x68]	23966	1			T1	2		T11	1		T18	2
valid_sources[0x69]	18909	1			T44	8		T11	1		T18	3
valid_sources[0x6a]	25953	1			T44	9		T13	3		T18	3
valid_sources[0x6b]	23958	1			T43	1		T1	2		T18	2
valid_sources[0x6c]	22090	1			T42	3		T1	1		T18	1
valid_sources[0x6d]	20220	1			T41	137		T42	2		T18	1
valid_sources[0x6e]	22874	1			T42	1		T18	1		T32	13
valid_sources[0x6f]	19165	1			T11	1		T33	5		T39	4
valid_sources[0x70]	20386	1			T44	2		T18	1		T3	10
valid_sources[0x71]	19781	1			T18	2		T3	7		T29	5
valid_sources[0x72]	23223	1			T11	3		T18	6		T38	1
valid_sources[0x73]	20750	1			T11	2		T39	1		T3	3
valid_sources[0x74]	25435	1			T18	4		T39	4		T3	7
valid_sources[0x75]	24980	1			T18	3		T39	2		T3	3
valid_sources[0x76]	20555	1			T43	1		T18	8		T35	9
valid_sources[0x77]	20914	1			T44	3		T18	2		T39	3
valid_sources[0x78]	23437	1			T46	3		T1	2		T11	3
valid_sources[0x79]	22509	1			T44	12		T1	1		T18	2
valid_sources[0x7a]	19007	1			T18	2		T32	10		T3	6
valid_sources[0x7b]	20271	1			T11	1		T3	4		T24	1
valid_sources[0x7c]	19796	1			T43	1		T11	1		T17	1
valid_sources[0x7d]	23307	1			T1	1		T13	1		T18	6
valid_sources[0x7e]	20100	1			T18	6		T32	4		T35	1
valid_sources[0x7f]	21639	1			T11	1		T13	1		T18	2
valid_sources[0x80]	20811	1			T1	2		T11	2		T13	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1428279

1

T41

31

T42

13

T43

9

values[0x0]

all_enables

biggest_size

1706676

1

T41

34

T42

51

T43

48

values[0x1]

all_enables

biggest_size

1707331

1

T41

26

T42

49

T43

52