Unified Coverage Report :: Module :: gpio_csr_assert_fpv

Module : gpio_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/gpio-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_gpio_csr_assert_0/gpio_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gpio_csr_assert	85.71						85.71

---

Module Instance : tb.dut.gpio_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : gpio_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	6	85.71
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	6	85.71

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	47788124	0	0	0
ctrl_en_input_filter_rd_A	47788124	56219	0	0
intr_ctrl_en_falling_rd_A	47788124	55546	0	0
intr_ctrl_en_lvlhigh_rd_A	47788124	54907	0	0
intr_ctrl_en_lvllow_rd_A	47788124	55662	0	0
intr_ctrl_en_rising_rd_A	47788124	54614	0	0
intr_enable_rd_A	47788124	56829	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	47788124	0	0	0

ctrl_en_input_filter_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	47788124	56219	0	0
T1	4408	8	0	0
T2	6685	1	0	0
T3	0	95	0	0
T4	0	185	0	0
T5	0	315	0	0
T6	0	6	0	0
T7	0	6	0	0
T8	0	978	0	0
T9	0	56	0	0
T10	0	306	0	0
T11	1800	0	0	0
T12	8398	0	0	0
T13	1647	0	0	0
T14	5979	0	0	0
T15	2862	0	0	0
T16	3463	0	0	0
T17	1556	0	0	0
T18	3115	0	0	0

intr_ctrl_en_falling_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	47788124	55546	0	0
T3	18091	131	0	0
T4	0	174	0	0
T5	0	329	0	0
T6	0	2	0	0
T7	0	10	0	0
T8	0	1150	0	0
T9	0	86	0	0
T10	0	333	0	0
T19	0	3	0	0
T20	0	1513	0	0
T21	1579	0	0	0
T22	2598	0	0	0
T23	3886	0	0	0
T24	1489	0	0	0
T25	1743	0	0	0
T26	1456	0	0	0
T27	3541	0	0	0
T28	2794	0	0	0
T29	5500	0	0	0

intr_ctrl_en_lvlhigh_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	47788124	54907	0	0
T1	4408	2	0	0
T2	6685	4	0	0
T3	0	114	0	0
T4	0	279	0	0
T5	0	294	0	0
T8	0	1139	0	0
T9	0	29	0	0
T10	0	265	0	0
T11	1800	0	0	0
T12	8398	0	0	0
T13	1647	0	0	0
T14	5979	0	0	0
T15	2862	0	0	0
T16	3463	0	0	0
T17	1556	0	0	0
T18	3115	0	0	0
T30	0	1	0	0
T31	0	1	0	0

intr_ctrl_en_lvllow_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	47788124	55662	0	0
T2	6685	19	0	0
T3	18091	88	0	0
T4	0	158	0	0
T5	0	330	0	0
T6	0	2	0	0
T8	0	1060	0	0
T9	0	53	0	0
T10	0	305	0	0
T20	0	1626	0	0
T30	0	3	0	0
T32	5717	0	0	0
T33	1571	0	0	0
T34	8962	0	0	0
T35	7526	0	0	0
T36	636	0	0	0
T37	2000	0	0	0
T38	13762	0	0	0
T39	9867	0	0	0

intr_ctrl_en_rising_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	47788124	54614	0	0
T1	4408	6	0	0
T2	6685	0	0	0
T3	0	79	0	0
T4	0	188	0	0
T5	0	307	0	0
T6	0	6	0	0
T8	0	1192	0	0
T9	0	30	0	0
T10	0	373	0	0
T11	1800	0	0	0
T12	8398	0	0	0
T13	1647	0	0	0
T14	5979	0	0	0
T15	2862	0	0	0
T16	3463	0	0	0
T17	1556	0	0	0
T18	3115	0	0	0
T30	0	3	0	0
T40	0	4	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	47788124	56829	0	0
T3	18091	105	0	0
T4	0	207	0	0
T5	0	268	0	0
T6	0	4	0	0
T8	0	1238	0	0
T9	0	43	0	0
T10	0	304	0	0
T19	0	10	0	0
T20	0	1592	0	0
T21	1579	0	0	0
T22	2598	0	0	0
T23	3886	0	0	0
T24	1489	0	0	0
T25	1743	0	0	0
T26	1456	0	0	0
T27	3541	0	0	0
T28	2794	0	0	0
T29	5500	0	0	0
T31	0	1	0	0