Unified Coverage Report :: Module :: prim_subreg_ext

Module : prim_subreg_ext

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/gpio-sim-vcs/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg.u_masked_out_lower_mask	66.67	66.67
tb.dut.u_reg.u_masked_out_upper_mask	66.67	66.67
tb.dut.u_reg.u_masked_oe_lower_mask	75.00	75.00
tb.dut.u_reg.u_masked_oe_upper_mask	75.00	75.00
tb.dut.u_reg.u_intr_test	100.00	100.00
tb.dut.u_reg.u_alert_test	100.00	100.00
tb.dut.u_reg.u_direct_out	100.00	100.00
tb.dut.u_reg.u_masked_out_lower_data	100.00	100.00
tb.dut.u_reg.u_masked_out_upper_data	100.00	100.00
tb.dut.u_reg.u_direct_oe	100.00	100.00
tb.dut.u_reg.u_masked_oe_lower_data	100.00	100.00
tb.dut.u_reg.u_masked_oe_upper_data	100.00	100.00

---

Module Instance : tb.dut.u_reg.u_masked_out_lower_mask

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
66.67	66.67

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
66.67	66.67

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.75	100.00	99.01			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_masked_out_upper_mask

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
66.67	66.67

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
66.67	66.67

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.75	100.00	99.01			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_masked_oe_lower_mask

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.75	100.00	99.01			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_masked_oe_upper_mask

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.75	100.00	99.01			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_intr_test

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.75	100.00	99.01			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_alert_test

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.75	100.00	99.01			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_direct_out

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.75	100.00	99.01			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_masked_out_lower_data

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.75	100.00	99.01			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_masked_out_upper_data

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.75	100.00	99.01			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_direct_oe

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.75	100.00	99.01			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_masked_oe_lower_data

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.75	100.00	99.01			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_masked_oe_upper_data

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.75	100.00	99.01			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_subreg_ext

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T41 T42 T43 
27         1/1            assign qs = d;
           Tests:       T41 T42 T43 
28         1/1            assign q = wd;
           Tests:       T41 T42 T43 
29         1/1            assign qe = we;
           Tests:       T41 T45 T1 
30         1/1            assign qre = re;
           Tests:       T44 T1 T16 

Line Coverage for Instance : tb.dut.u_reg.u_masked_out_lower_mask

	Line No.	Total	Covered	Percent
TOTAL		3	2	66.67
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	0	0
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	0	0

25                        // between qs and ds
26         0/1     ==>    assign ds = d;
27         excluded       assign qs = d;
Exclude Annotation: [UNR]
28         1/1            assign q = wd;
           Tests:       T41 T42 T43 
29         1/1            assign qe = we;
           Tests:       T42 T43 T44 
30         unreachable    assign qre = re;

Line Coverage for Instance : tb.dut.u_reg.u_masked_out_upper_mask

	Line No.	Total	Covered	Percent
TOTAL		3	2	66.67
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	0	0
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	0	0

25                        // between qs and ds
26         0/1     ==>    assign ds = d;
27         excluded       assign qs = d;
Exclude Annotation: [UNR]
28         1/1            assign q = wd;
           Tests:       T41 T42 T43 
29         1/1            assign qe = we;
           Tests:       T42 T43 T44 
30         unreachable    assign qre = re;

Line Coverage for Instance : tb.dut.u_reg.u_masked_oe_lower_mask

	Line No.	Total	Covered	Percent
TOTAL		4	3	75.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	0	0
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         0/1     ==>    assign ds = d;
27         excluded       assign qs = d;
Exclude Annotation: [UNR]
28         1/1            assign q = wd;
           Tests:       T41 T42 T43 
29         1/1            assign qe = we;
           Tests:       T42 T43 T44 
30         1/1            assign qre = re;
           Tests:       T44 T16 T33 

Line Coverage for Instance : tb.dut.u_reg.u_masked_oe_upper_mask

	Line No.	Total	Covered	Percent
TOTAL		4	3	75.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	0	0
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         0/1     ==>    assign ds = d;
27         excluded       assign qs = d;
Exclude Annotation: [UNR]
28         1/1            assign q = wd;
           Tests:       T41 T42 T43 
29         1/1            assign qe = we;
           Tests:       T42 T43 T44 
30         1/1            assign qre = re;
           Tests:       T44 T16 T33 

Line Coverage for Instance : tb.dut.u_reg.u_intr_test

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	26	0	0
CONT_ASSIGN	27	0	0
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	0	0

25                        // between qs and ds
26         unreachable    assign ds = d;
27         unreachable    assign qs = d;
28         1/1            assign q = wd;
           Tests:       T41 T42 T43 
29         1/1            assign qe = we;
           Tests:       T1 T2 T3 
30         unreachable    assign qre = re;

Line Coverage for Instance : tb.dut.u_reg.u_alert_test

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	26	0	0
CONT_ASSIGN	27	0	0
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	0	0

25                        // between qs and ds
26         unreachable    assign ds = d;
27         unreachable    assign qs = d;
28         1/1            assign q = wd;
           Tests:       T41 T42 T43 
29         1/1            assign qe = we;
           Tests:       T45 T17 T36 
30         unreachable    assign qre = re;

Line Coverage for Instance : tb.dut.u_reg.u_direct_out

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T41 T42 T43 
27         1/1            assign qs = d;
           Tests:       T41 T42 T43 
28         1/1            assign q = wd;
           Tests:       T41 T42 T43 
29         1/1            assign qe = we;
           Tests:       T41 T42 T43 
30         1/1            assign qre = re;
           Tests:       T44 T1 T16 

Line Coverage for Instance : tb.dut.u_reg.u_masked_out_lower_data

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T41 T42 T43 
27         1/1            assign qs = d;
           Tests:       T41 T42 T43 
28         1/1            assign q = wd;
           Tests:       T41 T42 T43 
29         1/1            assign qe = we;
           Tests:       T42 T43 T44 
30         1/1            assign qre = re;
           Tests:       T44 T16 T2 

Line Coverage for Instance : tb.dut.u_reg.u_masked_out_upper_data

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T41 T42 T43 
27         1/1            assign qs = d;
           Tests:       T41 T42 T43 
28         1/1            assign q = wd;
           Tests:       T41 T42 T43 
29         1/1            assign qe = we;
           Tests:       T42 T43 T44 
30         1/1            assign qre = re;
           Tests:       T44 T16 T33 

Line Coverage for Instance : tb.dut.u_reg.u_direct_oe

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T41 T42 T43 
27         1/1            assign qs = d;
           Tests:       T41 T42 T43 
28         1/1            assign q = wd;
           Tests:       T41 T42 T43 
29         1/1            assign qe = we;
           Tests:       T41 T42 T43 
30         1/1            assign qre = re;
           Tests:       T44 T16 T2 

Line Coverage for Instance : tb.dut.u_reg.u_masked_oe_lower_data

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T41 T42 T43 
27         1/1            assign qs = d;
           Tests:       T41 T42 T43 
28         1/1            assign q = wd;
           Tests:       T41 T42 T43 
29         1/1            assign qe = we;
           Tests:       T42 T43 T44 
30         1/1            assign qre = re;
           Tests:       T44 T16 T33 

Line Coverage for Instance : tb.dut.u_reg.u_masked_oe_upper_data

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T41 T42 T43 
27         1/1            assign qs = d;
           Tests:       T41 T42 T43 
28         1/1            assign q = wd;
           Tests:       T41 T42 T43 
29         1/1            assign qe = we;
           Tests:       T42 T43 T44 
30         1/1            assign qre = re;
           Tests:       T44 T16 T33