Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/gpio-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1488635	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

5322028

1

T25

192

T26

183

T27

112

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3030760	1			T25	48		T26	124		T27	83
values[0x0]	1881872	1			T25	70		T26	64		T27	46
values[0x1]	1898031	1			T25	99		T26	57		T27	32

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1181371	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5629292

1

T25

196

T26

190

T27

119

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	22236	1			T28	1		T30	1		T118	2
valid_sources[0x01]	21511	1			T28	2		T30	3		T33	2
valid_sources[0x02]	21548	1			T28	2		T29	10		T33	2
valid_sources[0x03]	20703	1			T29	9		T30	2		T33	4
valid_sources[0x04]	20550	1			T33	4		T118	2		T42	3
valid_sources[0x05]	20928	1			T28	2		T33	2		T60	2
valid_sources[0x06]	147690	1			T33	2		T118	2		T42	1
valid_sources[0x07]	23553	1			T28	1		T33	2		T118	1
valid_sources[0x08]	20714	1			T30	2		T33	1		T118	1
valid_sources[0x09]	20579	1			T28	1		T33	1		T42	2
valid_sources[0x0a]	20470	1			T28	1		T29	3		T33	3
valid_sources[0x0b]	21266	1			T28	1		T30	1		T33	2
valid_sources[0x0c]	19963	1			T29	11		T30	2		T33	1
valid_sources[0x0d]	21857	1			T28	1		T29	4		T33	3
valid_sources[0x0e]	20766	1			T28	1		T33	3		T42	2
valid_sources[0x0f]	19863	1			T118	8		T35	8		T61	5
valid_sources[0x10]	25414	1			T33	1		T42	2		T60	2
valid_sources[0x11]	20798	1			T28	1		T29	4		T33	1
valid_sources[0x12]	26882	1			T28	2		T30	1		T33	1
valid_sources[0x13]	154361	1			T28	2		T30	4		T118	6
valid_sources[0x14]	25321	1			T29	4		T42	2		T61	1
valid_sources[0x15]	21216	1			T28	1		T29	6		T33	4
valid_sources[0x16]	20475	1			T28	2		T29	10		T30	4
valid_sources[0x17]	21215	1			T30	2		T118	3		T42	1
valid_sources[0x18]	21588	1			T28	1		T118	5		T60	2
valid_sources[0x19]	20586	1			T28	3		T30	1		T33	1
valid_sources[0x1a]	20882	1			T30	3		T118	2		T42	3
valid_sources[0x1b]	20407	1			T118	4		T42	1		T60	3
valid_sources[0x1c]	19739	1			T28	2		T30	2		T31	34
valid_sources[0x1d]	27190	1			T30	2		T33	1		T44	1
valid_sources[0x1e]	20202	1			T28	1		T30	2		T33	1
valid_sources[0x1f]	20358	1			T28	2		T118	2		T35	2
valid_sources[0x20]	19794	1			T28	1		T29	7		T30	1
valid_sources[0x21]	22752	1			T28	2		T30	1		T118	7
valid_sources[0x22]	22250	1			T28	1		T33	2		T118	6
valid_sources[0x23]	22495	1			T29	5		T33	6		T42	5
valid_sources[0x24]	20356	1			T28	1		T33	1		T118	4
valid_sources[0x25]	20798	1			T28	2		T29	1		T30	1
valid_sources[0x26]	22415	1			T28	1		T33	1		T42	1
valid_sources[0x27]	20750	1			T33	2		T42	1		T35	2
valid_sources[0x28]	19773	1			T33	2		T42	5		T61	2
valid_sources[0x29]	20391	1			T30	4		T33	5		T118	6
valid_sources[0x2a]	19167	1			T33	2		T60	2		T35	12
valid_sources[0x2b]	23438	1			T30	10		T118	4		T35	3
valid_sources[0x2c]	19638	1			T28	4		T29	2		T30	1
valid_sources[0x2d]	22903	1			T28	2		T33	1		T34	105
valid_sources[0x2e]	19887	1			T28	2		T29	1		T30	4
valid_sources[0x2f]	20911	1			T29	3		T30	2		T33	1
valid_sources[0x30]	20819	1			T33	2		T118	4		T61	1
valid_sources[0x31]	22200	1			T29	7		T33	4		T118	1
valid_sources[0x32]	21854	1			T29	10		T31	33		T33	2
valid_sources[0x33]	24533	1			T30	1		T33	4		T118	5
valid_sources[0x34]	22708	1			T28	1		T30	3		T118	2
valid_sources[0x35]	21310	1			T29	3		T118	2		T42	3
valid_sources[0x36]	22460	1			T30	4		T33	2		T118	6
valid_sources[0x37]	21938	1			T28	1		T30	2		T118	11
valid_sources[0x38]	20102	1			T28	1		T29	3		T33	1
valid_sources[0x39]	24756	1			T118	2		T60	6		T35	2
valid_sources[0x3a]	20439	1			T33	3		T118	2		T42	1
valid_sources[0x3b]	27143	1			T30	2		T33	1		T118	4
valid_sources[0x3c]	22729	1			T118	13		T42	3		T60	4
valid_sources[0x3d]	20568	1			T30	1		T33	4		T35	2
valid_sources[0x3e]	137489	1			T28	1		T29	9		T33	1
valid_sources[0x3f]	22469	1			T28	1		T118	1		T35	3
valid_sources[0x40]	26411	1			T30	1		T42	2		T35	3
valid_sources[0x41]	53817	1			T28	1		T29	18		T33	2
valid_sources[0x42]	20669	1			T28	2		T29	13		T30	1
valid_sources[0x43]	20689	1			T30	1		T33	1		T118	2
valid_sources[0x44]	23587	1			T30	2		T33	1		T118	1
valid_sources[0x45]	22103	1			T28	1		T30	2		T42	1
valid_sources[0x46]	21682	1			T33	3		T118	1		T35	3
valid_sources[0x47]	23663	1			T29	13		T33	2		T118	4
valid_sources[0x48]	20782	1			T28	1		T33	2		T118	2
valid_sources[0x49]	20326	1			T29	7		T30	3		T33	2
valid_sources[0x4a]	21120	1			T28	1		T29	11		T33	2
valid_sources[0x4b]	19852	1			T30	2		T33	2		T118	1
valid_sources[0x4c]	21430	1			T29	6		T30	2		T33	1
valid_sources[0x4d]	19894	1			T118	2		T60	1		T35	3
valid_sources[0x4e]	21025	1			T33	1		T42	3		T35	6
valid_sources[0x4f]	21119	1			T30	5		T35	5		T61	4
valid_sources[0x50]	18821	1			T30	2		T33	1		T118	1
valid_sources[0x51]	20289	1			T28	1		T33	1		T118	9
valid_sources[0x52]	19865	1			T30	2		T33	1		T118	3
valid_sources[0x53]	22740	1			T33	1		T118	1		T42	6
valid_sources[0x54]	20636	1			T29	22		T33	1		T118	3
valid_sources[0x55]	20211	1			T28	2		T33	1		T118	7
valid_sources[0x56]	20432	1			T28	3		T33	1		T118	2
valid_sources[0x57]	22622	1			T28	1		T30	3		T33	5
valid_sources[0x58]	23104	1			T33	6		T118	1		T35	2
valid_sources[0x59]	19930	1			T28	2		T30	1		T118	1
valid_sources[0x5a]	21038	1			T31	14		T33	1		T35	1
valid_sources[0x5b]	23062	1			T28	1		T29	11		T30	1
valid_sources[0x5c]	20963	1			T28	3		T33	2		T118	7
valid_sources[0x5d]	26980	1			T28	1		T29	8		T31	15
valid_sources[0x5e]	20346	1			T28	1		T31	74		T33	1
valid_sources[0x5f]	22574	1			T33	3		T42	7		T60	1
valid_sources[0x60]	20122	1			T28	1		T29	26		T30	3
valid_sources[0x61]	62974	1			T33	1		T118	1		T42	1
valid_sources[0x62]	20068	1			T118	4		T35	12		T114	3
valid_sources[0x63]	21141	1			T28	1		T30	2		T33	2
valid_sources[0x64]	22433	1			T28	1		T30	3		T33	1
valid_sources[0x65]	20891	1			T33	1		T114	5		T116	5
valid_sources[0x66]	22461	1			T30	5		T33	4		T118	4
valid_sources[0x67]	26114	1			T28	2		T30	2		T33	1
valid_sources[0x68]	23543	1			T25	217		T28	1		T118	3
valid_sources[0x69]	25341	1			T33	1		T42	2		T60	3
valid_sources[0x6a]	164247	1			T28	2		T29	1		T118	1
valid_sources[0x6b]	21461	1			T30	2		T33	1		T118	5
valid_sources[0x6c]	20151	1			T30	2		T33	3		T118	1
valid_sources[0x6d]	21423	1			T28	1		T33	1		T35	4
valid_sources[0x6e]	23253	1			T118	5		T42	1		T60	1
valid_sources[0x6f]	23007	1			T30	2		T33	1		T118	3
valid_sources[0x70]	20215	1			T28	2		T30	1		T118	7
valid_sources[0x71]	22178	1			T28	1		T33	2		T118	2
valid_sources[0x72]	22592	1			T30	6		T35	4		T61	4
valid_sources[0x73]	20031	1			T33	1		T118	6		T60	3
valid_sources[0x74]	20298	1			T29	1		T30	2		T33	2
valid_sources[0x75]	26306	1			T118	2		T60	1		T35	14
valid_sources[0x76]	131666	1			T30	2		T118	4		T61	1
valid_sources[0x77]	20528	1			T30	2		T32	316		T47	3
valid_sources[0x78]	20217	1			T28	1		T30	3		T33	2
valid_sources[0x79]	20377	1			T33	1		T118	3		T61	3
valid_sources[0x7a]	23255	1			T28	1		T30	1		T33	1
valid_sources[0x7b]	20620	1			T29	8		T118	4		T35	2
valid_sources[0x7c]	20805	1			T33	2		T118	1		T42	2
valid_sources[0x7d]	23790	1			T28	3		T31	15		T33	2
valid_sources[0x7e]	20920	1			T28	1		T118	7		T42	1
valid_sources[0x7f]	23435	1			T33	1		T118	1		T42	2
valid_sources[0x80]	21048	1			T28	1		T29	2		T33	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1562417

1

T25

23

T26

62

T27

34

values[0x0]

all_enables

biggest_size

1879620

1

T25

70

T26

64

T27

46

values[0x1]

all_enables

biggest_size

1879991

1

T25

99

T26

57

T27

32