Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/gpio-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1233590	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4255016

1

T26

201

T27

129

T28

96

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2493934	1			T26	22		T27	24		T28	102
values[0x0]	1493996	1			T26	94		T27	50		T28	26
values[0x1]	1500676	1			T26	94		T27	64		T28	16

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	982279	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

4506327

1

T26

203

T27

131

T28

104

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	91993	1			T27	1		T29	3		T31	2
valid_sources[0x01]	121891	1			T26	1		T27	1		T34	2
valid_sources[0x02]	16609	1			T27	2		T34	1		T35	29
valid_sources[0x03]	18327	1			T26	1		T27	1		T29	8
valid_sources[0x04]	17904	1			T27	1		T31	4		T47	20
valid_sources[0x05]	16292	1			T27	2		T31	3		T47	16
valid_sources[0x06]	17738	1			T30	1		T31	3		T34	3
valid_sources[0x07]	17364	1			T27	1		T47	24		T42	2
valid_sources[0x08]	21345	1			T27	1		T31	1		T34	2
valid_sources[0x09]	18854	1			T31	3		T34	1		T47	23
valid_sources[0x0a]	19754	1			T29	11		T31	1		T47	14
valid_sources[0x0b]	17018	1			T34	1		T35	2		T47	21
valid_sources[0x0c]	16575	1			T26	1		T27	3		T31	1
valid_sources[0x0d]	17238	1			T26	1		T27	1		T31	3
valid_sources[0x0e]	21759	1			T26	4		T27	1		T31	2
valid_sources[0x0f]	17622	1			T29	5		T34	3		T47	18
valid_sources[0x10]	21232	1			T26	3		T27	2		T28	3
valid_sources[0x11]	18654	1			T26	2		T34	3		T47	20
valid_sources[0x12]	21998	1			T26	1		T27	1		T28	5
valid_sources[0x13]	16505	1			T27	3		T31	3		T34	1
valid_sources[0x14]	17291	1			T29	1		T34	1		T47	18
valid_sources[0x15]	16630	1			T31	3		T34	1		T47	19
valid_sources[0x16]	15810	1			T29	2		T31	1		T47	15
valid_sources[0x17]	18294	1			T26	2		T28	1		T35	16
valid_sources[0x18]	16289	1			T26	1		T31	2		T47	19
valid_sources[0x19]	67775	1			T26	1		T28	4		T29	5
valid_sources[0x1a]	18200	1			T29	2		T34	1		T47	11
valid_sources[0x1b]	18021	1			T26	1		T34	2		T47	25
valid_sources[0x1c]	18246	1			T29	2		T30	9		T34	1
valid_sources[0x1d]	16055	1			T26	2		T31	1		T34	2
valid_sources[0x1e]	18768	1			T27	2		T28	15		T47	16
valid_sources[0x1f]	19756	1			T26	1		T31	2		T47	12
valid_sources[0x20]	17069	1			T29	1		T31	1		T47	15
valid_sources[0x21]	16745	1			T31	2		T47	21		T43	5
valid_sources[0x22]	24086	1			T26	2		T27	1		T31	5
valid_sources[0x23]	16146	1			T26	1		T34	1		T47	18
valid_sources[0x24]	16183	1			T26	2		T27	2		T34	2
valid_sources[0x25]	17170	1			T27	1		T30	2		T35	4
valid_sources[0x26]	53008	1			T29	10		T31	2		T34	2
valid_sources[0x27]	16649	1			T34	5		T35	12		T47	13
valid_sources[0x28]	16409	1			T26	1		T31	3		T34	1
valid_sources[0x29]	17278	1			T26	3		T27	2		T31	1
valid_sources[0x2a]	19335	1			T26	2		T31	3		T34	1
valid_sources[0x2b]	20772	1			T27	3		T29	5		T31	2
valid_sources[0x2c]	17029	1			T26	3		T29	2		T31	2
valid_sources[0x2d]	16425	1			T34	2		T35	14		T47	25
valid_sources[0x2e]	17062	1			T30	7		T31	4		T47	18
valid_sources[0x2f]	18511	1			T26	1		T29	1		T34	1
valid_sources[0x30]	15606	1			T26	2		T28	3		T31	3
valid_sources[0x31]	17093	1			T27	1		T29	2		T47	13
valid_sources[0x32]	16124	1			T34	1		T47	18		T59	4
valid_sources[0x33]	16023	1			T28	1		T31	3		T47	13
valid_sources[0x34]	16525	1			T26	1		T31	1		T34	2
valid_sources[0x35]	17161	1			T28	4		T29	2		T34	2
valid_sources[0x36]	16505	1			T26	1		T47	27		T59	4
valid_sources[0x37]	68999	1			T30	2		T31	6		T34	1
valid_sources[0x38]	17341	1			T29	1		T31	2		T34	4
valid_sources[0x39]	17185	1			T34	3		T35	14		T47	15
valid_sources[0x3a]	19141	1			T26	1		T31	1		T34	3
valid_sources[0x3b]	17737	1			T27	4		T29	1		T30	2
valid_sources[0x3c]	16033	1			T28	1		T31	3		T34	1
valid_sources[0x3d]	19947	1			T27	1		T34	2		T35	57
valid_sources[0x3e]	16153	1			T27	1		T29	4		T34	2
valid_sources[0x3f]	21271	1			T34	2		T47	25		T59	2
valid_sources[0x40]	18354	1			T27	1		T34	1		T47	20
valid_sources[0x41]	186680	1			T26	1		T47	21		T60	1
valid_sources[0x42]	17367	1			T27	1		T47	16		T42	1
valid_sources[0x43]	16520	1			T31	2		T47	22		T59	1
valid_sources[0x44]	16221	1			T26	2		T28	1		T34	1
valid_sources[0x45]	15665	1			T29	2		T47	18		T42	1
valid_sources[0x46]	18005	1			T35	15		T47	16		T42	1
valid_sources[0x47]	18702	1			T31	1		T47	18		T60	3
valid_sources[0x48]	16374	1			T31	1		T47	26		T43	1
valid_sources[0x49]	22102	1			T47	14		T42	2		T60	2
valid_sources[0x4a]	17063	1			T28	1		T29	3		T31	1
valid_sources[0x4b]	20226	1			T27	2		T31	1		T47	14
valid_sources[0x4c]	16684	1			T27	1		T34	1		T47	26
valid_sources[0x4d]	16904	1			T26	1		T27	6		T31	1
valid_sources[0x4e]	22978	1			T27	1		T29	12		T31	2
valid_sources[0x4f]	20911	1			T26	5		T28	3		T31	1
valid_sources[0x50]	18274	1			T26	2		T27	1		T34	1
valid_sources[0x51]	16094	1			T26	2		T27	3		T29	1
valid_sources[0x52]	21703	1			T27	1		T30	8		T31	2
valid_sources[0x53]	16525	1			T26	1		T31	1		T34	3
valid_sources[0x54]	18876	1			T26	1		T27	1		T31	3
valid_sources[0x55]	17667	1			T34	1		T35	20		T47	21
valid_sources[0x56]	16948	1			T26	1		T30	4		T31	3
valid_sources[0x57]	18254	1			T28	2		T31	4		T34	1
valid_sources[0x58]	16322	1			T28	5		T31	1		T47	14
valid_sources[0x59]	16030	1			T29	6		T34	2		T47	18
valid_sources[0x5a]	21176	1			T26	2		T34	2		T47	17
valid_sources[0x5b]	24577	1			T26	3		T27	3		T29	2
valid_sources[0x5c]	17486	1			T29	4		T31	4		T35	64
valid_sources[0x5d]	19480	1			T30	1		T31	2		T34	2
valid_sources[0x5e]	16217	1			T26	1		T34	3		T47	22
valid_sources[0x5f]	16188	1			T26	2		T30	1		T31	1
valid_sources[0x60]	17839	1			T29	2		T47	13		T42	3
valid_sources[0x61]	16471	1			T31	3		T34	3		T35	1
valid_sources[0x62]	16741	1			T26	1		T29	6		T34	5
valid_sources[0x63]	16946	1			T27	1		T31	7		T34	1
valid_sources[0x64]	15986	1			T29	3		T31	2		T34	7
valid_sources[0x65]	18001	1			T27	1		T29	3		T31	3
valid_sources[0x66]	16553	1			T47	16		T60	2		T51	3
valid_sources[0x67]	25614	1			T29	3		T34	2		T47	14
valid_sources[0x68]	15640	1			T26	3		T31	3		T34	2
valid_sources[0x69]	16168	1			T34	1		T35	8		T47	13
valid_sources[0x6a]	18200	1			T27	1		T28	6		T34	1
valid_sources[0x6b]	16953	1			T29	3		T31	1		T47	19
valid_sources[0x6c]	27605	1			T29	3		T47	15		T59	4
valid_sources[0x6d]	16423	1			T27	2		T28	4		T31	3
valid_sources[0x6e]	16645	1			T26	2		T31	3		T47	18
valid_sources[0x6f]	17724	1			T26	1		T27	3		T34	4
valid_sources[0x70]	16636	1			T31	2		T47	25		T42	1
valid_sources[0x71]	19718	1			T26	7		T27	1		T34	3
valid_sources[0x72]	20291	1			T27	2		T29	5		T34	1
valid_sources[0x73]	16117	1			T27	1		T31	3		T34	2
valid_sources[0x74]	16283	1			T26	1		T31	3		T47	27
valid_sources[0x75]	16423	1			T27	1		T28	1		T29	4
valid_sources[0x76]	20305	1			T29	6		T30	3		T34	1
valid_sources[0x77]	17313	1			T29	3		T31	2		T34	2
valid_sources[0x78]	16728	1			T27	1		T31	2		T34	1
valid_sources[0x79]	16843	1			T27	1		T35	3		T47	23
valid_sources[0x7a]	18102	1			T29	2		T47	25		T59	1
valid_sources[0x7b]	16501	1			T26	1		T27	1		T47	18
valid_sources[0x7c]	16411	1			T28	2		T47	17		T42	2
valid_sources[0x7d]	16589	1			T47	16		T50	2		T60	1
valid_sources[0x7e]	19516	1			T27	1		T31	1		T34	5
valid_sources[0x7f]	16946	1			T27	2		T31	1		T34	2
valid_sources[0x80]	17438	1			T26	1		T27	1		T31	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1270270

1

T26

13

T27

15

T28

54

values[0x0]

all_enables

biggest_size

1492755

1

T26

94

T27

50

T28

26

values[0x1]

all_enables

biggest_size

1491991

1

T26

94

T27

64

T28

16