Unified Coverage Report :: Module :: prim_filter_ctr

Module : prim_filter_ctr

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/gpio-sim-vcs/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_filter[0].u_filter	100.00	100.00	100.00			100.00
tb.dut.gen_filter[1].u_filter	100.00	100.00	100.00			100.00
tb.dut.gen_filter[2].u_filter	100.00	100.00	100.00			100.00
tb.dut.gen_filter[3].u_filter	100.00	100.00	100.00			100.00
tb.dut.gen_filter[4].u_filter	100.00	100.00	100.00			100.00
tb.dut.gen_filter[5].u_filter	100.00	100.00	100.00			100.00
tb.dut.gen_filter[6].u_filter	100.00	100.00	100.00			100.00
tb.dut.gen_filter[7].u_filter	100.00	100.00	100.00			100.00
tb.dut.gen_filter[8].u_filter	100.00	100.00	100.00			100.00
tb.dut.gen_filter[9].u_filter	100.00	100.00	100.00			100.00
tb.dut.gen_filter[10].u_filter	100.00	100.00	100.00			100.00
tb.dut.gen_filter[11].u_filter	100.00	100.00	100.00			100.00
tb.dut.gen_filter[12].u_filter	100.00	100.00	100.00			100.00
tb.dut.gen_filter[13].u_filter	100.00	100.00	100.00			100.00
tb.dut.gen_filter[14].u_filter	100.00	100.00	100.00			100.00
tb.dut.gen_filter[15].u_filter	100.00	100.00	100.00			100.00
tb.dut.gen_filter[16].u_filter	100.00	100.00	100.00			100.00
tb.dut.gen_filter[17].u_filter	100.00	100.00	100.00			100.00
tb.dut.gen_filter[18].u_filter	100.00	100.00	100.00			100.00
tb.dut.gen_filter[19].u_filter	100.00	100.00	100.00			100.00
tb.dut.gen_filter[20].u_filter	100.00	100.00	100.00			100.00
tb.dut.gen_filter[21].u_filter	100.00	100.00	100.00			100.00
tb.dut.gen_filter[22].u_filter	100.00	100.00	100.00			100.00
tb.dut.gen_filter[23].u_filter	100.00	100.00	100.00			100.00
tb.dut.gen_filter[24].u_filter	100.00	100.00	100.00			100.00
tb.dut.gen_filter[25].u_filter	100.00	100.00	100.00			100.00
tb.dut.gen_filter[26].u_filter	100.00	100.00	100.00			100.00
tb.dut.gen_filter[27].u_filter	100.00	100.00	100.00			100.00
tb.dut.gen_filter[28].u_filter	100.00	100.00	100.00			100.00
tb.dut.gen_filter[29].u_filter	100.00	100.00	100.00			100.00
tb.dut.gen_filter[30].u_filter	100.00	100.00	100.00			100.00
tb.dut.gen_filter[31].u_filter	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut.gen_filter[0].u_filter

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_filter[1].u_filter

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_filter[2].u_filter

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_filter[3].u_filter

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_filter[4].u_filter

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_filter[5].u_filter

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_filter[6].u_filter

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_filter[7].u_filter

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_filter[8].u_filter

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_filter[9].u_filter

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_filter[10].u_filter

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_filter[11].u_filter

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_filter[12].u_filter

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_filter[13].u_filter

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_filter[14].u_filter

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_filter[15].u_filter

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_filter[16].u_filter

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_filter[17].u_filter

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_filter[18].u_filter

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_filter[19].u_filter

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_filter[20].u_filter

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_filter[21].u_filter

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_filter[22].u_filter

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_filter[23].u_filter

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_filter[24].u_filter

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_filter[25].u_filter

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_filter[26].u_filter

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_filter[27].u_filter

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_filter[28].u_filter

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_filter[29].u_filter

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_filter[30].u_filter

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_filter[31].u_filter

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_filter_ctr

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
CONT_ASSIGN	46	1	1	100.00
ALWAYS	50	3	3	100.00
ALWAYS	58	4	4	100.00
ALWAYS	66	3	3	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	79	1	1	100.00

45                        end else begin : gen_sync
46         1/1              assign filter_synced = filter_i;
           Tests:       T26 T27 T28 
47                        end
48                      
49                        always_ff @(posedge clk_i or negedge rst_ni) begin
50         1/1              if (!rst_ni) begin
           Tests:       T26 T27 T28 
51         1/1                filter_q <= 1'b0;
           Tests:       T26 T27 T28 
52                          end else begin
53         1/1                filter_q <= filter_synced;
           Tests:       T26 T27 T28 
54                          end
55                        end
56                      
57                        always_ff @(posedge clk_i or negedge rst_ni) begin
58         1/1              if (!rst_ni) begin
           Tests:       T26 T27 T28 
59         1/1                stored_value_q <= 1'b0;
           Tests:       T26 T27 T28 
60         1/1              end else if (update_stored_value) begin
           Tests:       T26 T27 T28 
61         1/1                stored_value_q <= filter_synced;
           Tests:       T26 T27 T28 
62                          end
                        MISSING_ELSE
63                        end
64                      
65                        always_ff @(posedge clk_i or negedge rst_ni) begin
66         1/1              if (!rst_ni) begin
           Tests:       T26 T27 T28 
67         1/1                diff_ctr_q <= '0;
           Tests:       T26 T27 T28 
68                          end else begin
69         1/1                diff_ctr_q <= diff_ctr_d;
           Tests:       T26 T27 T28 
70                          end
71                        end
72                      
73                        // always look for differences, even if not filter enabled
74         1/1            assign update_stored_value = (diff_ctr_d == thresh_i);
           Tests:       T26 T27 T28 
75         1/1            assign diff_ctr_d = (filter_synced != filter_q) ? '0       :           // restart
           Tests:       T26 T27 T28 
76                                            (diff_ctr_q >= thresh_i)    ? thresh_i :           // saturate
77                                                                          (diff_ctr_q + 1'b1); // count up
78                      
79         1/1            assign filter_o = enable_i ? stored_value_q : filter_synced;
           Tests:       T26 T27 T28 

---

Cond Coverage for Module : prim_filter_ctr

	Total	Covered	Percent
Conditions	10	10	100.00
Logical	10	10	100.00
Non-Logical	0	0
Event	0	0

 LINE       74
 EXPRESSION (diff_ctr_d == thresh_i)
            ------------1-----------

-1-	Status	Tests
0	Covered	T26,T27,T28
1	Covered	T26,T27,T28

 LINE       75
 EXPRESSION ((filter_synced != filter_q) ? '0 : ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1))))
             -------------1-------------

-1-	Status	Tests
0	Covered	T26,T27,T28
1	Covered	T26,T27,T28

 LINE       75
 SUB-EXPRESSION (filter_synced != filter_q)
                -------------1-------------

-1-	Status	Tests
0	Covered	T26,T27,T28
1	Covered	T26,T27,T28

 LINE       75
 SUB-EXPRESSION ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1)))
                 ------------1-----------

-1-	Status	Tests
0	Covered	T26,T27,T28
1	Covered	T26,T27,T28

 LINE       79
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---

-1-	Status	Tests
0	Covered	T26,T27,T28
1	Covered	T32,T34,T35

---

Branch Coverage for Module : prim_filter_ctr

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	75	3	3	100.00
TERNARY	79	2	2	100.00
IF	50	2	2	100.00
IF	58	3	3	100.00
IF	66	2	2	100.00

75           assign diff_ctr_d = (filter_synced != filter_q) ? '0       :           // restart
                                                             -1-  
                                                             ==>  
76                               (diff_ctr_q >= thresh_i)    ? thresh_i :           // saturate
                                                             -2-  
                                                             ==>  
                                                             ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T26,T27,T28
0	1	Covered	T26,T27,T28
0	0	Covered	T26,T27,T28

79           assign filter_o = enable_i ? stored_value_q : filter_synced;
                                        -1-  
                                        ==>  
                                        ==>  

Branches:

-1-	Status	Tests
1	Covered	T32,T34,T35
0	Covered	T26,T27,T28

50             if (!rst_ni) begin
               -1-  
51               filter_q <= 1'b0;
                 ==>
52             end else begin
53               filter_q <= filter_synced;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T26,T27,T28
0	Covered	T26,T27,T28

58             if (!rst_ni) begin
               -1-  
59               stored_value_q <= 1'b0;
                 ==>
60             end else if (update_stored_value) begin
                        -2-  
61               stored_value_q <= filter_synced;
                 ==>
62             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T26,T27,T28
0	1	Covered	T26,T27,T28
0	0	Covered	T26,T27,T28

66             if (!rst_ni) begin
               -1-  
67               diff_ctr_q <= '0;
                 ==>
68             end else begin
69               diff_ctr_q <= diff_ctr_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T26,T27,T28
0	Covered	T26,T27,T28

Line Coverage for Instance : tb.dut.gen_filter[0].u_filter

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
CONT_ASSIGN	46	1	1	100.00
ALWAYS	50	3	3	100.00
ALWAYS	58	4	4	100.00
ALWAYS	66	3	3	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	79	1	1	100.00

45                        end else begin : gen_sync
46         1/1              assign filter_synced = filter_i;
           Tests:       T26 T27 T28 
47                        end
48                      
49                        always_ff @(posedge clk_i or negedge rst_ni) begin
50         1/1              if (!rst_ni) begin
           Tests:       T26 T27 T28 
51         1/1                filter_q <= 1'b0;
           Tests:       T26 T27 T28 
52                          end else begin
53         1/1                filter_q <= filter_synced;
           Tests:       T26 T27 T28 
54                          end
55                        end
56                      
57                        always_ff @(posedge clk_i or negedge rst_ni) begin
58         1/1              if (!rst_ni) begin
           Tests:       T26 T27 T28 
59         1/1                stored_value_q <= 1'b0;
           Tests:       T26 T27 T28 
60         1/1              end else if (update_stored_value) begin
           Tests:       T26 T27 T28 
61         1/1                stored_value_q <= filter_synced;
           Tests:       T26 T27 T28 
62                          end
                        MISSING_ELSE
63                        end
64                      
65                        always_ff @(posedge clk_i or negedge rst_ni) begin
66         1/1              if (!rst_ni) begin
           Tests:       T26 T27 T28 
67         1/1                diff_ctr_q <= '0;
           Tests:       T26 T27 T28 
68                          end else begin
69         1/1                diff_ctr_q <= diff_ctr_d;
           Tests:       T26 T27 T28 
70                          end
71                        end
72                      
73                        // always look for differences, even if not filter enabled
74         1/1            assign update_stored_value = (diff_ctr_d == thresh_i);
           Tests:       T26 T27 T28 
75         1/1            assign diff_ctr_d = (filter_synced != filter_q) ? '0       :           // restart
           Tests:       T26 T27 T28 
76                                            (diff_ctr_q >= thresh_i)    ? thresh_i :           // saturate
77                                                                          (diff_ctr_q + 1'b1); // count up
78                      
79         1/1            assign filter_o = enable_i ? stored_value_q : filter_synced;
           Tests:       T26 T27 T28 

---

Cond Coverage for Instance : tb.dut.gen_filter[0].u_filter

	Total	Covered	Percent
Conditions	10	10	100.00
Logical	10	10	100.00
Non-Logical	0	0
Event	0	0

 LINE       74
 EXPRESSION (diff_ctr_d == thresh_i)
            ------------1-----------

-1-	Status	Tests
0	Covered	T26,T27,T28
1	Covered	T26,T27,T28

 LINE       75
 EXPRESSION ((filter_synced != filter_q) ? '0 : ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1))))
             -------------1-------------

-1-	Status	Tests
0	Covered	T26,T27,T28
1	Covered	T26,T27,T28

 LINE       75
 SUB-EXPRESSION (filter_synced != filter_q)
                -------------1-------------

-1-	Status	Tests
0	Covered	T26,T27,T28
1	Covered	T26,T27,T28

 LINE       75
 SUB-EXPRESSION ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1)))
                 ------------1-----------

-1-	Status	Tests
0	Covered	T26,T27,T28
1	Covered	T26,T27,T28

 LINE       79
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---

-1-	Status	Tests
0	Covered	T26,T27,T28
1	Covered	T32,T34,T35

---

Branch Coverage for Instance : tb.dut.gen_filter[0].u_filter

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	75	3	3	100.00
TERNARY	79	2	2	100.00
IF	50	2	2	100.00
IF	58	3	3	100.00
IF	66	2	2	100.00

75           assign diff_ctr_d = (filter_synced != filter_q) ? '0       :           // restart
                                                             -1-  
                                                             ==>  
76                               (diff_ctr_q >= thresh_i)    ? thresh_i :           // saturate
                                                             -2-  
                                                             ==>  
                                                             ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T26,T27,T28
0	1	Covered	T26,T27,T28
0	0	Covered	T26,T27,T28

79           assign filter_o = enable_i ? stored_value_q : filter_synced;
                                        -1-  
                                        ==>  
                                        ==>  

Branches:

-1-	Status	Tests
1	Covered	T32,T34,T35
0	Covered	T26,T27,T28

50             if (!rst_ni) begin
               -1-  
51               filter_q <= 1'b0;
                 ==>
52             end else begin
53               filter_q <= filter_synced;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T26,T27,T28
0	Covered	T26,T27,T28

58             if (!rst_ni) begin
               -1-  
59               stored_value_q <= 1'b0;
                 ==>
60             end else if (update_stored_value) begin
                        -2-  
61               stored_value_q <= filter_synced;
                 ==>
62             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T26,T27,T28
0	1	Covered	T26,T27,T28
0	0	Covered	T26,T27,T28

66             if (!rst_ni) begin
               -1-  
67               diff_ctr_q <= '0;
                 ==>
68             end else begin
69               diff_ctr_q <= diff_ctr_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T26,T27,T28
0	Covered	T26,T27,T28

Line Coverage for Instance : tb.dut.gen_filter[1].u_filter

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
CONT_ASSIGN	46	1	1	100.00
ALWAYS	50	3	3	100.00
ALWAYS	58	4	4	100.00
ALWAYS	66	3	3	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	79	1	1	100.00

45                        end else begin : gen_sync
46         1/1              assign filter_synced = filter_i;
           Tests:       T26 T27 T28 
47                        end
48                      
49                        always_ff @(posedge clk_i or negedge rst_ni) begin
50         1/1              if (!rst_ni) begin
           Tests:       T26 T27 T28 
51         1/1                filter_q <= 1'b0;
           Tests:       T26 T27 T28 
52                          end else begin
53         1/1                filter_q <= filter_synced;
           Tests:       T26 T27 T28 
54                          end
55                        end
56                      
57                        always_ff @(posedge clk_i or negedge rst_ni) begin
58         1/1              if (!rst_ni) begin
           Tests:       T26 T27 T28 
59         1/1                stored_value_q <= 1'b0;
           Tests:       T26 T27 T28 
60         1/1              end else if (update_stored_value) begin
           Tests:       T26 T27 T28 
61         1/1                stored_value_q <= filter_synced;
           Tests:       T26 T27 T28 
62                          end
                        MISSING_ELSE
63                        end
64                      
65                        always_ff @(posedge clk_i or negedge rst_ni) begin
66         1/1              if (!rst_ni) begin
           Tests:       T26 T27 T28 
67         1/1                diff_ctr_q <= '0;
           Tests:       T26 T27 T28 
68                          end else begin
69         1/1                diff_ctr_q <= diff_ctr_d;
           Tests:       T26 T27 T28 
70                          end
71                        end
72                      
73                        // always look for differences, even if not filter enabled
74         1/1            assign update_stored_value = (diff_ctr_d == thresh_i);
           Tests:       T26 T27 T28 
75         1/1            assign diff_ctr_d = (filter_synced != filter_q) ? '0       :           // restart
           Tests:       T26 T27 T28 
76                                            (diff_ctr_q >= thresh_i)    ? thresh_i :           // saturate
77                                                                          (diff_ctr_q + 1'b1); // count up
78                      
79         1/1            assign filter_o = enable_i ? stored_value_q : filter_synced;
           Tests:       T26 T27 T28 

---

Cond Coverage for Instance : tb.dut.gen_filter[1].u_filter

	Total	Covered	Percent
Conditions	10	10	100.00
Logical	10	10	100.00
Non-Logical	0	0
Event	0	0

 LINE       74
 EXPRESSION (diff_ctr_d == thresh_i)
            ------------1-----------

-1-	Status	Tests
0	Covered	T26,T27,T28
1	Covered	T26,T27,T28

 LINE       75
 EXPRESSION ((filter_synced != filter_q) ? '0 : ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1))))
             -------------1-------------

-1-	Status	Tests
0	Covered	T26,T27,T28
1	Covered	T26,T27,T28

 LINE       75
 SUB-EXPRESSION (filter_synced != filter_q)
                -------------1-------------

-1-	Status	Tests
0	Covered	T26,T27,T28
1	Covered	T26,T27,T28

 LINE       75
 SUB-EXPRESSION ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1)))
                 ------------1-----------

-1-	Status	Tests
0	Covered	T26,T27,T28
1	Covered	T26,T27,T28

 LINE       79
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---

-1-	Status	Tests
0	Covered	T26,T27,T28
1	Covered	T32,T34,T35

---

Branch Coverage for Instance : tb.dut.gen_filter[1].u_filter

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	75	3	3	100.00
TERNARY	79	2	2	100.00
IF	50	2	2	100.00
IF	58	3	3	100.00
IF	66	2	2	100.00

75           assign diff_ctr_d = (filter_synced != filter_q) ? '0       :           // restart
                                                             -1-  
                                                             ==>  
76                               (diff_ctr_q >= thresh_i)    ? thresh_i :           // saturate
                                                             -2-  
                                                             ==>  
                                                             ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T26,T27,T28
0	1	Covered	T26,T27,T28
0	0	Covered	T26,T27,T28

79           assign filter_o = enable_i ? stored_value_q : filter_synced;
                                        -1-  
                                        ==>  
                                        ==>  

Branches:

-1-	Status	Tests
1	Covered	T32,T34,T35
0	Covered	T26,T27,T28

50             if (!rst_ni) begin
               -1-  
51               filter_q <= 1'b0;
                 ==>
52             end else begin
53               filter_q <= filter_synced;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T26,T27,T28
0	Covered	T26,T27,T28

58             if (!rst_ni) begin
               -1-  
59               stored_value_q <= 1'b0;
                 ==>
60             end else if (update_stored_value) begin
                        -2-  
61               stored_value_q <= filter_synced;
                 ==>
62             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T26,T27,T28
0	1	Covered	T26,T27,T28
0	0	Covered	T26,T27,T28

66             if (!rst_ni) begin
               -1-  
67               diff_ctr_q <= '0;
                 ==>
68             end else begin
69               diff_ctr_q <= diff_ctr_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T26,T27,T28
0	Covered	T26,T27,T28

Line Coverage for Instance : tb.dut.gen_filter[2].u_filter

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
CONT_ASSIGN	46	1	1	100.00
ALWAYS	50	3	3	100.00
ALWAYS	58	4	4	100.00
ALWAYS	66	3	3	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	79	1	1	100.00

45                        end else begin : gen_sync
46         1/1              assign filter_synced = filter_i;
           Tests:       T26 T27 T28 
47                        end
48                      
49                        always_ff @(posedge clk_i or negedge rst_ni) begin
50         1/1              if (!rst_ni) begin
           Tests:       T26 T27 T28 
51         1/1                filter_q <= 1'b0;
           Tests:       T26 T27 T28 
52                          end else begin
53         1/1                filter_q <= filter_synced;
           Tests:       T26 T27 T28 
54                          end
55                        end
56                      
57                        always_ff @(posedge clk_i or negedge rst_ni) begin
58         1/1              if (!rst_ni) begin
           Tests:       T26 T27 T28 
59         1/1                stored_value_q <= 1'b0;
           Tests:       T26 T27 T28 
60         1/1              end else if (update_stored_value) begin
           Tests:       T26 T27 T28 
61         1/1                stored_value_q <= filter_synced;
           Tests:       T26 T27 T28 
62                          end
                        MISSING_ELSE
63                        end
64                      
65                        always_ff @(posedge clk_i or negedge rst_ni) begin
66         1/1              if (!rst_ni) begin
           Tests:       T26 T27 T28 
67         1/1                diff_ctr_q <= '0;
           Tests:       T26 T27 T28 
68                          end else begin
69         1/1                diff_ctr_q <= diff_ctr_d;
           Tests:       T26 T27 T28 
70                          end
71                        end
72                      
73                        // always look for differences, even if not filter enabled
74         1/1            assign update_stored_value = (diff_ctr_d == thresh_i);
           Tests:       T26 T27 T28 
75         1/1            assign diff_ctr_d = (filter_synced != filter_q) ? '0       :           // restart
           Tests:       T26 T27 T28 
76                                            (diff_ctr_q >= thresh_i)    ? thresh_i :           // saturate
77                                                                          (diff_ctr_q + 1'b1); // count up
78                      
79         1/1            assign filter_o = enable_i ? stored_value_q : filter_synced;
           Tests:       T26 T27 T28 

---

Cond Coverage for Instance : tb.dut.gen_filter[2].u_filter

	Total	Covered	Percent
Conditions	10	10	100.00
Logical	10	10	100.00
Non-Logical	0	0
Event	0	0

 LINE       74
 EXPRESSION (diff_ctr_d == thresh_i)
            ------------1-----------

-1-	Status	Tests
0	Covered	T26,T27,T28
1	Covered	T26,T27,T28

 LINE       75
 EXPRESSION ((filter_synced != filter_q) ? '0 : ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1))))
             -------------1-------------

-1-	Status	Tests
0	Covered	T26,T27,T28
1	Covered	T26,T27,T28

 LINE       75
 SUB-EXPRESSION (filter_synced != filter_q)
                -------------1-------------

-1-	Status	Tests
0	Covered	T26,T27,T28
1	Covered	T26,T27,T28

 LINE       75
 SUB-EXPRESSION ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1)))
                 ------------1-----------

-1-	Status	Tests
0	Covered	T26,T27,T28
1	Covered	T26,T27,T28

 LINE       79
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---

-1-	Status	Tests
0	Covered	T26,T27,T28
1	Covered	T32,T34,T35

---

Branch Coverage for Instance : tb.dut.gen_filter[2].u_filter

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	75	3	3	100.00
TERNARY	79	2	2	100.00
IF	50	2	2	100.00
IF	58	3	3	100.00
IF	66	2	2	100.00

75           assign diff_ctr_d = (filter_synced != filter_q) ? '0       :           // restart
                                                             -1-  
                                                             ==>  
76                               (diff_ctr_q >= thresh_i)    ? thresh_i :           // saturate
                                                             -2-  
                                                             ==>  
                                                             ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T26,T27,T28
0	1	Covered	T26,T27,T28
0	0	Covered	T26,T27,T28

79           assign filter_o = enable_i ? stored_value_q : filter_synced;
                                        -1-  
                                        ==>  
                                        ==>  

Branches:

-1-	Status	Tests
1	Covered	T32,T34,T35
0	Covered	T26,T27,T28

50             if (!rst_ni) begin
               -1-  
51               filter_q <= 1'b0;
                 ==>
52             end else begin
53               filter_q <= filter_synced;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T26,T27,T28
0	Covered	T26,T27,T28

58             if (!rst_ni) begin
               -1-  
59               stored_value_q <= 1'b0;
                 ==>
60             end else if (update_stored_value) begin
                        -2-  
61               stored_value_q <= filter_synced;
                 ==>
62             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T26,T27,T28
0	1	Covered	T26,T27,T28
0	0	Covered	T26,T27,T28

66             if (!rst_ni) begin
               -1-  
67               diff_ctr_q <= '0;
                 ==>
68             end else begin
69               diff_ctr_q <= diff_ctr_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T26,T27,T28
0	Covered	T26,T27,T28

Line Coverage for Instance : tb.dut.gen_filter[3].u_filter

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
CONT_ASSIGN	46	1	1	100.00
ALWAYS	50	3	3	100.00
ALWAYS	58	4	4	100.00
ALWAYS	66	3	3	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	79	1	1	100.00

45                        end else begin : gen_sync
46         1/1              assign filter_synced = filter_i;
           Tests:       T26 T27 T28 
47                        end
48                      
49                        always_ff @(posedge clk_i or negedge rst_ni) begin
50         1/1              if (!rst_ni) begin
           Tests:       T26 T27 T28 
51         1/1                filter_q <= 1'b0;
           Tests:       T26 T27 T28 
52                          end else begin
53         1/1                filter_q <= filter_synced;
           Tests:       T26 T27 T28 
54                          end
55                        end
56                      
57                        always_ff @(posedge clk_i or negedge rst_ni) begin
58         1/1              if (!rst_ni) begin
           Tests:       T26 T27 T28 
59         1/1                stored_value_q <= 1'b0;
           Tests:       T26 T27 T28 
60         1/1              end else if (update_stored_value) begin
           Tests:       T26 T27 T28 
61         1/1                stored_value_q <= filter_synced;
           Tests:       T26 T27 T28 
62                          end
                        MISSING_ELSE
63                        end
64                      
65                        always_ff @(posedge clk_i or negedge rst_ni) begin
66         1/1              if (!rst_ni) begin
           Tests:       T26 T27 T28 
67         1/1                diff_ctr_q <= '0;
           Tests:       T26 T27 T28 
68                          end else begin
69         1/1                diff_ctr_q <= diff_ctr_d;
           Tests:       T26 T27 T28 
70                          end
71                        end
72                      
73                        // always look for differences, even if not filter enabled
74         1/1            assign update_stored_value = (diff_ctr_d == thresh_i);
           Tests:       T26 T27 T28 
75         1/1            assign diff_ctr_d = (filter_synced != filter_q) ? '0       :           // restart
           Tests:       T26 T27 T28 
76                                            (diff_ctr_q >= thresh_i)    ? thresh_i :           // saturate
77                                                                          (diff_ctr_q + 1'b1); // count up
78                      
79         1/1            assign filter_o = enable_i ? stored_value_q : filter_synced;
           Tests:       T26 T27 T28 

---

Cond Coverage for Instance : tb.dut.gen_filter[3].u_filter

	Total	Covered	Percent
Conditions	10	10	100.00
Logical	10	10	100.00
Non-Logical	0	0
Event	0	0

 LINE       74
 EXPRESSION (diff_ctr_d == thresh_i)
            ------------1-----------

-1-	Status	Tests
0	Covered	T26,T27,T28
1	Covered	T26,T27,T28

 LINE       75
 EXPRESSION ((filter_synced != filter_q) ? '0 : ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1))))
             -------------1-------------

-1-	Status	Tests
0	Covered	T26,T27,T28
1	Covered	T26,T27,T28

 LINE       75
 SUB-EXPRESSION (filter_synced != filter_q)
                -------------1-------------

-1-	Status	Tests
0	Covered	T26,T27,T28
1	Covered	T26,T27,T28

 LINE       75
 SUB-EXPRESSION ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1)))
                 ------------1-----------

-1-	Status	Tests
0	Covered	T26,T27,T28
1	Covered	T26,T27,T28

 LINE       79
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---

-1-	Status	Tests
0	Covered	T26,T27,T28
1	Covered	T32,T34,T35

---

Branch Coverage for Instance : tb.dut.gen_filter[3].u_filter

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	75	3	3	100.00
TERNARY	79	2	2	100.00
IF	50	2	2	100.00
IF	58	3	3	100.00
IF	66	2	2	100.00

75           assign diff_ctr_d = (filter_synced != filter_q) ? '0       :           // restart
                                                             -1-  
                                                             ==>  
76                               (diff_ctr_q >= thresh_i)    ? thresh_i :           // saturate
                                                             -2-  
                                                             ==>  
                                                             ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T26,T27,T28
0	1	Covered	T26,T27,T28
0	0	Covered	T26,T27,T28

79           assign filter_o = enable_i ? stored_value_q : filter_synced;
                                        -1-  
                                        ==>  
                                        ==>  

Branches:

-1-	Status	Tests
1	Covered	T32,T34,T35
0	Covered	T26,T27,T28

50             if (!rst_ni) begin
               -1-  
51               filter_q <= 1'b0;
                 ==>
52             end else begin
53               filter_q <= filter_synced;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T26,T27,T28
0	Covered	T26,T27,T28

58             if (!rst_ni) begin
               -1-  
59               stored_value_q <= 1'b0;
                 ==>
60             end else if (update_stored_value) begin
                        -2-  
61               stored_value_q <= filter_synced;
                 ==>
62             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T26,T27,T28
0	1	Covered	T26,T27,T28
0	0	Covered	T26,T27,T28

66             if (!rst_ni) begin
               -1-  
67               diff_ctr_q <= '0;
                 ==>
68             end else begin
69               diff_ctr_q <= diff_ctr_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T26,T27,T28
0	Covered	T26,T27,T28

Line Coverage for Instance : tb.dut.gen_filter[4].u_filter

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
CONT_ASSIGN	46	1	1	100.00
ALWAYS	50	3	3	100.00
ALWAYS	58	4	4	100.00
ALWAYS	66	3	3	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	79	1	1	100.00

45                        end else begin : gen_sync
46         1/1              assign filter_synced = filter_i;
           Tests:       T26 T27 T28 
47                        end
48                      
49                        always_ff @(posedge clk_i or negedge rst_ni) begin
50         1/1              if (!rst_ni) begin
           Tests:       T26 T27 T28 
51         1/1                filter_q <= 1'b0;
           Tests:       T26 T27 T28 
52                          end else begin
53         1/1                filter_q <= filter_synced;
           Tests:       T26 T27 T28 
54                          end
55                        end
56                      
57                        always_ff @(posedge clk_i or negedge rst_ni) begin
58         1/1              if (!rst_ni) begin
           Tests:       T26 T27 T28 
59         1/1                stored_value_q <= 1'b0;
           Tests:       T26 T27 T28 
60         1/1              end else if (update_stored_value) begin
           Tests:       T26 T27 T28 
61         1/1                stored_value_q <= filter_synced;
           Tests:       T26 T27 T28 
62                          end
                        MISSING_ELSE
63                        end
64                      
65                        always_ff @(posedge clk_i or negedge rst_ni) begin
66         1/1              if (!rst_ni) begin
           Tests:       T26 T27 T28 
67         1/1                diff_ctr_q <= '0;
           Tests:       T26 T27 T28 
68                          end else begin
69         1/1                diff_ctr_q <= diff_ctr_d;
           Tests:       T26 T27 T28 
70                          end
71                        end
72                      
73                        // always look for differences, even if not filter enabled
74         1/1            assign update_stored_value = (diff_ctr_d == thresh_i);
           Tests:       T26 T27 T28 
75         1/1            assign diff_ctr_d = (filter_synced != filter_q) ? '0       :           // restart
           Tests:       T26 T27 T28 
76                                            (diff_ctr_q >= thresh_i)    ? thresh_i :           // saturate
77                                                                          (diff_ctr_q + 1'b1); // count up
78                      
79         1/1            assign filter_o = enable_i ? stored_value_q : filter_synced;
           Tests:       T26 T27 T28 

---

Cond Coverage for Instance : tb.dut.gen_filter[4].u_filter

	Total	Covered	Percent
Conditions	10	10	100.00
Logical	10	10	100.00
Non-Logical	0	0
Event	0	0

 LINE       74
 EXPRESSION (diff_ctr_d == thresh_i)
            ------------1-----------

-1-	Status	Tests
0	Covered	T26,T27,T28
1	Covered	T26,T27,T28

 LINE       75
 EXPRESSION ((filter_synced != filter_q) ? '0 : ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1))))
             -------------1-------------

-1-	Status	Tests
0	Covered	T26,T27,T28
1	Covered	T26,T27,T28

 LINE       75
 SUB-EXPRESSION (filter_synced != filter_q)
                -------------1-------------

-1-	Status	Tests
0	Covered	T26,T27,T28
1	Covered	T26,T27,T28

 LINE       75
 SUB-EXPRESSION ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1)))
                 ------------1-----------

-1-	Status	Tests
0	Covered	T26,T27,T28
1	Covered	T26,T27,T28

 LINE       79
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---

-1-	Status	Tests
0	Covered	T26,T27,T28
1	Covered	T32,T34,T35

---

Branch Coverage for Instance : tb.dut.gen_filter[4].u_filter

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	75	3	3	100.00
TERNARY	79	2	2	100.00
IF	50	2	2	100.00
IF	58	3	3	100.00
IF	66	2	2	100.00

75           assign diff_ctr_d = (filter_synced != filter_q) ? '0       :           // restart
                                                             -1-  
                                                             ==>  
76                               (diff_ctr_q >= thresh_i)    ? thresh_i :           // saturate
                                                             -2-  
                                                             ==>  
                                                             ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T26,T27,T28
0	1	Covered	T26,T27,T28
0	0	Covered	T26,T27,T28

79           assign filter_o = enable_i ? stored_value_q : filter_synced;
                                        -1-  
                                        ==>  
                                        ==>  

Branches:

-1-	Status	Tests
1	Covered	T32,T34,T35
0	Covered	T26,T27,T28

50             if (!rst_ni) begin
               -1-  
51               filter_q <= 1'b0;
                 ==>
52             end else begin
53               filter_q <= filter_synced;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T26,T27,T28
0	Covered	T26,T27,T28

58             if (!rst_ni) begin
               -1-  
59               stored_value_q <= 1'b0;
                 ==>
60             end else if (update_stored_value) begin
                        -2-  
61               stored_value_q <= filter_synced;
                 ==>
62             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T26,T27,T28
0	1	Covered	T26,T27,T28
0	0	Covered	T26,T27,T28

66             if (!rst_ni) begin
               -1-  
67               diff_ctr_q <= '0;
                 ==>
68             end else begin
69               diff_ctr_q <= diff_ctr_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T26,T27,T28
0	Covered	T26,T27,T28

Line Coverage for Instance : tb.dut.gen_filter[5].u_filter

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
CONT_ASSIGN	46	1	1	100.00
ALWAYS	50	3	3	100.00
ALWAYS	58	4	4	100.00
ALWAYS	66	3	3	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	79	1	1	100.00

45                        end else begin : gen_sync
46         1/1              assign filter_synced = filter_i;
           Tests:       T26 T27 T28 
47                        end
48                      
49                        always_ff @(posedge clk_i or negedge rst_ni) begin
50         1/1              if (!rst_ni) begin
           Tests:       T26 T27 T28 
51         1/1                filter_q <= 1'b0;
           Tests:       T26 T27 T28 
52                          end else begin
53         1/1                filter_q <= filter_synced;
           Tests:       T26 T27 T28 
54                          end
55                        end
56                      
57                        always_ff @(posedge clk_i or negedge rst_ni) begin
58         1/1              if (!rst_ni) begin
           Tests:       T26 T27 T28 
59         1/1                stored_value_q <= 1'b0;
           Tests:       T26 T27 T28 
60         1/1              end else if (update_stored_value) begin
           Tests:       T26 T27 T28 
61         1/1                stored_value_q <= filter_synced;
           Tests:       T26 T27 T28 
62                          end
                        MISSING_ELSE
63                        end
64                      
65                        always_ff @(posedge clk_i or negedge rst_ni) begin
66         1/1              if (!rst_ni) begin
           Tests:       T26 T27 T28 
67         1/1                diff_ctr_q <= '0;
           Tests:       T26 T27 T28 
68                          end else begin
69         1/1                diff_ctr_q <= diff_ctr_d;
           Tests:       T26 T27 T28 
70                          end
71                        end
72                      
73                        // always look for differences, even if not filter enabled
74         1/1            assign update_stored_value = (diff_ctr_d == thresh_i);
           Tests:       T26 T27 T28 
75         1/1            assign diff_ctr_d = (filter_synced != filter_q) ? '0       :           // restart
           Tests:       T26 T27 T28 
76                                            (diff_ctr_q >= thresh_i)    ? thresh_i :           // saturate
77                                                                          (diff_ctr_q + 1'b1); // count up
78                      
79         1/1            assign filter_o = enable_i ? stored_value_q : filter_synced;
           Tests:       T26 T27 T28 

---

Cond Coverage for Instance : tb.dut.gen_filter[5].u_filter

	Total	Covered	Percent
Conditions	10	10	100.00
Logical	10	10	100.00
Non-Logical	0	0
Event	0	0

 LINE       74
 EXPRESSION (diff_ctr_d == thresh_i)
            ------------1-----------

-1-	Status	Tests
0	Covered	T26,T27,T28
1	Covered	T26,T27,T28

 LINE       75
 EXPRESSION ((filter_synced != filter_q) ? '0 : ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1))))
             -------------1-------------

-1-	Status	Tests
0	Covered	T26,T27,T28
1	Covered	T26,T27,T28

 LINE       75
 SUB-EXPRESSION (filter_synced != filter_q)
                -------------1-------------

-1-	Status	Tests
0	Covered	T26,T27,T28
1	Covered	T26,T27,T28

 LINE       75
 SUB-EXPRESSION ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1)))
                 ------------1-----------

-1-	Status	Tests
0	Covered	T26,T27,T28
1	Covered	T26,T27,T28

 LINE       79
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---

-1-	Status	Tests
0	Covered	T26,T27,T28
1	Covered	T32,T34,T35

---

Branch Coverage for Instance : tb.dut.gen_filter[5].u_filter

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	75	3	3	100.00
TERNARY	79	2	2	100.00
IF	50	2	2	100.00
IF	58	3	3	100.00
IF	66	2	2	100.00

75           assign diff_ctr_d = (filter_synced != filter_q) ? '0       :           // restart
                                                             -1-  
                                                             ==>  
76                               (diff_ctr_q >= thresh_i)    ? thresh_i :           // saturate
                                                             -2-  
                                                             ==>  
                                                             ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T26,T27,T28
0	1	Covered	T26,T27,T28
0	0	Covered	T26,T27,T28

79           assign filter_o = enable_i ? stored_value_q : filter_synced;
                                        -1-  
                                        ==>  
                                        ==>  

Branches:

-1-	Status	Tests
1	Covered	T32,T34,T35
0	Covered	T26,T27,T28

50             if (!rst_ni) begin
               -1-  
51               filter_q <= 1'b0;
                 ==>
52             end else begin
53               filter_q <= filter_synced;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T26,T27,T28
0	Covered	T26,T27,T28

58             if (!rst_ni) begin
               -1-  
59               stored_value_q <= 1'b0;
                 ==>
60             end else if (update_stored_value) begin
                        -2-  
61               stored_value_q <= filter_synced;
                 ==>
62             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T26,T27,T28
0	1	Covered	T26,T27,T28
0	0	Covered	T26,T27,T28

66             if (!rst_ni) begin
               -1-  
67               diff_ctr_q <= '0;
                 ==>
68             end else begin
69               diff_ctr_q <= diff_ctr_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T26,T27,T28
0	Covered	T26,T27,T28

Line Coverage for Instance : tb.dut.gen_filter[6].u_filter

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
CONT_ASSIGN	46	1	1	100.00
ALWAYS	50	3	3	100.00
ALWAYS	58	4	4	100.00
ALWAYS	66	3	3	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	79	1	1	100.00

45                        end else begin : gen_sync
46         1/1              assign filter_synced = filter_i;
           Tests:       T26 T27 T28 
47                        end
48                      
49                        always_ff @(posedge clk_i or negedge rst_ni) begin
50         1/1              if (!rst_ni) begin
           Tests:       T26 T27 T28 
51         1/1                filter_q <= 1'b0;
           Tests:       T26 T27 T28 
52                          end else begin
53         1/1                filter_q <= filter_synced;
           Tests:       T26 T27 T28 
54                          end
55                        end
56                      
57                        always_ff @(posedge clk_i or negedge rst_ni) begin
58         1/1              if (!rst_ni) begin
           Tests:       T26 T27 T28 
59         1/1                stored_value_q <= 1'b0;
           Tests:       T26 T27 T28 
60         1/1              end else if (update_stored_value) begin
           Tests:       T26 T27 T28 
61         1/1                stored_value_q <= filter_synced;
           Tests:       T26 T27 T28 
62                          end
                        MISSING_ELSE
63                        end
64                      
65                        always_ff @(posedge clk_i or negedge rst_ni) begin
66         1/1              if (!rst_ni) begin
           Tests:       T26 T27 T28 
67         1/1                diff_ctr_q <= '0;
           Tests:       T26 T27 T28 
68                          end else begin
69         1/1                diff_ctr_q <= diff_ctr_d;
           Tests:       T26 T27 T28 
70                          end
71                        end
72                      
73                        // always look for differences, even if not filter enabled
74         1/1            assign update_stored_value = (diff_ctr_d == thresh_i);
           Tests:       T26 T27 T28 
75         1/1            assign diff_ctr_d = (filter_synced != filter_q) ? '0       :           // restart
           Tests:       T26 T27 T28 
76                                            (diff_ctr_q >= thresh_i)    ? thresh_i :           // saturate
77                                                                          (diff_ctr_q + 1'b1); // count up
78                      
79         1/1            assign filter_o = enable_i ? stored_value_q : filter_synced;
           Tests:       T26 T27 T28 

---

Cond Coverage for Instance : tb.dut.gen_filter[6].u_filter

	Total	Covered	Percent
Conditions	10	10	100.00
Logical	10	10	100.00
Non-Logical	0	0
Event	0	0

 LINE       74
 EXPRESSION (diff_ctr_d == thresh_i)
            ------------1-----------

-1-	Status	Tests
0	Covered	T26,T27,T28
1	Covered	T26,T27,T28

 LINE       75
 EXPRESSION ((filter_synced != filter_q) ? '0 : ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1))))
             -------------1-------------

-1-	Status	Tests
0	Covered	T26,T27,T28
1	Covered	T26,T27,T28

 LINE       75
 SUB-EXPRESSION (filter_synced != filter_q)
                -------------1-------------

-1-	Status	Tests
0	Covered	T26,T27,T28
1	Covered	T26,T27,T28

 LINE       75
 SUB-EXPRESSION ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1)))
                 ------------1-----------

-1-	Status	Tests
0	Covered	T26,T27,T28
1	Covered	T26,T27,T28

 LINE       79
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---

-1-	Status	Tests
0	Covered	T26,T27,T28
1	Covered	T32,T34,T35

---

Branch Coverage for Instance : tb.dut.gen_filter[6].u_filter

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	75	3	3	100.00
TERNARY	79	2	2	100.00
IF	50	2	2	100.00
IF	58	3	3	100.00
IF	66	2	2	100.00

75           assign diff_ctr_d = (filter_synced != filter_q) ? '0       :           // restart
                                                             -1-  
                                                             ==>  
76                               (diff_ctr_q >= thresh_i)    ? thresh_i :           // saturate
                                                             -2-  
                                                             ==>  
                                                             ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T26,T27,T28
0	1	Covered	T26,T27,T28
0	0	Covered	T26,T27,T28

79           assign filter_o = enable_i ? stored_value_q : filter_synced;
                                        -1-  
                                        ==>  
                                        ==>  

Branches:

-1-	Status	Tests
1	Covered	T32,T34,T35
0	Covered	T26,T27,T28

50             if (!rst_ni) begin
               -1-  
51               filter_q <= 1'b0;
                 ==>
52             end else begin
53               filter_q <= filter_synced;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T26,T27,T28
0	Covered	T26,T27,T28

58             if (!rst_ni) begin
               -1-  
59               stored_value_q <= 1'b0;
                 ==>
60             end else if (update_stored_value) begin
                        -2-  
61               stored_value_q <= filter_synced;
                 ==>
62             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T26,T27,T28
0	1	Covered	T26,T27,T28
0	0	Covered	T26,T27,T28

66             if (!rst_ni) begin
               -1-  
67               diff_ctr_q <= '0;
                 ==>
68             end else begin
69               diff_ctr_q <= diff_ctr_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T26,T27,T28
0	Covered	T26,T27,T28

Line Coverage for Instance : tb.dut.gen_filter[7].u_filter

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
CONT_ASSIGN	46	1	1	100.00
ALWAYS	50	3	3	100.00
ALWAYS	58	4	4	100.00
ALWAYS	66	3	3	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	79	1	1	100.00

45                        end else begin : gen_sync
46         1/1              assign filter_synced = filter_i;
           Tests:       T26 T27 T28 
47                        end
48                      
49                        always_ff @(posedge clk_i or negedge rst_ni) begin
50         1/1              if (!rst_ni) begin
           Tests:       T26 T27 T28 
51         1/1                filter_q <= 1'b0;
           Tests:       T26 T27 T28 
52                          end else begin
53         1/1                filter_q <= filter_synced;
           Tests:       T26 T27 T28 
54                          end
55                        end
56                      
57                        always_ff @(posedge clk_i or negedge rst_ni) begin
58         1/1              if (!rst_ni) begin
           Tests:       T26 T27 T28 
59         1/1                stored_value_q <= 1'b0;
           Tests:       T26 T27 T28 
60         1/1              end else if (update_stored_value) begin
           Tests:       T26 T27 T28 
61         1/1                stored_value_q <= filter_synced;
           Tests:       T26 T27 T28 
62                          end
                        MISSING_ELSE
63                        end
64                      
65                        always_ff @(posedge clk_i or negedge rst_ni) begin
66         1/1              if (!rst_ni) begin
           Tests:       T26 T27 T28 
67         1/1                diff_ctr_q <= '0;
           Tests:       T26 T27 T28 
68                          end else begin
69         1/1                diff_ctr_q <= diff_ctr_d;
           Tests:       T26 T27 T28 
70                          end
71                        end
72                      
73                        // always look for differences, even if not filter enabled
74         1/1            assign update_stored_value = (diff_ctr_d == thresh_i);
           Tests:       T26 T27 T28 
75         1/1            assign diff_ctr_d = (filter_synced != filter_q) ? '0       :           // restart
           Tests:       T26 T27 T28 
76                                            (diff_ctr_q >= thresh_i)    ? thresh_i :           // saturate
77                                                                          (diff_ctr_q + 1'b1); // count up
78                      
79         1/1            assign filter_o = enable_i ? stored_value_q : filter_synced;
           Tests:       T26 T27 T28 

---

Cond Coverage for Instance : tb.dut.gen_filter[7].u_filter

	Total	Covered	Percent
Conditions	10	10	100.00
Logical	10	10	100.00
Non-Logical	0	0
Event	0	0

 LINE       74
 EXPRESSION (diff_ctr_d == thresh_i)
            ------------1-----------

-1-	Status	Tests
0	Covered	T26,T27,T28
1	Covered	T26,T27,T28

 LINE       75
 EXPRESSION ((filter_synced != filter_q) ? '0 : ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1))))
             -------------1-------------

-1-	Status	Tests
0	Covered	T26,T27,T28
1	Covered	T26,T27,T28

 LINE       75
 SUB-EXPRESSION (filter_synced != filter_q)
                -------------1-------------

-1-	Status	Tests
0	Covered	T26,T27,T28
1	Covered	T26,T27,T28

 LINE       75
 SUB-EXPRESSION ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1)))
                 ------------1-----------

-1-	Status	Tests
0	Covered	T26,T27,T28
1	Covered	T26,T27,T28

 LINE       79
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---

-1-	Status	Tests
0	Covered	T26,T27,T28
1	Covered	T32,T34,T35

---

Branch Coverage for Instance : tb.dut.gen_filter[7].u_filter

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	75	3	3	100.00
TERNARY	79	2	2	100.00
IF	50	2	2	100.00
IF	58	3	3	100.00
IF	66	2	2	100.00

75           assign diff_ctr_d = (filter_synced != filter_q) ? '0       :           // restart
                                                             -1-  
                                                             ==>  
76                               (diff_ctr_q >= thresh_i)    ? thresh_i :           // saturate
                                                             -2-  
                                                             ==>  
                                                             ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T26,T27,T28
0	1	Covered	T26,T27,T28
0	0	Covered	T26,T27,T28

79           assign filter_o = enable_i ? stored_value_q : filter_synced;
                                        -1-  
                                        ==>  
                                        ==>  

Branches:

-1-	Status	Tests
1	Covered	T32,T34,T35
0	Covered	T26,T27,T28

50             if (!rst_ni) begin
               -1-  
51               filter_q <= 1'b0;
                 ==>
52             end else begin
53               filter_q <= filter_synced;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T26,T27,T28
0	Covered	T26,T27,T28

58             if (!rst_ni) begin
               -1-  
59               stored_value_q <= 1'b0;
                 ==>
60             end else if (update_stored_value) begin
                        -2-  
61               stored_value_q <= filter_synced;
                 ==>
62             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T26,T27,T28
0	1	Covered	T26,T27,T28
0	0	Covered	T26,T27,T28

66             if (!rst_ni) begin
               -1-  
67               diff_ctr_q <= '0;
                 ==>
68             end else begin
69               diff_ctr_q <= diff_ctr_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T26,T27,T28
0	Covered	T26,T27,T28

Line Coverage for Instance : tb.dut.gen_filter[8].u_filter

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
CONT_ASSIGN	46	1	1	100.00
ALWAYS	50	3	3	100.00
ALWAYS	58	4	4	100.00
ALWAYS	66	3	3	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	79	1	1	100.00

45                        end else begin : gen_sync
46         1/1              assign filter_synced = filter_i;
           Tests:       T26 T27 T28 
47                        end
48                      
49                        always_ff @(posedge clk_i or negedge rst_ni) begin
50         1/1              if (!rst_ni) begin
           Tests:       T26 T27 T28 
51         1/1                filter_q <= 1'b0;
           Tests:       T26 T27 T28 
52                          end else begin
53         1/1                filter_q <= filter_synced;
           Tests:       T26 T27 T28 
54                          end
55                        end
56                      
57                        always_ff @(posedge clk_i or negedge rst_ni) begin
58         1/1              if (!rst_ni) begin
           Tests:       T26 T27 T28 
59         1/1                stored_value_q <= 1'b0;
           Tests:       T26 T27 T28 
60         1/1              end else if (update_stored_value) begin
           Tests:       T26 T27 T28 
61         1/1                stored_value_q <= filter_synced;
           Tests:       T26 T27 T28 
62                          end
                        MISSING_ELSE
63                        end
64                      
65                        always_ff @(posedge clk_i or negedge rst_ni) begin
66         1/1              if (!rst_ni) begin
           Tests:       T26 T27 T28 
67         1/1                diff_ctr_q <= '0;
           Tests:       T26 T27 T28 
68                          end else begin
69         1/1                diff_ctr_q <= diff_ctr_d;
           Tests:       T26 T27 T28 
70                          end
71                        end
72                      
73                        // always look for differences, even if not filter enabled
74         1/1            assign update_stored_value = (diff_ctr_d == thresh_i);
           Tests:       T26 T27 T28 
75         1/1            assign diff_ctr_d = (filter_synced != filter_q) ? '0       :           // restart
           Tests:       T26 T27 T28 
76                                            (diff_ctr_q >= thresh_i)    ? thresh_i :           // saturate
77                                                                          (diff_ctr_q + 1'b1); // count up
78                      
79         1/1            assign filter_o = enable_i ? stored_value_q : filter_synced;
           Tests:       T26 T27 T28 

---

Cond Coverage for Instance : tb.dut.gen_filter[8].u_filter

	Total	Covered	Percent
Conditions	10	10	100.00
Logical	10	10	100.00
Non-Logical	0	0
Event	0	0

 LINE       74
 EXPRESSION (diff_ctr_d == thresh_i)
            ------------1-----------

-1-	Status	Tests
0	Covered	T26,T27,T28
1	Covered	T26,T27,T28

 LINE       75
 EXPRESSION ((filter_synced != filter_q) ? '0 : ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1))))
             -------------1-------------

-1-	Status	Tests
0	Covered	T26,T27,T28
1	Covered	T26,T27,T28

 LINE       75
 SUB-EXPRESSION (filter_synced != filter_q)
                -------------1-------------

-1-	Status	Tests
0	Covered	T26,T27,T28
1	Covered	T26,T27,T28

 LINE       75
 SUB-EXPRESSION ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1)))
                 ------------1-----------

-1-	Status	Tests
0	Covered	T26,T27,T28
1	Covered	T26,T27,T28

 LINE       79
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---

-1-	Status	Tests
0	Covered	T26,T27,T28
1	Covered	T32,T34,T35

---

Branch Coverage for Instance : tb.dut.gen_filter[8].u_filter

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	75	3	3	100.00
TERNARY	79	2	2	100.00
IF	50	2	2	100.00
IF	58	3	3	100.00
IF	66	2	2	100.00

75           assign diff_ctr_d = (filter_synced != filter_q) ? '0       :           // restart
                                                             -1-  
                                                             ==>  
76                               (diff_ctr_q >= thresh_i)    ? thresh_i :           // saturate
                                                             -2-  
                                                             ==>  
                                                             ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T26,T27,T28
0	1	Covered	T26,T27,T28
0	0	Covered	T26,T27,T28

79           assign filter_o = enable_i ? stored_value_q : filter_synced;
                                        -1-  
                                        ==>  
                                        ==>  

Branches:

-1-	Status	Tests
1	Covered	T32,T34,T35
0	Covered	T26,T27,T28

50             if (!rst_ni) begin
               -1-  
51               filter_q <= 1'b0;
                 ==>
52             end else begin
53               filter_q <= filter_synced;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T26,T27,T28
0	Covered	T26,T27,T28

58             if (!rst_ni) begin
               -1-  
59               stored_value_q <= 1'b0;
                 ==>
60             end else if (update_stored_value) begin
                        -2-  
61               stored_value_q <= filter_synced;
                 ==>
62             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T26,T27,T28
0	1	Covered	T26,T27,T28
0	0	Covered	T26,T27,T28

66             if (!rst_ni) begin
               -1-  
67               diff_ctr_q <= '0;
                 ==>
68             end else begin
69               diff_ctr_q <= diff_ctr_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T26,T27,T28
0	Covered	T26,T27,T28

Line Coverage for Instance : tb.dut.gen_filter[9].u_filter

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
CONT_ASSIGN	46	1	1	100.00
ALWAYS	50	3	3	100.00
ALWAYS	58	4	4	100.00
ALWAYS	66	3	3	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	79	1	1	100.00

45                        end else begin : gen_sync
46         1/1              assign filter_synced = filter_i;
           Tests:       T26 T27 T28 
47                        end
48                      
49                        always_ff @(posedge clk_i or negedge rst_ni) begin
50         1/1              if (!rst_ni) begin
           Tests:       T26 T27 T28 
51         1/1                filter_q <= 1'b0;
           Tests:       T26 T27 T28 
52                          end else begin
53         1/1                filter_q <= filter_synced;
           Tests:       T26 T27 T28 
54                          end
55                        end
56                      
57                        always_ff @(posedge clk_i or negedge rst_ni) begin
58         1/1              if (!rst_ni) begin
           Tests:       T26 T27 T28 
59         1/1                stored_value_q <= 1'b0;
           Tests:       T26 T27 T28 
60         1/1              end else if (update_stored_value) begin
           Tests:       T26 T27 T28 
61         1/1                stored_value_q <= filter_synced;
           Tests:       T26 T27 T28 
62                          end
                        MISSING_ELSE
63                        end
64                      
65                        always_ff @(posedge clk_i or negedge rst_ni) begin
66         1/1              if (!rst_ni) begin
           Tests:       T26 T27 T28 
67         1/1                diff_ctr_q <= '0;
           Tests:       T26 T27 T28 
68                          end else begin
69         1/1                diff_ctr_q <= diff_ctr_d;
           Tests:       T26 T27 T28 
70                          end
71                        end
72                      
73                        // always look for differences, even if not filter enabled
74         1/1            assign update_stored_value = (diff_ctr_d == thresh_i);
           Tests:       T26 T27 T28 
75         1/1            assign diff_ctr_d = (filter_synced != filter_q) ? '0       :           // restart
           Tests:       T26 T27 T28 
76                                            (diff_ctr_q >= thresh_i)    ? thresh_i :           // saturate
77                                                                          (diff_ctr_q + 1'b1); // count up
78                      
79         1/1            assign filter_o = enable_i ? stored_value_q : filter_synced;
           Tests:       T26 T27 T28 

---

Cond Coverage for Instance : tb.dut.gen_filter[9].u_filter

	Total	Covered	Percent
Conditions	10	10	100.00
Logical	10	10	100.00
Non-Logical	0	0
Event	0	0

 LINE       74
 EXPRESSION (diff_ctr_d == thresh_i)
            ------------1-----------

-1-	Status	Tests
0	Covered	T26,T27,T28
1	Covered	T26,T27,T28

 LINE       75
 EXPRESSION ((filter_synced != filter_q) ? '0 : ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1))))
             -------------1-------------

-1-	Status	Tests
0	Covered	T26,T27,T28
1	Covered	T26,T27,T28

 LINE       75
 SUB-EXPRESSION (filter_synced != filter_q)
                -------------1-------------

-1-	Status	Tests
0	Covered	T26,T27,T28
1	Covered	T26,T27,T28

 LINE       75
 SUB-EXPRESSION ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1)))
                 ------------1-----------

-1-	Status	Tests
0	Covered	T26,T27,T28
1	Covered	T26,T27,T28

 LINE       79
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---

-1-	Status	Tests
0	Covered	T26,T27,T28
1	Covered	T32,T34,T35

---

Branch Coverage for Instance : tb.dut.gen_filter[9].u_filter

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	75	3	3	100.00
TERNARY	79	2	2	100.00
IF	50	2	2	100.00
IF	58	3	3	100.00
IF	66	2	2	100.00

75           assign diff_ctr_d = (filter_synced != filter_q) ? '0       :           // restart
                                                             -1-  
                                                             ==>  
76                               (diff_ctr_q >= thresh_i)    ? thresh_i :           // saturate
                                                             -2-  
                                                             ==>  
                                                             ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T26,T27,T28
0	1	Covered	T26,T27,T28
0	0	Covered	T26,T27,T28

79           assign filter_o = enable_i ? stored_value_q : filter_synced;
                                        -1-  
                                        ==>  
                                        ==>  

Branches:

-1-	Status	Tests
1	Covered	T32,T34,T35
0	Covered	T26,T27,T28

50             if (!rst_ni) begin
               -1-  
51               filter_q <= 1'b0;
                 ==>
52             end else begin
53               filter_q <= filter_synced;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T26,T27,T28
0	Covered	T26,T27,T28

58             if (!rst_ni) begin
               -1-  
59               stored_value_q <= 1'b0;
                 ==>
60             end else if (update_stored_value) begin
                        -2-  
61               stored_value_q <= filter_synced;
                 ==>
62             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T26,T27,T28
0	1	Covered	T26,T27,T28
0	0	Covered	T26,T27,T28

66             if (!rst_ni) begin
               -1-  
67               diff_ctr_q <= '0;
                 ==>
68             end else begin
69               diff_ctr_q <= diff_ctr_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T26,T27,T28
0	Covered	T26,T27,T28

Line Coverage for Instance : tb.dut.gen_filter[10].u_filter

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
CONT_ASSIGN	46	1	1	100.00
ALWAYS	50	3	3	100.00
ALWAYS	58	4	4	100.00
ALWAYS	66	3	3	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	79	1	1	100.00

45                        end else begin : gen_sync
46         1/1              assign filter_synced = filter_i;
           Tests:       T26 T27 T28 
47                        end
48                      
49                        always_ff @(posedge clk_i or negedge rst_ni) begin
50         1/1              if (!rst_ni) begin
           Tests:       T26 T27 T28 
51         1/1                filter_q <= 1'b0;
           Tests:       T26 T27 T28 
52                          end else begin
53         1/1                filter_q <= filter_synced;
           Tests:       T26 T27 T28 
54                          end
55                        end
56                      
57                        always_ff @(posedge clk_i or negedge rst_ni) begin
58         1/1              if (!rst_ni) begin
           Tests:       T26 T27 T28 
59         1/1                stored_value_q <= 1'b0;
           Tests:       T26 T27 T28 
60         1/1              end else if (update_stored_value) begin
           Tests:       T26 T27 T28 
61         1/1                stored_value_q <= filter_synced;
           Tests:       T26 T27 T28 
62                          end
                        MISSING_ELSE
63                        end
64                      
65                        always_ff @(posedge clk_i or negedge rst_ni) begin
66         1/1              if (!rst_ni) begin
           Tests:       T26 T27 T28 
67         1/1                diff_ctr_q <= '0;
           Tests:       T26 T27 T28 
68                          end else begin
69         1/1                diff_ctr_q <= diff_ctr_d;
           Tests:       T26 T27 T28 
70                          end
71                        end
72                      
73                        // always look for differences, even if not filter enabled
74         1/1            assign update_stored_value = (diff_ctr_d == thresh_i);
           Tests:       T26 T27 T28 
75         1/1            assign diff_ctr_d = (filter_synced != filter_q) ? '0       :           // restart
           Tests:       T26 T27 T28 
76                                            (diff_ctr_q >= thresh_i)    ? thresh_i :           // saturate
77                                                                          (diff_ctr_q + 1'b1); // count up
78                      
79         1/1            assign filter_o = enable_i ? stored_value_q : filter_synced;
           Tests:       T26 T27 T28 

---

Cond Coverage for Instance : tb.dut.gen_filter[10].u_filter

	Total	Covered	Percent
Conditions	10	10	100.00
Logical	10	10	100.00
Non-Logical	0	0
Event	0	0

 LINE       74
 EXPRESSION (diff_ctr_d == thresh_i)
            ------------1-----------

-1-	Status	Tests
0	Covered	T26,T27,T28
1	Covered	T26,T27,T28

 LINE       75
 EXPRESSION ((filter_synced != filter_q) ? '0 : ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1))))
             -------------1-------------

-1-	Status	Tests
0	Covered	T26,T27,T28
1	Covered	T26,T27,T28

 LINE       75
 SUB-EXPRESSION (filter_synced != filter_q)
                -------------1-------------

-1-	Status	Tests
0	Covered	T26,T27,T28
1	Covered	T26,T27,T28

 LINE       75
 SUB-EXPRESSION ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1)))
                 ------------1-----------

-1-	Status	Tests
0	Covered	T26,T27,T28
1	Covered	T26,T27,T28

 LINE       79
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---

-1-	Status	Tests
0	Covered	T26,T27,T28
1	Covered	T32,T34,T35

---

Branch Coverage for Instance : tb.dut.gen_filter[10].u_filter

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	75	3	3	100.00
TERNARY	79	2	2	100.00
IF	50	2	2	100.00
IF	58	3	3	100.00
IF	66	2	2	100.00

75           assign diff_ctr_d = (filter_synced != filter_q) ? '0       :           // restart
                                                             -1-  
                                                             ==>  
76                               (diff_ctr_q >= thresh_i)    ? thresh_i :           // saturate
                                                             -2-  
                                                             ==>  
                                                             ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T26,T27,T28
0	1	Covered	T26,T27,T28
0	0	Covered	T26,T27,T28

79           assign filter_o = enable_i ? stored_value_q : filter_synced;
                                        -1-  
                                        ==>  
                                        ==>  

Branches:

-1-	Status	Tests
1	Covered	T32,T34,T35
0	Covered	T26,T27,T28

50             if (!rst_ni) begin
               -1-  
51               filter_q <= 1'b0;
                 ==>
52             end else begin
53               filter_q <= filter_synced;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T26,T27,T28
0	Covered	T26,T27,T28

58             if (!rst_ni) begin
               -1-  
59               stored_value_q <= 1'b0;
                 ==>
60             end else if (update_stored_value) begin
                        -2-  
61               stored_value_q <= filter_synced;
                 ==>
62             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T26,T27,T28
0	1	Covered	T26,T27,T28
0	0	Covered	T26,T27,T28

66             if (!rst_ni) begin
               -1-  
67               diff_ctr_q <= '0;
                 ==>
68             end else begin
69               diff_ctr_q <= diff_ctr_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T26,T27,T28
0	Covered	T26,T27,T28

Line Coverage for Instance : tb.dut.gen_filter[11].u_filter

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
CONT_ASSIGN	46	1	1	100.00
ALWAYS	50	3	3	100.00
ALWAYS	58	4	4	100.00
ALWAYS	66	3	3	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	79	1	1	100.00

45                        end else begin : gen_sync
46         1/1              assign filter_synced = filter_i;
           Tests:       T26 T27 T28 
47                        end
48                      
49                        always_ff @(posedge clk_i or negedge rst_ni) begin
50         1/1              if (!rst_ni) begin
           Tests:       T26 T27 T28 
51         1/1                filter_q <= 1'b0;
           Tests:       T26 T27 T28 
52                          end else begin
53         1/1                filter_q <= filter_synced;
           Tests:       T26 T27 T28 
54                          end
55                        end
56                      
57                        always_ff @(posedge clk_i or negedge rst_ni) begin
58         1/1              if (!rst_ni) begin
           Tests:       T26 T27 T28 
59         1/1                stored_value_q <= 1'b0;
           Tests:       T26 T27 T28 
60         1/1              end else if (update_stored_value) begin
           Tests:       T26 T27 T28 
61         1/1                stored_value_q <= filter_synced;
           Tests:       T26 T27 T28 
62                          end
                        MISSING_ELSE
63                        end
64                      
65                        always_ff @(posedge clk_i or negedge rst_ni) begin
66         1/1              if (!rst_ni) begin
           Tests:       T26 T27 T28 
67         1/1                diff_ctr_q <= '0;
           Tests:       T26 T27 T28 
68                          end else begin
69         1/1                diff_ctr_q <= diff_ctr_d;
           Tests:       T26 T27 T28 
70                          end
71                        end
72                      
73                        // always look for differences, even if not filter enabled
74         1/1            assign update_stored_value = (diff_ctr_d == thresh_i);
           Tests:       T26 T27 T28 
75         1/1            assign diff_ctr_d = (filter_synced != filter_q) ? '0       :           // restart
           Tests:       T26 T27 T28 
76                                            (diff_ctr_q >= thresh_i)    ? thresh_i :           // saturate
77                                                                          (diff_ctr_q + 1'b1); // count up
78                      
79         1/1            assign filter_o = enable_i ? stored_value_q : filter_synced;
           Tests:       T26 T27 T28 

---

Cond Coverage for Instance : tb.dut.gen_filter[11].u_filter

	Total	Covered	Percent
Conditions	10	10	100.00
Logical	10	10	100.00
Non-Logical	0	0
Event	0	0

 LINE       74
 EXPRESSION (diff_ctr_d == thresh_i)
            ------------1-----------

-1-	Status	Tests
0	Covered	T26,T27,T28
1	Covered	T26,T27,T28

 LINE       75
 EXPRESSION ((filter_synced != filter_q) ? '0 : ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1))))
             -------------1-------------

-1-	Status	Tests
0	Covered	T26,T27,T28
1	Covered	T26,T27,T28

 LINE       75
 SUB-EXPRESSION (filter_synced != filter_q)
                -------------1-------------

-1-	Status	Tests
0	Covered	T26,T27,T28
1	Covered	T26,T27,T28

 LINE       75
 SUB-EXPRESSION ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1)))
                 ------------1-----------

-1-	Status	Tests
0	Covered	T26,T27,T28
1	Covered	T26,T27,T28

 LINE       79
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---

-1-	Status	Tests
0	Covered	T26,T27,T28
1	Covered	T32,T34,T35

---

Branch Coverage for Instance : tb.dut.gen_filter[11].u_filter

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	75	3	3	100.00
TERNARY	79	2	2	100.00
IF	50	2	2	100.00
IF	58	3	3	100.00
IF	66	2	2	100.00

75           assign diff_ctr_d = (filter_synced != filter_q) ? '0       :           // restart
                                                             -1-  
                                                             ==>  
76                               (diff_ctr_q >= thresh_i)    ? thresh_i :           // saturate
                                                             -2-  
                                                             ==>  
                                                             ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T26,T27,T28
0	1	Covered	T26,T27,T28
0	0	Covered	T26,T27,T28

79           assign filter_o = enable_i ? stored_value_q : filter_synced;
                                        -1-  
                                        ==>  
                                        ==>  

Branches:

-1-	Status	Tests
1	Covered	T32,T34,T35
0	Covered	T26,T27,T28

50             if (!rst_ni) begin
               -1-  
51               filter_q <= 1'b0;
                 ==>
52             end else begin
53               filter_q <= filter_synced;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T26,T27,T28
0	Covered	T26,T27,T28

58             if (!rst_ni) begin
               -1-  
59               stored_value_q <= 1'b0;
                 ==>
60             end else if (update_stored_value) begin
                        -2-  
61               stored_value_q <= filter_synced;
                 ==>
62             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T26,T27,T28
0	1	Covered	T26,T27,T28
0	0	Covered	T26,T27,T28

66             if (!rst_ni) begin
               -1-  
67               diff_ctr_q <= '0;
                 ==>
68             end else begin
69               diff_ctr_q <= diff_ctr_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T26,T27,T28
0	Covered	T26,T27,T28

Line Coverage for Instance : tb.dut.gen_filter[12].u_filter

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
CONT_ASSIGN	46	1	1	100.00
ALWAYS	50	3	3	100.00
ALWAYS	58	4	4	100.00
ALWAYS	66	3	3	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	79	1	1	100.00

45                        end else begin : gen_sync
46         1/1              assign filter_synced = filter_i;
           Tests:       T26 T27 T28 
47                        end
48                      
49                        always_ff @(posedge clk_i or negedge rst_ni) begin
50         1/1              if (!rst_ni) begin
           Tests:       T26 T27 T28 
51         1/1                filter_q <= 1'b0;
           Tests:       T26 T27 T28 
52                          end else begin
53         1/1                filter_q <= filter_synced;
           Tests:       T26 T27 T28 
54                          end
55                        end
56                      
57                        always_ff @(posedge clk_i or negedge rst_ni) begin
58         1/1              if (!rst_ni) begin
           Tests:       T26 T27 T28 
59         1/1                stored_value_q <= 1'b0;
           Tests:       T26 T27 T28 
60         1/1              end else if (update_stored_value) begin
           Tests:       T26 T27 T28 
61         1/1                stored_value_q <= filter_synced;
           Tests:       T26 T27 T28 
62                          end
                        MISSING_ELSE
63                        end
64                      
65                        always_ff @(posedge clk_i or negedge rst_ni) begin
66         1/1              if (!rst_ni) begin
           Tests:       T26 T27 T28 
67         1/1                diff_ctr_q <= '0;
           Tests:       T26 T27 T28 
68                          end else begin
69         1/1                diff_ctr_q <= diff_ctr_d;
           Tests:       T26 T27 T28 
70                          end
71                        end
72                      
73                        // always look for differences, even if not filter enabled
74         1/1            assign update_stored_value = (diff_ctr_d == thresh_i);
           Tests:       T26 T27 T28 
75         1/1            assign diff_ctr_d = (filter_synced != filter_q) ? '0       :           // restart
           Tests:       T26 T27 T28 
76                                            (diff_ctr_q >= thresh_i)    ? thresh_i :           // saturate
77                                                                          (diff_ctr_q + 1'b1); // count up
78                      
79         1/1            assign filter_o = enable_i ? stored_value_q : filter_synced;
           Tests:       T26 T27 T28 

---

Cond Coverage for Instance : tb.dut.gen_filter[12].u_filter

	Total	Covered	Percent
Conditions	10	10	100.00
Logical	10	10	100.00
Non-Logical	0	0
Event	0	0

 LINE       74
 EXPRESSION (diff_ctr_d == thresh_i)
            ------------1-----------

-1-	Status	Tests
0	Covered	T26,T27,T28
1	Covered	T26,T27,T28

 LINE       75
 EXPRESSION ((filter_synced != filter_q) ? '0 : ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1))))
             -------------1-------------

-1-	Status	Tests
0	Covered	T26,T27,T28
1	Covered	T26,T27,T28

 LINE       75
 SUB-EXPRESSION (filter_synced != filter_q)
                -------------1-------------

-1-	Status	Tests
0	Covered	T26,T27,T28
1	Covered	T26,T27,T28

 LINE       75
 SUB-EXPRESSION ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1)))
                 ------------1-----------

-1-	Status	Tests
0	Covered	T26,T27,T28
1	Covered	T26,T27,T28

 LINE       79
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---

-1-	Status	Tests
0	Covered	T26,T27,T28
1	Covered	T32,T34,T35

---

Branch Coverage for Instance : tb.dut.gen_filter[12].u_filter

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	75	3	3	100.00
TERNARY	79	2	2	100.00
IF	50	2	2	100.00
IF	58	3	3	100.00
IF	66	2	2	100.00

75           assign diff_ctr_d = (filter_synced != filter_q) ? '0       :           // restart
                                                             -1-  
                                                             ==>  
76                               (diff_ctr_q >= thresh_i)    ? thresh_i :           // saturate
                                                             -2-  
                                                             ==>  
                                                             ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T26,T27,T28
0	1	Covered	T26,T27,T28
0	0	Covered	T26,T27,T28

79           assign filter_o = enable_i ? stored_value_q : filter_synced;
                                        -1-  
                                        ==>  
                                        ==>  

Branches:

-1-	Status	Tests
1	Covered	T32,T34,T35
0	Covered	T26,T27,T28

50             if (!rst_ni) begin
               -1-  
51               filter_q <= 1'b0;
                 ==>
52             end else begin
53               filter_q <= filter_synced;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T26,T27,T28
0	Covered	T26,T27,T28

58             if (!rst_ni) begin
               -1-  
59               stored_value_q <= 1'b0;
                 ==>
60             end else if (update_stored_value) begin
                        -2-  
61               stored_value_q <= filter_synced;
                 ==>
62             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T26,T27,T28
0	1	Covered	T26,T27,T28
0	0	Covered	T26,T27,T28

66             if (!rst_ni) begin
               -1-  
67               diff_ctr_q <= '0;
                 ==>
68             end else begin
69               diff_ctr_q <= diff_ctr_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T26,T27,T28
0	Covered	T26,T27,T28

Line Coverage for Instance : tb.dut.gen_filter[13].u_filter

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
CONT_ASSIGN	46	1	1	100.00
ALWAYS	50	3	3	100.00
ALWAYS	58	4	4	100.00
ALWAYS	66	3	3	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	79	1	1	100.00

45                        end else begin : gen_sync
46         1/1              assign filter_synced = filter_i;
           Tests:       T26 T27 T28 
47                        end
48                      
49                        always_ff @(posedge clk_i or negedge rst_ni) begin
50         1/1              if (!rst_ni) begin
           Tests:       T26 T27 T28 
51         1/1                filter_q <= 1'b0;
           Tests:       T26 T27 T28 
52                          end else begin
53         1/1                filter_q <= filter_synced;
           Tests:       T26 T27 T28 
54                          end
55                        end
56                      
57                        always_ff @(posedge clk_i or negedge rst_ni) begin
58         1/1              if (!rst_ni) begin
           Tests:       T26 T27 T28 
59         1/1                stored_value_q <= 1'b0;
           Tests:       T26 T27 T28 
60         1/1              end else if (update_stored_value) begin
           Tests:       T26 T27 T28 
61         1/1                stored_value_q <= filter_synced;
           Tests:       T26 T27 T28 
62                          end
                        MISSING_ELSE
63                        end
64                      
65                        always_ff @(posedge clk_i or negedge rst_ni) begin
66         1/1              if (!rst_ni) begin
           Tests:       T26 T27 T28 
67         1/1                diff_ctr_q <= '0;
           Tests:       T26 T27 T28 
68                          end else begin
69         1/1                diff_ctr_q <= diff_ctr_d;
           Tests:       T26 T27 T28 
70                          end
71                        end
72                      
73                        // always look for differences, even if not filter enabled
74         1/1            assign update_stored_value = (diff_ctr_d == thresh_i);
           Tests:       T26 T27 T28 
75         1/1            assign diff_ctr_d = (filter_synced != filter_q) ? '0       :           // restart
           Tests:       T26 T27 T28 
76                                            (diff_ctr_q >= thresh_i)    ? thresh_i :           // saturate
77                                                                          (diff_ctr_q + 1'b1); // count up
78                      
79         1/1            assign filter_o = enable_i ? stored_value_q : filter_synced;
           Tests:       T26 T27 T28 

---

Cond Coverage for Instance : tb.dut.gen_filter[13].u_filter

	Total	Covered	Percent
Conditions	10	10	100.00
Logical	10	10	100.00
Non-Logical	0	0
Event	0	0

 LINE       74
 EXPRESSION (diff_ctr_d == thresh_i)
            ------------1-----------

-1-	Status	Tests
0	Covered	T26,T27,T28
1	Covered	T26,T27,T28

 LINE       75
 EXPRESSION ((filter_synced != filter_q) ? '0 : ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1))))
             -------------1-------------

-1-	Status	Tests
0	Covered	T26,T27,T28
1	Covered	T26,T27,T28

 LINE       75
 SUB-EXPRESSION (filter_synced != filter_q)
                -------------1-------------

-1-	Status	Tests
0	Covered	T26,T27,T28
1	Covered	T26,T27,T28

 LINE       75
 SUB-EXPRESSION ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1)))
                 ------------1-----------

-1-	Status	Tests
0	Covered	T26,T27,T28
1	Covered	T26,T27,T28

 LINE       79
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---

-1-	Status	Tests
0	Covered	T26,T27,T28
1	Covered	T32,T34,T35

---

Branch Coverage for Instance : tb.dut.gen_filter[13].u_filter

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	75	3	3	100.00
TERNARY	79	2	2	100.00
IF	50	2	2	100.00
IF	58	3	3	100.00
IF	66	2	2	100.00

75           assign diff_ctr_d = (filter_synced != filter_q) ? '0       :           // restart
                                                             -1-  
                                                             ==>  
76                               (diff_ctr_q >= thresh_i)    ? thresh_i :           // saturate
                                                             -2-  
                                                             ==>  
                                                             ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T26,T27,T28
0	1	Covered	T26,T27,T28
0	0	Covered	T26,T27,T28

79           assign filter_o = enable_i ? stored_value_q : filter_synced;
                                        -1-  
                                        ==>  
                                        ==>  

Branches:

-1-	Status	Tests
1	Covered	T32,T34,T35
0	Covered	T26,T27,T28

50             if (!rst_ni) begin
               -1-  
51               filter_q <= 1'b0;
                 ==>
52             end else begin
53               filter_q <= filter_synced;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T26,T27,T28
0	Covered	T26,T27,T28

58             if (!rst_ni) begin
               -1-  
59               stored_value_q <= 1'b0;
                 ==>
60             end else if (update_stored_value) begin
                        -2-  
61               stored_value_q <= filter_synced;
                 ==>
62             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T26,T27,T28
0	1	Covered	T26,T27,T28
0	0	Covered	T26,T27,T28

66             if (!rst_ni) begin
               -1-  
67               diff_ctr_q <= '0;
                 ==>
68             end else begin
69               diff_ctr_q <= diff_ctr_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T26,T27,T28
0	Covered	T26,T27,T28

Line Coverage for Instance : tb.dut.gen_filter[14].u_filter

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
CONT_ASSIGN	46	1	1	100.00
ALWAYS	50	3	3	100.00
ALWAYS	58	4	4	100.00
ALWAYS	66	3	3	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	79	1	1	100.00

45                        end else begin : gen_sync
46         1/1              assign filter_synced = filter_i;
           Tests:       T26 T27 T28 
47                        end
48                      
49                        always_ff @(posedge clk_i or negedge rst_ni) begin
50         1/1              if (!rst_ni) begin
           Tests:       T26 T27 T28 
51         1/1                filter_q <= 1'b0;
           Tests:       T26 T27 T28 
52                          end else begin
53         1/1                filter_q <= filter_synced;
           Tests:       T26 T27 T28 
54                          end
55                        end
56                      
57                        always_ff @(posedge clk_i or negedge rst_ni) begin
58         1/1              if (!rst_ni) begin
           Tests:       T26 T27 T28 
59         1/1                stored_value_q <= 1'b0;
           Tests:       T26 T27 T28 
60         1/1              end else if (update_stored_value) begin
           Tests:       T26 T27 T28 
61         1/1                stored_value_q <= filter_synced;
           Tests:       T26 T27 T28 
62                          end
                        MISSING_ELSE
63                        end
64                      
65                        always_ff @(posedge clk_i or negedge rst_ni) begin
66         1/1              if (!rst_ni) begin
           Tests:       T26 T27 T28 
67         1/1                diff_ctr_q <= '0;
           Tests:       T26 T27 T28 
68                          end else begin
69         1/1                diff_ctr_q <= diff_ctr_d;
           Tests:       T26 T27 T28 
70                          end
71                        end
72                      
73                        // always look for differences, even if not filter enabled
74         1/1            assign update_stored_value = (diff_ctr_d == thresh_i);
           Tests:       T26 T27 T28 
75         1/1            assign diff_ctr_d = (filter_synced != filter_q) ? '0       :           // restart
           Tests:       T26 T27 T28 
76                                            (diff_ctr_q >= thresh_i)    ? thresh_i :           // saturate
77                                                                          (diff_ctr_q + 1'b1); // count up
78                      
79         1/1            assign filter_o = enable_i ? stored_value_q : filter_synced;
           Tests:       T26 T27 T28 

---

Cond Coverage for Instance : tb.dut.gen_filter[14].u_filter

	Total	Covered	Percent
Conditions	10	10	100.00
Logical	10	10	100.00
Non-Logical	0	0
Event	0	0

 LINE       74
 EXPRESSION (diff_ctr_d == thresh_i)
            ------------1-----------

-1-	Status	Tests
0	Covered	T26,T27,T28
1	Covered	T26,T27,T28

 LINE       75
 EXPRESSION ((filter_synced != filter_q) ? '0 : ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1))))
             -------------1-------------

-1-	Status	Tests
0	Covered	T26,T27,T28
1	Covered	T26,T27,T28

 LINE       75
 SUB-EXPRESSION (filter_synced != filter_q)
                -------------1-------------

-1-	Status	Tests
0	Covered	T26,T27,T28
1	Covered	T26,T27,T28

 LINE       75
 SUB-EXPRESSION ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1)))
                 ------------1-----------

-1-	Status	Tests
0	Covered	T26,T27,T28
1	Covered	T26,T27,T28

 LINE       79
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---

-1-	Status	Tests
0	Covered	T26,T27,T28
1	Covered	T32,T34,T35

---

Branch Coverage for Instance : tb.dut.gen_filter[14].u_filter

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	75	3	3	100.00
TERNARY	79	2	2	100.00
IF	50	2	2	100.00
IF	58	3	3	100.00
IF	66	2	2	100.00

75           assign diff_ctr_d = (filter_synced != filter_q) ? '0       :           // restart
                                                             -1-  
                                                             ==>  
76                               (diff_ctr_q >= thresh_i)    ? thresh_i :           // saturate
                                                             -2-  
                                                             ==>  
                                                             ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T26,T27,T28
0	1	Covered	T26,T27,T28
0	0	Covered	T26,T27,T28

79           assign filter_o = enable_i ? stored_value_q : filter_synced;
                                        -1-  
                                        ==>  
                                        ==>  

Branches:

-1-	Status	Tests
1	Covered	T32,T34,T35
0	Covered	T26,T27,T28

50             if (!rst_ni) begin
               -1-  
51               filter_q <= 1'b0;
                 ==>
52             end else begin
53               filter_q <= filter_synced;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T26,T27,T28
0	Covered	T26,T27,T28

58             if (!rst_ni) begin
               -1-  
59               stored_value_q <= 1'b0;
                 ==>
60             end else if (update_stored_value) begin
                        -2-  
61               stored_value_q <= filter_synced;
                 ==>
62             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T26,T27,T28
0	1	Covered	T26,T27,T28
0	0	Covered	T26,T27,T28

66             if (!rst_ni) begin
               -1-  
67               diff_ctr_q <= '0;
                 ==>
68             end else begin
69               diff_ctr_q <= diff_ctr_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T26,T27,T28
0	Covered	T26,T27,T28

Line Coverage for Instance : tb.dut.gen_filter[15].u_filter

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
CONT_ASSIGN	46	1	1	100.00
ALWAYS	50	3	3	100.00
ALWAYS	58	4	4	100.00
ALWAYS	66	3	3	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	79	1	1	100.00

45                        end else begin : gen_sync
46         1/1              assign filter_synced = filter_i;
           Tests:       T26 T27 T28 
47                        end
48                      
49                        always_ff @(posedge clk_i or negedge rst_ni) begin
50         1/1              if (!rst_ni) begin
           Tests:       T26 T27 T28 
51         1/1                filter_q <= 1'b0;
           Tests:       T26 T27 T28 
52                          end else begin
53         1/1                filter_q <= filter_synced;
           Tests:       T26 T27 T28 
54                          end
55                        end
56                      
57                        always_ff @(posedge clk_i or negedge rst_ni) begin
58         1/1              if (!rst_ni) begin
           Tests:       T26 T27 T28 
59         1/1                stored_value_q <= 1'b0;
           Tests:       T26 T27 T28 
60         1/1              end else if (update_stored_value) begin
           Tests:       T26 T27 T28 
61         1/1                stored_value_q <= filter_synced;
           Tests:       T26 T27 T28 
62                          end
                        MISSING_ELSE
63                        end
64                      
65                        always_ff @(posedge clk_i or negedge rst_ni) begin
66         1/1              if (!rst_ni) begin
           Tests:       T26 T27 T28 
67         1/1                diff_ctr_q <= '0;
           Tests:       T26 T27 T28 
68                          end else begin
69         1/1                diff_ctr_q <= diff_ctr_d;
           Tests:       T26 T27 T28 
70                          end
71                        end
72                      
73                        // always look for differences, even if not filter enabled
74         1/1            assign update_stored_value = (diff_ctr_d == thresh_i);
           Tests:       T26 T27 T28 
75         1/1            assign diff_ctr_d = (filter_synced != filter_q) ? '0       :           // restart
           Tests:       T26 T27 T28 
76                                            (diff_ctr_q >= thresh_i)    ? thresh_i :           // saturate
77                                                                          (diff_ctr_q + 1'b1); // count up
78                      
79         1/1            assign filter_o = enable_i ? stored_value_q : filter_synced;
           Tests:       T26 T27 T28 

---

Cond Coverage for Instance : tb.dut.gen_filter[15].u_filter

	Total	Covered	Percent
Conditions	10	10	100.00
Logical	10	10	100.00
Non-Logical	0	0
Event	0	0

 LINE       74
 EXPRESSION (diff_ctr_d == thresh_i)
            ------------1-----------

-1-	Status	Tests
0	Covered	T26,T27,T28
1	Covered	T26,T27,T28

 LINE       75
 EXPRESSION ((filter_synced != filter_q) ? '0 : ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1))))
             -------------1-------------

-1-	Status	Tests
0	Covered	T26,T27,T28
1	Covered	T26,T27,T28

 LINE       75
 SUB-EXPRESSION (filter_synced != filter_q)
                -------------1-------------

-1-	Status	Tests
0	Covered	T26,T27,T28
1	Covered	T26,T27,T28

 LINE       75
 SUB-EXPRESSION ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1)))
                 ------------1-----------

-1-	Status	Tests
0	Covered	T26,T27,T28
1	Covered	T26,T27,T28

 LINE       79
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---

-1-	Status	Tests
0	Covered	T26,T27,T28
1	Covered	T32,T34,T35

---

Branch Coverage for Instance : tb.dut.gen_filter[15].u_filter

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	75	3	3	100.00
TERNARY	79	2	2	100.00
IF	50	2	2	100.00
IF	58	3	3	100.00
IF	66	2	2	100.00

75           assign diff_ctr_d = (filter_synced != filter_q) ? '0       :           // restart
                                                             -1-  
                                                             ==>  
76                               (diff_ctr_q >= thresh_i)    ? thresh_i :           // saturate
                                                             -2-  
                                                             ==>  
                                                             ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T26,T27,T28
0	1	Covered	T26,T27,T28
0	0	Covered	T26,T27,T28

79           assign filter_o = enable_i ? stored_value_q : filter_synced;
                                        -1-  
                                        ==>  
                                        ==>  

Branches:

-1-	Status	Tests
1	Covered	T32,T34,T35
0	Covered	T26,T27,T28

50             if (!rst_ni) begin
               -1-  
51               filter_q <= 1'b0;
                 ==>
52             end else begin
53               filter_q <= filter_synced;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T26,T27,T28
0	Covered	T26,T27,T28

58             if (!rst_ni) begin
               -1-  
59               stored_value_q <= 1'b0;
                 ==>
60             end else if (update_stored_value) begin
                        -2-  
61               stored_value_q <= filter_synced;
                 ==>
62             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T26,T27,T28
0	1	Covered	T26,T27,T28
0	0	Covered	T26,T27,T28

66             if (!rst_ni) begin
               -1-  
67               diff_ctr_q <= '0;
                 ==>
68             end else begin
69               diff_ctr_q <= diff_ctr_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T26,T27,T28
0	Covered	T26,T27,T28

Line Coverage for Instance : tb.dut.gen_filter[16].u_filter

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
CONT_ASSIGN	46	1	1	100.00
ALWAYS	50	3	3	100.00
ALWAYS	58	4	4	100.00
ALWAYS	66	3	3	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	79	1	1	100.00

45                        end else begin : gen_sync
46         1/1              assign filter_synced = filter_i;
           Tests:       T26 T27 T28 
47                        end
48                      
49                        always_ff @(posedge clk_i or negedge rst_ni) begin
50         1/1              if (!rst_ni) begin
           Tests:       T26 T27 T28 
51         1/1                filter_q <= 1'b0;
           Tests:       T26 T27 T28 
52                          end else begin
53         1/1                filter_q <= filter_synced;
           Tests:       T26 T27 T28 
54                          end
55                        end
56                      
57                        always_ff @(posedge clk_i or negedge rst_ni) begin
58         1/1              if (!rst_ni) begin
           Tests:       T26 T27 T28 
59         1/1                stored_value_q <= 1'b0;
           Tests:       T26 T27 T28 
60         1/1              end else if (update_stored_value) begin
           Tests:       T26 T27 T28 
61         1/1                stored_value_q <= filter_synced;
           Tests:       T26 T27 T28 
62                          end
                        MISSING_ELSE
63                        end
64                      
65                        always_ff @(posedge clk_i or negedge rst_ni) begin
66         1/1              if (!rst_ni) begin
           Tests:       T26 T27 T28 
67         1/1                diff_ctr_q <= '0;
           Tests:       T26 T27 T28 
68                          end else begin
69         1/1                diff_ctr_q <= diff_ctr_d;
           Tests:       T26 T27 T28 
70                          end
71                        end
72                      
73                        // always look for differences, even if not filter enabled
74         1/1            assign update_stored_value = (diff_ctr_d == thresh_i);
           Tests:       T26 T27 T28 
75         1/1            assign diff_ctr_d = (filter_synced != filter_q) ? '0       :           // restart
           Tests:       T26 T27 T28 
76                                            (diff_ctr_q >= thresh_i)    ? thresh_i :           // saturate
77                                                                          (diff_ctr_q + 1'b1); // count up
78                      
79         1/1            assign filter_o = enable_i ? stored_value_q : filter_synced;
           Tests:       T26 T27 T28 

---

Cond Coverage for Instance : tb.dut.gen_filter[16].u_filter

	Total	Covered	Percent
Conditions	10	10	100.00
Logical	10	10	100.00
Non-Logical	0	0
Event	0	0

 LINE       74
 EXPRESSION (diff_ctr_d == thresh_i)
            ------------1-----------

-1-	Status	Tests
0	Covered	T26,T27,T28
1	Covered	T26,T27,T28

 LINE       75
 EXPRESSION ((filter_synced != filter_q) ? '0 : ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1))))
             -------------1-------------

-1-	Status	Tests
0	Covered	T26,T27,T28
1	Covered	T26,T27,T28

 LINE       75
 SUB-EXPRESSION (filter_synced != filter_q)
                -------------1-------------

-1-	Status	Tests
0	Covered	T26,T27,T28
1	Covered	T26,T27,T28

 LINE       75
 SUB-EXPRESSION ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1)))
                 ------------1-----------

-1-	Status	Tests
0	Covered	T26,T27,T28
1	Covered	T26,T27,T28

 LINE       79
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---

-1-	Status	Tests
0	Covered	T26,T27,T28
1	Covered	T32,T34,T35

---

Branch Coverage for Instance : tb.dut.gen_filter[16].u_filter

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	75	3	3	100.00
TERNARY	79	2	2	100.00
IF	50	2	2	100.00
IF	58	3	3	100.00
IF	66	2	2	100.00

75           assign diff_ctr_d = (filter_synced != filter_q) ? '0       :           // restart
                                                             -1-  
                                                             ==>  
76                               (diff_ctr_q >= thresh_i)    ? thresh_i :           // saturate
                                                             -2-  
                                                             ==>  
                                                             ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T26,T27,T28
0	1	Covered	T26,T27,T28
0	0	Covered	T26,T27,T28

79           assign filter_o = enable_i ? stored_value_q : filter_synced;
                                        -1-  
                                        ==>  
                                        ==>  

Branches:

-1-	Status	Tests
1	Covered	T32,T34,T35
0	Covered	T26,T27,T28

50             if (!rst_ni) begin
               -1-  
51               filter_q <= 1'b0;
                 ==>
52             end else begin
53               filter_q <= filter_synced;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T26,T27,T28
0	Covered	T26,T27,T28

58             if (!rst_ni) begin
               -1-  
59               stored_value_q <= 1'b0;
                 ==>
60             end else if (update_stored_value) begin
                        -2-  
61               stored_value_q <= filter_synced;
                 ==>
62             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T26,T27,T28
0	1	Covered	T26,T27,T28
0	0	Covered	T26,T27,T28

66             if (!rst_ni) begin
               -1-  
67               diff_ctr_q <= '0;
                 ==>
68             end else begin
69               diff_ctr_q <= diff_ctr_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T26,T27,T28
0	Covered	T26,T27,T28

Line Coverage for Instance : tb.dut.gen_filter[17].u_filter

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
CONT_ASSIGN	46	1	1	100.00
ALWAYS	50	3	3	100.00
ALWAYS	58	4	4	100.00
ALWAYS	66	3	3	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	79	1	1	100.00

45                        end else begin : gen_sync
46         1/1              assign filter_synced = filter_i;
           Tests:       T26 T27 T28 
47                        end
48                      
49                        always_ff @(posedge clk_i or negedge rst_ni) begin
50         1/1              if (!rst_ni) begin
           Tests:       T26 T27 T28 
51         1/1                filter_q <= 1'b0;
           Tests:       T26 T27 T28 
52                          end else begin
53         1/1                filter_q <= filter_synced;
           Tests:       T26 T27 T28 
54                          end
55                        end
56                      
57                        always_ff @(posedge clk_i or negedge rst_ni) begin
58         1/1              if (!rst_ni) begin
           Tests:       T26 T27 T28 
59         1/1                stored_value_q <= 1'b0;
           Tests:       T26 T27 T28 
60         1/1              end else if (update_stored_value) begin
           Tests:       T26 T27 T28 
61         1/1                stored_value_q <= filter_synced;
           Tests:       T26 T27 T28 
62                          end
                        MISSING_ELSE
63                        end
64                      
65                        always_ff @(posedge clk_i or negedge rst_ni) begin
66         1/1              if (!rst_ni) begin
           Tests:       T26 T27 T28 
67         1/1                diff_ctr_q <= '0;
           Tests:       T26 T27 T28 
68                          end else begin
69         1/1                diff_ctr_q <= diff_ctr_d;
           Tests:       T26 T27 T28 
70                          end
71                        end
72                      
73                        // always look for differences, even if not filter enabled
74         1/1            assign update_stored_value = (diff_ctr_d == thresh_i);
           Tests:       T26 T27 T28 
75         1/1            assign diff_ctr_d = (filter_synced != filter_q) ? '0       :           // restart
           Tests:       T26 T27 T28 
76                                            (diff_ctr_q >= thresh_i)    ? thresh_i :           // saturate
77                                                                          (diff_ctr_q + 1'b1); // count up
78                      
79         1/1            assign filter_o = enable_i ? stored_value_q : filter_synced;
           Tests:       T26 T27 T28 

---

Cond Coverage for Instance : tb.dut.gen_filter[17].u_filter

	Total	Covered	Percent
Conditions	10	10	100.00
Logical	10	10	100.00
Non-Logical	0	0
Event	0	0

 LINE       74
 EXPRESSION (diff_ctr_d == thresh_i)
            ------------1-----------

-1-	Status	Tests
0	Covered	T26,T27,T28
1	Covered	T26,T27,T28

 LINE       75
 EXPRESSION ((filter_synced != filter_q) ? '0 : ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1))))
             -------------1-------------

-1-	Status	Tests
0	Covered	T26,T27,T28
1	Covered	T26,T27,T28

 LINE       75
 SUB-EXPRESSION (filter_synced != filter_q)
                -------------1-------------

-1-	Status	Tests
0	Covered	T26,T27,T28
1	Covered	T26,T27,T28

 LINE       75
 SUB-EXPRESSION ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1)))
                 ------------1-----------

-1-	Status	Tests
0	Covered	T26,T27,T28
1	Covered	T26,T27,T28

 LINE       79
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---

-1-	Status	Tests
0	Covered	T26,T27,T28
1	Covered	T32,T34,T35

---

Branch Coverage for Instance : tb.dut.gen_filter[17].u_filter

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	75	3	3	100.00
TERNARY	79	2	2	100.00
IF	50	2	2	100.00
IF	58	3	3	100.00
IF	66	2	2	100.00

75           assign diff_ctr_d = (filter_synced != filter_q) ? '0       :           // restart
                                                             -1-  
                                                             ==>  
76                               (diff_ctr_q >= thresh_i)    ? thresh_i :           // saturate
                                                             -2-  
                                                             ==>  
                                                             ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T26,T27,T28
0	1	Covered	T26,T27,T28
0	0	Covered	T26,T27,T28

79           assign filter_o = enable_i ? stored_value_q : filter_synced;
                                        -1-  
                                        ==>  
                                        ==>  

Branches:

-1-	Status	Tests
1	Covered	T32,T34,T35
0	Covered	T26,T27,T28

50             if (!rst_ni) begin
               -1-  
51               filter_q <= 1'b0;
                 ==>
52             end else begin
53               filter_q <= filter_synced;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T26,T27,T28
0	Covered	T26,T27,T28

58             if (!rst_ni) begin
               -1-  
59               stored_value_q <= 1'b0;
                 ==>
60             end else if (update_stored_value) begin
                        -2-  
61               stored_value_q <= filter_synced;
                 ==>
62             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T26,T27,T28
0	1	Covered	T26,T27,T28
0	0	Covered	T26,T27,T28

66             if (!rst_ni) begin
               -1-  
67               diff_ctr_q <= '0;
                 ==>
68             end else begin
69               diff_ctr_q <= diff_ctr_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T26,T27,T28
0	Covered	T26,T27,T28

Line Coverage for Instance : tb.dut.gen_filter[18].u_filter

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
CONT_ASSIGN	46	1	1	100.00
ALWAYS	50	3	3	100.00
ALWAYS	58	4	4	100.00
ALWAYS	66	3	3	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	79	1	1	100.00

45                        end else begin : gen_sync
46         1/1              assign filter_synced = filter_i;
           Tests:       T26 T27 T28 
47                        end
48                      
49                        always_ff @(posedge clk_i or negedge rst_ni) begin
50         1/1              if (!rst_ni) begin
           Tests:       T26 T27 T28 
51         1/1                filter_q <= 1'b0;
           Tests:       T26 T27 T28 
52                          end else begin
53         1/1                filter_q <= filter_synced;
           Tests:       T26 T27 T28 
54                          end
55                        end
56                      
57                        always_ff @(posedge clk_i or negedge rst_ni) begin
58         1/1              if (!rst_ni) begin
           Tests:       T26 T27 T28 
59         1/1                stored_value_q <= 1'b0;
           Tests:       T26 T27 T28 
60         1/1              end else if (update_stored_value) begin
           Tests:       T26 T27 T28 
61         1/1                stored_value_q <= filter_synced;
           Tests:       T26 T27 T28 
62                          end
                        MISSING_ELSE
63                        end
64                      
65                        always_ff @(posedge clk_i or negedge rst_ni) begin
66         1/1              if (!rst_ni) begin
           Tests:       T26 T27 T28 
67         1/1                diff_ctr_q <= '0;
           Tests:       T26 T27 T28 
68                          end else begin
69         1/1                diff_ctr_q <= diff_ctr_d;
           Tests:       T26 T27 T28 
70                          end
71                        end
72                      
73                        // always look for differences, even if not filter enabled
74         1/1            assign update_stored_value = (diff_ctr_d == thresh_i);
           Tests:       T26 T27 T28 
75         1/1            assign diff_ctr_d = (filter_synced != filter_q) ? '0       :           // restart
           Tests:       T26 T27 T28 
76                                            (diff_ctr_q >= thresh_i)    ? thresh_i :           // saturate
77                                                                          (diff_ctr_q + 1'b1); // count up
78                      
79         1/1            assign filter_o = enable_i ? stored_value_q : filter_synced;
           Tests:       T26 T27 T28 

---

Cond Coverage for Instance : tb.dut.gen_filter[18].u_filter

	Total	Covered	Percent
Conditions	10	10	100.00
Logical	10	10	100.00
Non-Logical	0	0
Event	0	0

 LINE       74
 EXPRESSION (diff_ctr_d == thresh_i)
            ------------1-----------

-1-	Status	Tests
0	Covered	T26,T27,T28
1	Covered	T26,T27,T28

 LINE       75
 EXPRESSION ((filter_synced != filter_q) ? '0 : ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1))))
             -------------1-------------

-1-	Status	Tests
0	Covered	T26,T27,T28
1	Covered	T26,T27,T28

 LINE       75
 SUB-EXPRESSION (filter_synced != filter_q)
                -------------1-------------

-1-	Status	Tests
0	Covered	T26,T27,T28
1	Covered	T26,T27,T28

 LINE       75
 SUB-EXPRESSION ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1)))
                 ------------1-----------

-1-	Status	Tests
0	Covered	T26,T27,T28
1	Covered	T26,T27,T28

 LINE       79
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---

-1-	Status	Tests
0	Covered	T26,T27,T28
1	Covered	T32,T34,T35

---

Branch Coverage for Instance : tb.dut.gen_filter[18].u_filter

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	75	3	3	100.00
TERNARY	79	2	2	100.00
IF	50	2	2	100.00
IF	58	3	3	100.00
IF	66	2	2	100.00

75           assign diff_ctr_d = (filter_synced != filter_q) ? '0       :           // restart
                                                             -1-  
                                                             ==>  
76                               (diff_ctr_q >= thresh_i)    ? thresh_i :           // saturate
                                                             -2-  
                                                             ==>  
                                                             ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T26,T27,T28
0	1	Covered	T26,T27,T28
0	0	Covered	T26,T27,T28

79           assign filter_o = enable_i ? stored_value_q : filter_synced;
                                        -1-  
                                        ==>  
                                        ==>  

Branches:

-1-	Status	Tests
1	Covered	T32,T34,T35
0	Covered	T26,T27,T28

50             if (!rst_ni) begin
               -1-  
51               filter_q <= 1'b0;
                 ==>
52             end else begin
53               filter_q <= filter_synced;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T26,T27,T28
0	Covered	T26,T27,T28

58             if (!rst_ni) begin
               -1-  
59               stored_value_q <= 1'b0;
                 ==>
60             end else if (update_stored_value) begin
                        -2-  
61               stored_value_q <= filter_synced;
                 ==>
62             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T26,T27,T28
0	1	Covered	T26,T27,T28
0	0	Covered	T26,T27,T28

66             if (!rst_ni) begin
               -1-  
67               diff_ctr_q <= '0;
                 ==>
68             end else begin
69               diff_ctr_q <= diff_ctr_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T26,T27,T28
0	Covered	T26,T27,T28

Line Coverage for Instance : tb.dut.gen_filter[19].u_filter

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
CONT_ASSIGN	46	1	1	100.00
ALWAYS	50	3	3	100.00
ALWAYS	58	4	4	100.00
ALWAYS	66	3	3	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	79	1	1	100.00

45                        end else begin : gen_sync
46         1/1              assign filter_synced = filter_i;
           Tests:       T26 T27 T28 
47                        end
48                      
49                        always_ff @(posedge clk_i or negedge rst_ni) begin
50         1/1              if (!rst_ni) begin
           Tests:       T26 T27 T28 
51         1/1                filter_q <= 1'b0;
           Tests:       T26 T27 T28 
52                          end else begin
53         1/1                filter_q <= filter_synced;
           Tests:       T26 T27 T28 
54                          end
55                        end
56                      
57                        always_ff @(posedge clk_i or negedge rst_ni) begin
58         1/1              if (!rst_ni) begin
           Tests:       T26 T27 T28 
59         1/1                stored_value_q <= 1'b0;
           Tests:       T26 T27 T28 
60         1/1              end else if (update_stored_value) begin
           Tests:       T26 T27 T28 
61         1/1                stored_value_q <= filter_synced;
           Tests:       T26 T27 T28 
62                          end
                        MISSING_ELSE
63                        end
64                      
65                        always_ff @(posedge clk_i or negedge rst_ni) begin
66         1/1              if (!rst_ni) begin
           Tests:       T26 T27 T28 
67         1/1                diff_ctr_q <= '0;
           Tests:       T26 T27 T28 
68                          end else begin
69         1/1                diff_ctr_q <= diff_ctr_d;
           Tests:       T26 T27 T28 
70                          end
71                        end
72                      
73                        // always look for differences, even if not filter enabled
74         1/1            assign update_stored_value = (diff_ctr_d == thresh_i);
           Tests:       T26 T27 T28 
75         1/1            assign diff_ctr_d = (filter_synced != filter_q) ? '0       :           // restart
           Tests:       T26 T27 T28 
76                                            (diff_ctr_q >= thresh_i)    ? thresh_i :           // saturate
77                                                                          (diff_ctr_q + 1'b1); // count up
78                      
79         1/1            assign filter_o = enable_i ? stored_value_q : filter_synced;
           Tests:       T26 T27 T28 

---

Cond Coverage for Instance : tb.dut.gen_filter[19].u_filter

	Total	Covered	Percent
Conditions	10	10	100.00
Logical	10	10	100.00
Non-Logical	0	0
Event	0	0

 LINE       74
 EXPRESSION (diff_ctr_d == thresh_i)
            ------------1-----------

-1-	Status	Tests
0	Covered	T26,T27,T28
1	Covered	T26,T27,T28

 LINE       75
 EXPRESSION ((filter_synced != filter_q) ? '0 : ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1))))
             -------------1-------------

-1-	Status	Tests
0	Covered	T26,T27,T28
1	Covered	T26,T27,T28

 LINE       75
 SUB-EXPRESSION (filter_synced != filter_q)
                -------------1-------------

-1-	Status	Tests
0	Covered	T26,T27,T28
1	Covered	T26,T27,T28

 LINE       75
 SUB-EXPRESSION ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1)))
                 ------------1-----------

-1-	Status	Tests
0	Covered	T26,T27,T28
1	Covered	T26,T27,T28

 LINE       79
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---

-1-	Status	Tests
0	Covered	T26,T27,T28
1	Covered	T32,T34,T35

---

Branch Coverage for Instance : tb.dut.gen_filter[19].u_filter

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	75	3	3	100.00
TERNARY	79	2	2	100.00
IF	50	2	2	100.00
IF	58	3	3	100.00
IF	66	2	2	100.00

75           assign diff_ctr_d = (filter_synced != filter_q) ? '0       :           // restart
                                                             -1-  
                                                             ==>  
76                               (diff_ctr_q >= thresh_i)    ? thresh_i :           // saturate
                                                             -2-  
                                                             ==>  
                                                             ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T26,T27,T28
0	1	Covered	T26,T27,T28
0	0	Covered	T26,T27,T28

79           assign filter_o = enable_i ? stored_value_q : filter_synced;
                                        -1-  
                                        ==>  
                                        ==>  

Branches:

-1-	Status	Tests
1	Covered	T32,T34,T35
0	Covered	T26,T27,T28

50             if (!rst_ni) begin
               -1-  
51               filter_q <= 1'b0;
                 ==>
52             end else begin
53               filter_q <= filter_synced;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T26,T27,T28
0	Covered	T26,T27,T28

58             if (!rst_ni) begin
               -1-  
59               stored_value_q <= 1'b0;
                 ==>
60             end else if (update_stored_value) begin
                        -2-  
61               stored_value_q <= filter_synced;
                 ==>
62             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T26,T27,T28
0	1	Covered	T26,T27,T28
0	0	Covered	T26,T27,T28

66             if (!rst_ni) begin
               -1-  
67               diff_ctr_q <= '0;
                 ==>
68             end else begin
69               diff_ctr_q <= diff_ctr_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T26,T27,T28
0	Covered	T26,T27,T28

Line Coverage for Instance : tb.dut.gen_filter[20].u_filter

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
CONT_ASSIGN	46	1	1	100.00
ALWAYS	50	3	3	100.00
ALWAYS	58	4	4	100.00
ALWAYS	66	3	3	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	79	1	1	100.00

45                        end else begin : gen_sync
46         1/1              assign filter_synced = filter_i;
           Tests:       T26 T27 T28 
47                        end
48                      
49                        always_ff @(posedge clk_i or negedge rst_ni) begin
50         1/1              if (!rst_ni) begin
           Tests:       T26 T27 T28 
51         1/1                filter_q <= 1'b0;
           Tests:       T26 T27 T28 
52                          end else begin
53         1/1                filter_q <= filter_synced;
           Tests:       T26 T27 T28 
54                          end
55                        end
56                      
57                        always_ff @(posedge clk_i or negedge rst_ni) begin
58         1/1              if (!rst_ni) begin
           Tests:       T26 T27 T28 
59         1/1                stored_value_q <= 1'b0;
           Tests:       T26 T27 T28 
60         1/1              end else if (update_stored_value) begin
           Tests:       T26 T27 T28 
61         1/1                stored_value_q <= filter_synced;
           Tests:       T26 T27 T28 
62                          end
                        MISSING_ELSE
63                        end
64                      
65                        always_ff @(posedge clk_i or negedge rst_ni) begin
66         1/1              if (!rst_ni) begin
           Tests:       T26 T27 T28 
67         1/1                diff_ctr_q <= '0;
           Tests:       T26 T27 T28 
68                          end else begin
69         1/1                diff_ctr_q <= diff_ctr_d;
           Tests:       T26 T27 T28 
70                          end
71                        end
72                      
73                        // always look for differences, even if not filter enabled
74         1/1            assign update_stored_value = (diff_ctr_d == thresh_i);
           Tests:       T26 T27 T28 
75         1/1            assign diff_ctr_d = (filter_synced != filter_q) ? '0       :           // restart
           Tests:       T26 T27 T28 
76                                            (diff_ctr_q >= thresh_i)    ? thresh_i :           // saturate
77                                                                          (diff_ctr_q + 1'b1); // count up
78                      
79         1/1            assign filter_o = enable_i ? stored_value_q : filter_synced;
           Tests:       T26 T27 T28 

---

Cond Coverage for Instance : tb.dut.gen_filter[20].u_filter

	Total	Covered	Percent
Conditions	10	10	100.00
Logical	10	10	100.00
Non-Logical	0	0
Event	0	0

 LINE       74
 EXPRESSION (diff_ctr_d == thresh_i)
            ------------1-----------

-1-	Status	Tests
0	Covered	T26,T27,T28
1	Covered	T26,T27,T28

 LINE       75
 EXPRESSION ((filter_synced != filter_q) ? '0 : ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1))))
             -------------1-------------

-1-	Status	Tests
0	Covered	T26,T27,T28
1	Covered	T26,T27,T28

 LINE       75
 SUB-EXPRESSION (filter_synced != filter_q)
                -------------1-------------

-1-	Status	Tests
0	Covered	T26,T27,T28
1	Covered	T26,T27,T28

 LINE       75
 SUB-EXPRESSION ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1)))
                 ------------1-----------

-1-	Status	Tests
0	Covered	T26,T27,T28
1	Covered	T26,T27,T28

 LINE       79
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---

-1-	Status	Tests
0	Covered	T26,T27,T28
1	Covered	T32,T34,T35

---

Branch Coverage for Instance : tb.dut.gen_filter[20].u_filter

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	75	3	3	100.00
TERNARY	79	2	2	100.00
IF	50	2	2	100.00
IF	58	3	3	100.00
IF	66	2	2	100.00

75           assign diff_ctr_d = (filter_synced != filter_q) ? '0       :           // restart
                                                             -1-  
                                                             ==>  
76                               (diff_ctr_q >= thresh_i)    ? thresh_i :           // saturate
                                                             -2-  
                                                             ==>  
                                                             ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T26,T27,T28
0	1	Covered	T26,T27,T28
0	0	Covered	T26,T27,T28

79           assign filter_o = enable_i ? stored_value_q : filter_synced;
                                        -1-  
                                        ==>  
                                        ==>  

Branches:

-1-	Status	Tests
1	Covered	T32,T34,T35
0	Covered	T26,T27,T28

50             if (!rst_ni) begin
               -1-  
51               filter_q <= 1'b0;
                 ==>
52             end else begin
53               filter_q <= filter_synced;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T26,T27,T28
0	Covered	T26,T27,T28

58             if (!rst_ni) begin
               -1-  
59               stored_value_q <= 1'b0;
                 ==>
60             end else if (update_stored_value) begin
                        -2-  
61               stored_value_q <= filter_synced;
                 ==>
62             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T26,T27,T28
0	1	Covered	T26,T27,T28
0	0	Covered	T26,T27,T28

66             if (!rst_ni) begin
               -1-  
67               diff_ctr_q <= '0;
                 ==>
68             end else begin
69               diff_ctr_q <= diff_ctr_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T26,T27,T28
0	Covered	T26,T27,T28

Line Coverage for Instance : tb.dut.gen_filter[21].u_filter

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
CONT_ASSIGN	46	1	1	100.00
ALWAYS	50	3	3	100.00
ALWAYS	58	4	4	100.00
ALWAYS	66	3	3	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	79	1	1	100.00

45                        end else begin : gen_sync
46         1/1              assign filter_synced = filter_i;
           Tests:       T26 T27 T28 
47                        end
48                      
49                        always_ff @(posedge clk_i or negedge rst_ni) begin
50         1/1              if (!rst_ni) begin
           Tests:       T26 T27 T28 
51         1/1                filter_q <= 1'b0;
           Tests:       T26 T27 T28 
52                          end else begin
53         1/1                filter_q <= filter_synced;
           Tests:       T26 T27 T28 
54                          end
55                        end
56                      
57                        always_ff @(posedge clk_i or negedge rst_ni) begin
58         1/1              if (!rst_ni) begin
           Tests:       T26 T27 T28 
59         1/1                stored_value_q <= 1'b0;
           Tests:       T26 T27 T28 
60         1/1              end else if (update_stored_value) begin
           Tests:       T26 T27 T28 
61         1/1                stored_value_q <= filter_synced;
           Tests:       T26 T27 T28 
62                          end
                        MISSING_ELSE
63                        end
64                      
65                        always_ff @(posedge clk_i or negedge rst_ni) begin
66         1/1              if (!rst_ni) begin
           Tests:       T26 T27 T28 
67         1/1                diff_ctr_q <= '0;
           Tests:       T26 T27 T28 
68                          end else begin
69         1/1                diff_ctr_q <= diff_ctr_d;
           Tests:       T26 T27 T28 
70                          end
71                        end
72                      
73                        // always look for differences, even if not filter enabled
74         1/1            assign update_stored_value = (diff_ctr_d == thresh_i);
           Tests:       T26 T27 T28 
75         1/1            assign diff_ctr_d = (filter_synced != filter_q) ? '0       :           // restart
           Tests:       T26 T27 T28 
76                                            (diff_ctr_q >= thresh_i)    ? thresh_i :           // saturate
77                                                                          (diff_ctr_q + 1'b1); // count up
78                      
79         1/1            assign filter_o = enable_i ? stored_value_q : filter_synced;
           Tests:       T26 T27 T28 

---

Cond Coverage for Instance : tb.dut.gen_filter[21].u_filter

	Total	Covered	Percent
Conditions	10	10	100.00
Logical	10	10	100.00
Non-Logical	0	0
Event	0	0

 LINE       74
 EXPRESSION (diff_ctr_d == thresh_i)
            ------------1-----------

-1-	Status	Tests
0	Covered	T26,T27,T28
1	Covered	T26,T27,T28

 LINE       75
 EXPRESSION ((filter_synced != filter_q) ? '0 : ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1))))
             -------------1-------------

-1-	Status	Tests
0	Covered	T26,T27,T28
1	Covered	T26,T27,T28

 LINE       75
 SUB-EXPRESSION (filter_synced != filter_q)
                -------------1-------------

-1-	Status	Tests
0	Covered	T26,T27,T28
1	Covered	T26,T27,T28

 LINE       75
 SUB-EXPRESSION ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1)))
                 ------------1-----------

-1-	Status	Tests
0	Covered	T26,T27,T28
1	Covered	T26,T27,T28

 LINE       79
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---

-1-	Status	Tests
0	Covered	T26,T27,T28
1	Covered	T32,T34,T35

---

Branch Coverage for Instance : tb.dut.gen_filter[21].u_filter

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	75	3	3	100.00
TERNARY	79	2	2	100.00
IF	50	2	2	100.00
IF	58	3	3	100.00
IF	66	2	2	100.00

75           assign diff_ctr_d = (filter_synced != filter_q) ? '0       :           // restart
                                                             -1-  
                                                             ==>  
76                               (diff_ctr_q >= thresh_i)    ? thresh_i :           // saturate
                                                             -2-  
                                                             ==>  
                                                             ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T26,T27,T28
0	1	Covered	T26,T27,T28
0	0	Covered	T26,T27,T28

79           assign filter_o = enable_i ? stored_value_q : filter_synced;
                                        -1-  
                                        ==>  
                                        ==>  

Branches:

-1-	Status	Tests
1	Covered	T32,T34,T35
0	Covered	T26,T27,T28

50             if (!rst_ni) begin
               -1-  
51               filter_q <= 1'b0;
                 ==>
52             end else begin
53               filter_q <= filter_synced;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T26,T27,T28
0	Covered	T26,T27,T28

58             if (!rst_ni) begin
               -1-  
59               stored_value_q <= 1'b0;
                 ==>
60             end else if (update_stored_value) begin
                        -2-  
61               stored_value_q <= filter_synced;
                 ==>
62             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T26,T27,T28
0	1	Covered	T26,T27,T28
0	0	Covered	T26,T27,T28

66             if (!rst_ni) begin
               -1-  
67               diff_ctr_q <= '0;
                 ==>
68             end else begin
69               diff_ctr_q <= diff_ctr_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T26,T27,T28
0	Covered	T26,T27,T28

Line Coverage for Instance : tb.dut.gen_filter[22].u_filter

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
CONT_ASSIGN	46	1	1	100.00
ALWAYS	50	3	3	100.00
ALWAYS	58	4	4	100.00
ALWAYS	66	3	3	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	79	1	1	100.00

45                        end else begin : gen_sync
46         1/1              assign filter_synced = filter_i;
           Tests:       T26 T27 T28 
47                        end
48                      
49                        always_ff @(posedge clk_i or negedge rst_ni) begin
50         1/1              if (!rst_ni) begin
           Tests:       T26 T27 T28 
51         1/1                filter_q <= 1'b0;
           Tests:       T26 T27 T28 
52                          end else begin
53         1/1                filter_q <= filter_synced;
           Tests:       T26 T27 T28 
54                          end
55                        end
56                      
57                        always_ff @(posedge clk_i or negedge rst_ni) begin
58         1/1              if (!rst_ni) begin
           Tests:       T26 T27 T28 
59         1/1                stored_value_q <= 1'b0;
           Tests:       T26 T27 T28 
60         1/1              end else if (update_stored_value) begin
           Tests:       T26 T27 T28 
61         1/1                stored_value_q <= filter_synced;
           Tests:       T26 T27 T28 
62                          end
                        MISSING_ELSE
63                        end
64                      
65                        always_ff @(posedge clk_i or negedge rst_ni) begin
66         1/1              if (!rst_ni) begin
           Tests:       T26 T27 T28 
67         1/1                diff_ctr_q <= '0;
           Tests:       T26 T27 T28 
68                          end else begin
69         1/1                diff_ctr_q <= diff_ctr_d;
           Tests:       T26 T27 T28 
70                          end
71                        end
72                      
73                        // always look for differences, even if not filter enabled
74         1/1            assign update_stored_value = (diff_ctr_d == thresh_i);
           Tests:       T26 T27 T28 
75         1/1            assign diff_ctr_d = (filter_synced != filter_q) ? '0       :           // restart
           Tests:       T26 T27 T28 
76                                            (diff_ctr_q >= thresh_i)    ? thresh_i :           // saturate
77                                                                          (diff_ctr_q + 1'b1); // count up
78                      
79         1/1            assign filter_o = enable_i ? stored_value_q : filter_synced;
           Tests:       T26 T27 T28 

---

Cond Coverage for Instance : tb.dut.gen_filter[22].u_filter

	Total	Covered	Percent
Conditions	10	10	100.00
Logical	10	10	100.00
Non-Logical	0	0
Event	0	0

 LINE       74
 EXPRESSION (diff_ctr_d == thresh_i)
            ------------1-----------

-1-	Status	Tests
0	Covered	T26,T27,T28
1	Covered	T26,T27,T28

 LINE       75
 EXPRESSION ((filter_synced != filter_q) ? '0 : ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1))))
             -------------1-------------

-1-	Status	Tests
0	Covered	T26,T27,T28
1	Covered	T26,T27,T28

 LINE       75
 SUB-EXPRESSION (filter_synced != filter_q)
                -------------1-------------

-1-	Status	Tests
0	Covered	T26,T27,T28
1	Covered	T26,T27,T28

 LINE       75
 SUB-EXPRESSION ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1)))
                 ------------1-----------

-1-	Status	Tests
0	Covered	T26,T27,T28
1	Covered	T26,T27,T28

 LINE       79
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---

-1-	Status	Tests
0	Covered	T26,T27,T28
1	Covered	T32,T34,T35

---

Branch Coverage for Instance : tb.dut.gen_filter[22].u_filter

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	75	3	3	100.00
TERNARY	79	2	2	100.00
IF	50	2	2	100.00
IF	58	3	3	100.00
IF	66	2	2	100.00

75           assign diff_ctr_d = (filter_synced != filter_q) ? '0       :           // restart
                                                             -1-  
                                                             ==>  
76                               (diff_ctr_q >= thresh_i)    ? thresh_i :           // saturate
                                                             -2-  
                                                             ==>  
                                                             ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T26,T27,T28
0	1	Covered	T26,T27,T28
0	0	Covered	T26,T27,T28

79           assign filter_o = enable_i ? stored_value_q : filter_synced;
                                        -1-  
                                        ==>  
                                        ==>  

Branches:

-1-	Status	Tests
1	Covered	T32,T34,T35
0	Covered	T26,T27,T28

50             if (!rst_ni) begin
               -1-  
51               filter_q <= 1'b0;
                 ==>
52             end else begin
53               filter_q <= filter_synced;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T26,T27,T28
0	Covered	T26,T27,T28

58             if (!rst_ni) begin
               -1-  
59               stored_value_q <= 1'b0;
                 ==>
60             end else if (update_stored_value) begin
                        -2-  
61               stored_value_q <= filter_synced;
                 ==>
62             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T26,T27,T28
0	1	Covered	T26,T27,T28
0	0	Covered	T26,T27,T28

66             if (!rst_ni) begin
               -1-  
67               diff_ctr_q <= '0;
                 ==>
68             end else begin
69               diff_ctr_q <= diff_ctr_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T26,T27,T28
0	Covered	T26,T27,T28

Line Coverage for Instance : tb.dut.gen_filter[23].u_filter

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
CONT_ASSIGN	46	1	1	100.00
ALWAYS	50	3	3	100.00
ALWAYS	58	4	4	100.00
ALWAYS	66	3	3	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	79	1	1	100.00

45                        end else begin : gen_sync
46         1/1              assign filter_synced = filter_i;
           Tests:       T26 T27 T28 
47                        end
48                      
49                        always_ff @(posedge clk_i or negedge rst_ni) begin
50         1/1              if (!rst_ni) begin
           Tests:       T26 T27 T28 
51         1/1                filter_q <= 1'b0;
           Tests:       T26 T27 T28 
52                          end else begin
53         1/1                filter_q <= filter_synced;
           Tests:       T26 T27 T28 
54                          end
55                        end
56                      
57                        always_ff @(posedge clk_i or negedge rst_ni) begin
58         1/1              if (!rst_ni) begin
           Tests:       T26 T27 T28 
59         1/1                stored_value_q <= 1'b0;
           Tests:       T26 T27 T28 
60         1/1              end else if (update_stored_value) begin
           Tests:       T26 T27 T28 
61         1/1                stored_value_q <= filter_synced;
           Tests:       T26 T27 T28 
62                          end
                        MISSING_ELSE
63                        end
64                      
65                        always_ff @(posedge clk_i or negedge rst_ni) begin
66         1/1              if (!rst_ni) begin
           Tests:       T26 T27 T28 
67         1/1                diff_ctr_q <= '0;
           Tests:       T26 T27 T28 
68                          end else begin
69         1/1                diff_ctr_q <= diff_ctr_d;
           Tests:       T26 T27 T28 
70                          end
71                        end
72                      
73                        // always look for differences, even if not filter enabled
74         1/1            assign update_stored_value = (diff_ctr_d == thresh_i);
           Tests:       T26 T27 T28 
75         1/1            assign diff_ctr_d = (filter_synced != filter_q) ? '0       :           // restart
           Tests:       T26 T27 T28 
76                                            (diff_ctr_q >= thresh_i)    ? thresh_i :           // saturate
77                                                                          (diff_ctr_q + 1'b1); // count up
78                      
79         1/1            assign filter_o = enable_i ? stored_value_q : filter_synced;
           Tests:       T26 T27 T28 

---

Cond Coverage for Instance : tb.dut.gen_filter[23].u_filter

	Total	Covered	Percent
Conditions	10	10	100.00
Logical	10	10	100.00
Non-Logical	0	0
Event	0	0

 LINE       74
 EXPRESSION (diff_ctr_d == thresh_i)
            ------------1-----------

-1-	Status	Tests
0	Covered	T26,T27,T28
1	Covered	T26,T27,T28

 LINE       75
 EXPRESSION ((filter_synced != filter_q) ? '0 : ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1))))
             -------------1-------------

-1-	Status	Tests
0	Covered	T26,T27,T28
1	Covered	T26,T27,T28

 LINE       75
 SUB-EXPRESSION (filter_synced != filter_q)
                -------------1-------------

-1-	Status	Tests
0	Covered	T26,T27,T28
1	Covered	T26,T27,T28

 LINE       75
 SUB-EXPRESSION ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1)))
                 ------------1-----------

-1-	Status	Tests
0	Covered	T26,T27,T28
1	Covered	T26,T27,T28

 LINE       79
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---

-1-	Status	Tests
0	Covered	T26,T27,T28
1	Covered	T32,T34,T35

---

Branch Coverage for Instance : tb.dut.gen_filter[23].u_filter

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	75	3	3	100.00
TERNARY	79	2	2	100.00
IF	50	2	2	100.00
IF	58	3	3	100.00
IF	66	2	2	100.00

75           assign diff_ctr_d = (filter_synced != filter_q) ? '0       :           // restart
                                                             -1-  
                                                             ==>  
76                               (diff_ctr_q >= thresh_i)    ? thresh_i :           // saturate
                                                             -2-  
                                                             ==>  
                                                             ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T26,T27,T28
0	1	Covered	T26,T27,T28
0	0	Covered	T26,T27,T28

79           assign filter_o = enable_i ? stored_value_q : filter_synced;
                                        -1-  
                                        ==>  
                                        ==>  

Branches:

-1-	Status	Tests
1	Covered	T32,T34,T35
0	Covered	T26,T27,T28

50             if (!rst_ni) begin
               -1-  
51               filter_q <= 1'b0;
                 ==>
52             end else begin
53               filter_q <= filter_synced;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T26,T27,T28
0	Covered	T26,T27,T28

58             if (!rst_ni) begin
               -1-  
59               stored_value_q <= 1'b0;
                 ==>
60             end else if (update_stored_value) begin
                        -2-  
61               stored_value_q <= filter_synced;
                 ==>
62             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T26,T27,T28
0	1	Covered	T26,T27,T28
0	0	Covered	T26,T27,T28

66             if (!rst_ni) begin
               -1-  
67               diff_ctr_q <= '0;
                 ==>
68             end else begin
69               diff_ctr_q <= diff_ctr_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T26,T27,T28
0	Covered	T26,T27,T28

Line Coverage for Instance : tb.dut.gen_filter[24].u_filter

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
CONT_ASSIGN	46	1	1	100.00
ALWAYS	50	3	3	100.00
ALWAYS	58	4	4	100.00
ALWAYS	66	3	3	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	79	1	1	100.00

45                        end else begin : gen_sync
46         1/1              assign filter_synced = filter_i;
           Tests:       T26 T27 T28 
47                        end
48                      
49                        always_ff @(posedge clk_i or negedge rst_ni) begin
50         1/1              if (!rst_ni) begin
           Tests:       T26 T27 T28 
51         1/1                filter_q <= 1'b0;
           Tests:       T26 T27 T28 
52                          end else begin
53         1/1                filter_q <= filter_synced;
           Tests:       T26 T27 T28 
54                          end
55                        end
56                      
57                        always_ff @(posedge clk_i or negedge rst_ni) begin
58         1/1              if (!rst_ni) begin
           Tests:       T26 T27 T28 
59         1/1                stored_value_q <= 1'b0;
           Tests:       T26 T27 T28 
60         1/1              end else if (update_stored_value) begin
           Tests:       T26 T27 T28 
61         1/1                stored_value_q <= filter_synced;
           Tests:       T26 T27 T28 
62                          end
                        MISSING_ELSE
63                        end
64                      
65                        always_ff @(posedge clk_i or negedge rst_ni) begin
66         1/1              if (!rst_ni) begin
           Tests:       T26 T27 T28 
67         1/1                diff_ctr_q <= '0;
           Tests:       T26 T27 T28 
68                          end else begin
69         1/1                diff_ctr_q <= diff_ctr_d;
           Tests:       T26 T27 T28 
70                          end
71                        end
72                      
73                        // always look for differences, even if not filter enabled
74         1/1            assign update_stored_value = (diff_ctr_d == thresh_i);
           Tests:       T26 T27 T28 
75         1/1            assign diff_ctr_d = (filter_synced != filter_q) ? '0       :           // restart
           Tests:       T26 T27 T28 
76                                            (diff_ctr_q >= thresh_i)    ? thresh_i :           // saturate
77                                                                          (diff_ctr_q + 1'b1); // count up
78                      
79         1/1            assign filter_o = enable_i ? stored_value_q : filter_synced;
           Tests:       T26 T27 T28 

---

Cond Coverage for Instance : tb.dut.gen_filter[24].u_filter

	Total	Covered	Percent
Conditions	10	10	100.00
Logical	10	10	100.00
Non-Logical	0	0
Event	0	0

 LINE       74
 EXPRESSION (diff_ctr_d == thresh_i)
            ------------1-----------

-1-	Status	Tests
0	Covered	T26,T27,T28
1	Covered	T26,T27,T28

 LINE       75
 EXPRESSION ((filter_synced != filter_q) ? '0 : ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1))))
             -------------1-------------

-1-	Status	Tests
0	Covered	T26,T27,T28
1	Covered	T26,T27,T28

 LINE       75
 SUB-EXPRESSION (filter_synced != filter_q)
                -------------1-------------

-1-	Status	Tests
0	Covered	T26,T27,T28
1	Covered	T26,T27,T28

 LINE       75
 SUB-EXPRESSION ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1)))
                 ------------1-----------

-1-	Status	Tests
0	Covered	T26,T27,T28
1	Covered	T26,T27,T28

 LINE       79
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---

-1-	Status	Tests
0	Covered	T26,T27,T28
1	Covered	T32,T34,T35

---

Branch Coverage for Instance : tb.dut.gen_filter[24].u_filter

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	75	3	3	100.00
TERNARY	79	2	2	100.00
IF	50	2	2	100.00
IF	58	3	3	100.00
IF	66	2	2	100.00

75           assign diff_ctr_d = (filter_synced != filter_q) ? '0       :           // restart
                                                             -1-  
                                                             ==>  
76                               (diff_ctr_q >= thresh_i)    ? thresh_i :           // saturate
                                                             -2-  
                                                             ==>  
                                                             ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T26,T27,T28
0	1	Covered	T26,T27,T28
0	0	Covered	T26,T27,T28

79           assign filter_o = enable_i ? stored_value_q : filter_synced;
                                        -1-  
                                        ==>  
                                        ==>  

Branches:

-1-	Status	Tests
1	Covered	T32,T34,T35
0	Covered	T26,T27,T28

50             if (!rst_ni) begin
               -1-  
51               filter_q <= 1'b0;
                 ==>
52             end else begin
53               filter_q <= filter_synced;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T26,T27,T28
0	Covered	T26,T27,T28

58             if (!rst_ni) begin
               -1-  
59               stored_value_q <= 1'b0;
                 ==>
60             end else if (update_stored_value) begin
                        -2-  
61               stored_value_q <= filter_synced;
                 ==>
62             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T26,T27,T28
0	1	Covered	T26,T27,T28
0	0	Covered	T26,T27,T28

66             if (!rst_ni) begin
               -1-  
67               diff_ctr_q <= '0;
                 ==>
68             end else begin
69               diff_ctr_q <= diff_ctr_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T26,T27,T28
0	Covered	T26,T27,T28

Line Coverage for Instance : tb.dut.gen_filter[25].u_filter

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
CONT_ASSIGN	46	1	1	100.00
ALWAYS	50	3	3	100.00
ALWAYS	58	4	4	100.00
ALWAYS	66	3	3	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	79	1	1	100.00

45                        end else begin : gen_sync
46         1/1              assign filter_synced = filter_i;
           Tests:       T26 T27 T28 
47                        end
48                      
49                        always_ff @(posedge clk_i or negedge rst_ni) begin
50         1/1              if (!rst_ni) begin
           Tests:       T26 T27 T28 
51         1/1                filter_q <= 1'b0;
           Tests:       T26 T27 T28 
52                          end else begin
53         1/1                filter_q <= filter_synced;
           Tests:       T26 T27 T28 
54                          end
55                        end
56                      
57                        always_ff @(posedge clk_i or negedge rst_ni) begin
58         1/1              if (!rst_ni) begin
           Tests:       T26 T27 T28 
59         1/1                stored_value_q <= 1'b0;
           Tests:       T26 T27 T28 
60         1/1              end else if (update_stored_value) begin
           Tests:       T26 T27 T28 
61         1/1                stored_value_q <= filter_synced;
           Tests:       T26 T27 T28 
62                          end
                        MISSING_ELSE
63                        end
64                      
65                        always_ff @(posedge clk_i or negedge rst_ni) begin
66         1/1              if (!rst_ni) begin
           Tests:       T26 T27 T28 
67         1/1                diff_ctr_q <= '0;
           Tests:       T26 T27 T28 
68                          end else begin
69         1/1                diff_ctr_q <= diff_ctr_d;
           Tests:       T26 T27 T28 
70                          end
71                        end
72                      
73                        // always look for differences, even if not filter enabled
74         1/1            assign update_stored_value = (diff_ctr_d == thresh_i);
           Tests:       T26 T27 T28 
75         1/1            assign diff_ctr_d = (filter_synced != filter_q) ? '0       :           // restart
           Tests:       T26 T27 T28 
76                                            (diff_ctr_q >= thresh_i)    ? thresh_i :           // saturate
77                                                                          (diff_ctr_q + 1'b1); // count up
78                      
79         1/1            assign filter_o = enable_i ? stored_value_q : filter_synced;
           Tests:       T26 T27 T28 

---

Cond Coverage for Instance : tb.dut.gen_filter[25].u_filter

	Total	Covered	Percent
Conditions	10	10	100.00
Logical	10	10	100.00
Non-Logical	0	0
Event	0	0

 LINE       74
 EXPRESSION (diff_ctr_d == thresh_i)
            ------------1-----------

-1-	Status	Tests
0	Covered	T26,T27,T28
1	Covered	T26,T27,T28

 LINE       75
 EXPRESSION ((filter_synced != filter_q) ? '0 : ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1))))
             -------------1-------------

-1-	Status	Tests
0	Covered	T26,T27,T28
1	Covered	T26,T27,T28

 LINE       75
 SUB-EXPRESSION (filter_synced != filter_q)
                -------------1-------------

-1-	Status	Tests
0	Covered	T26,T27,T28
1	Covered	T26,T27,T28

 LINE       75
 SUB-EXPRESSION ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1)))
                 ------------1-----------

-1-	Status	Tests
0	Covered	T26,T27,T28
1	Covered	T26,T27,T28

 LINE       79
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---

-1-	Status	Tests
0	Covered	T26,T27,T28
1	Covered	T32,T34,T35

---

Branch Coverage for Instance : tb.dut.gen_filter[25].u_filter

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	75	3	3	100.00
TERNARY	79	2	2	100.00
IF	50	2	2	100.00
IF	58	3	3	100.00
IF	66	2	2	100.00

75           assign diff_ctr_d = (filter_synced != filter_q) ? '0       :           // restart
                                                             -1-  
                                                             ==>  
76                               (diff_ctr_q >= thresh_i)    ? thresh_i :           // saturate
                                                             -2-  
                                                             ==>  
                                                             ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T26,T27,T28
0	1	Covered	T26,T27,T28
0	0	Covered	T26,T27,T28

79           assign filter_o = enable_i ? stored_value_q : filter_synced;
                                        -1-  
                                        ==>  
                                        ==>  

Branches:

-1-	Status	Tests
1	Covered	T32,T34,T35
0	Covered	T26,T27,T28

50             if (!rst_ni) begin
               -1-  
51               filter_q <= 1'b0;
                 ==>
52             end else begin
53               filter_q <= filter_synced;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T26,T27,T28
0	Covered	T26,T27,T28

58             if (!rst_ni) begin
               -1-  
59               stored_value_q <= 1'b0;
                 ==>
60             end else if (update_stored_value) begin
                        -2-  
61               stored_value_q <= filter_synced;
                 ==>
62             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T26,T27,T28
0	1	Covered	T26,T27,T28
0	0	Covered	T26,T27,T28

66             if (!rst_ni) begin
               -1-  
67               diff_ctr_q <= '0;
                 ==>
68             end else begin
69               diff_ctr_q <= diff_ctr_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T26,T27,T28
0	Covered	T26,T27,T28

Line Coverage for Instance : tb.dut.gen_filter[26].u_filter

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
CONT_ASSIGN	46	1	1	100.00
ALWAYS	50	3	3	100.00
ALWAYS	58	4	4	100.00
ALWAYS	66	3	3	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	79	1	1	100.00

45                        end else begin : gen_sync
46         1/1              assign filter_synced = filter_i;
           Tests:       T26 T27 T28 
47                        end
48                      
49                        always_ff @(posedge clk_i or negedge rst_ni) begin
50         1/1              if (!rst_ni) begin
           Tests:       T26 T27 T28 
51         1/1                filter_q <= 1'b0;
           Tests:       T26 T27 T28 
52                          end else begin
53         1/1                filter_q <= filter_synced;
           Tests:       T26 T27 T28 
54                          end
55                        end
56                      
57                        always_ff @(posedge clk_i or negedge rst_ni) begin
58         1/1              if (!rst_ni) begin
           Tests:       T26 T27 T28 
59         1/1                stored_value_q <= 1'b0;
           Tests:       T26 T27 T28 
60         1/1              end else if (update_stored_value) begin
           Tests:       T26 T27 T28 
61         1/1                stored_value_q <= filter_synced;
           Tests:       T26 T27 T28 
62                          end
                        MISSING_ELSE
63                        end
64                      
65                        always_ff @(posedge clk_i or negedge rst_ni) begin
66         1/1              if (!rst_ni) begin
           Tests:       T26 T27 T28 
67         1/1                diff_ctr_q <= '0;
           Tests:       T26 T27 T28 
68                          end else begin
69         1/1                diff_ctr_q <= diff_ctr_d;
           Tests:       T26 T27 T28 
70                          end
71                        end
72                      
73                        // always look for differences, even if not filter enabled
74         1/1            assign update_stored_value = (diff_ctr_d == thresh_i);
           Tests:       T26 T27 T28 
75         1/1            assign diff_ctr_d = (filter_synced != filter_q) ? '0       :           // restart
           Tests:       T26 T27 T28 
76                                            (diff_ctr_q >= thresh_i)    ? thresh_i :           // saturate
77                                                                          (diff_ctr_q + 1'b1); // count up
78                      
79         1/1            assign filter_o = enable_i ? stored_value_q : filter_synced;
           Tests:       T26 T27 T28 

---

Cond Coverage for Instance : tb.dut.gen_filter[26].u_filter

	Total	Covered	Percent
Conditions	10	10	100.00
Logical	10	10	100.00
Non-Logical	0	0
Event	0	0

 LINE       74
 EXPRESSION (diff_ctr_d == thresh_i)
            ------------1-----------

-1-	Status	Tests
0	Covered	T26,T27,T28
1	Covered	T26,T27,T28

 LINE       75
 EXPRESSION ((filter_synced != filter_q) ? '0 : ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1))))
             -------------1-------------

-1-	Status	Tests
0	Covered	T26,T27,T28
1	Covered	T26,T27,T28

 LINE       75
 SUB-EXPRESSION (filter_synced != filter_q)
                -------------1-------------

-1-	Status	Tests
0	Covered	T26,T27,T28
1	Covered	T26,T27,T28

 LINE       75
 SUB-EXPRESSION ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1)))
                 ------------1-----------

-1-	Status	Tests
0	Covered	T26,T27,T28
1	Covered	T26,T27,T28

 LINE       79
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---

-1-	Status	Tests
0	Covered	T26,T27,T28
1	Covered	T32,T34,T35

---

Branch Coverage for Instance : tb.dut.gen_filter[26].u_filter

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	75	3	3	100.00
TERNARY	79	2	2	100.00
IF	50	2	2	100.00
IF	58	3	3	100.00
IF	66	2	2	100.00

75           assign diff_ctr_d = (filter_synced != filter_q) ? '0       :           // restart
                                                             -1-  
                                                             ==>  
76                               (diff_ctr_q >= thresh_i)    ? thresh_i :           // saturate
                                                             -2-  
                                                             ==>  
                                                             ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T26,T27,T28
0	1	Covered	T26,T27,T28
0	0	Covered	T26,T27,T28

79           assign filter_o = enable_i ? stored_value_q : filter_synced;
                                        -1-  
                                        ==>  
                                        ==>  

Branches:

-1-	Status	Tests
1	Covered	T32,T34,T35
0	Covered	T26,T27,T28

50             if (!rst_ni) begin
               -1-  
51               filter_q <= 1'b0;
                 ==>
52             end else begin
53               filter_q <= filter_synced;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T26,T27,T28
0	Covered	T26,T27,T28

58             if (!rst_ni) begin
               -1-  
59               stored_value_q <= 1'b0;
                 ==>
60             end else if (update_stored_value) begin
                        -2-  
61               stored_value_q <= filter_synced;
                 ==>
62             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T26,T27,T28
0	1	Covered	T26,T27,T28
0	0	Covered	T26,T27,T28

66             if (!rst_ni) begin
               -1-  
67               diff_ctr_q <= '0;
                 ==>
68             end else begin
69               diff_ctr_q <= diff_ctr_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T26,T27,T28
0	Covered	T26,T27,T28

Line Coverage for Instance : tb.dut.gen_filter[27].u_filter

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
CONT_ASSIGN	46	1	1	100.00
ALWAYS	50	3	3	100.00
ALWAYS	58	4	4	100.00
ALWAYS	66	3	3	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	79	1	1	100.00

45                        end else begin : gen_sync
46         1/1              assign filter_synced = filter_i;
           Tests:       T26 T27 T28 
47                        end
48                      
49                        always_ff @(posedge clk_i or negedge rst_ni) begin
50         1/1              if (!rst_ni) begin
           Tests:       T26 T27 T28 
51         1/1                filter_q <= 1'b0;
           Tests:       T26 T27 T28 
52                          end else begin
53         1/1                filter_q <= filter_synced;
           Tests:       T26 T27 T28 
54                          end
55                        end
56                      
57                        always_ff @(posedge clk_i or negedge rst_ni) begin
58         1/1              if (!rst_ni) begin
           Tests:       T26 T27 T28 
59         1/1                stored_value_q <= 1'b0;
           Tests:       T26 T27 T28 
60         1/1              end else if (update_stored_value) begin
           Tests:       T26 T27 T28 
61         1/1                stored_value_q <= filter_synced;
           Tests:       T26 T27 T28 
62                          end
                        MISSING_ELSE
63                        end
64                      
65                        always_ff @(posedge clk_i or negedge rst_ni) begin
66         1/1              if (!rst_ni) begin
           Tests:       T26 T27 T28 
67         1/1                diff_ctr_q <= '0;
           Tests:       T26 T27 T28 
68                          end else begin
69         1/1                diff_ctr_q <= diff_ctr_d;
           Tests:       T26 T27 T28 
70                          end
71                        end
72                      
73                        // always look for differences, even if not filter enabled
74         1/1            assign update_stored_value = (diff_ctr_d == thresh_i);
           Tests:       T26 T27 T28 
75         1/1            assign diff_ctr_d = (filter_synced != filter_q) ? '0       :           // restart
           Tests:       T26 T27 T28 
76                                            (diff_ctr_q >= thresh_i)    ? thresh_i :           // saturate
77                                                                          (diff_ctr_q + 1'b1); // count up
78                      
79         1/1            assign filter_o = enable_i ? stored_value_q : filter_synced;
           Tests:       T26 T27 T28 

---

Cond Coverage for Instance : tb.dut.gen_filter[27].u_filter

	Total	Covered	Percent
Conditions	10	10	100.00
Logical	10	10	100.00
Non-Logical	0	0
Event	0	0

 LINE       74
 EXPRESSION (diff_ctr_d == thresh_i)
            ------------1-----------

-1-	Status	Tests
0	Covered	T26,T27,T28
1	Covered	T26,T27,T28

 LINE       75
 EXPRESSION ((filter_synced != filter_q) ? '0 : ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1))))
             -------------1-------------

-1-	Status	Tests
0	Covered	T26,T27,T28
1	Covered	T26,T27,T28

 LINE       75
 SUB-EXPRESSION (filter_synced != filter_q)
                -------------1-------------

-1-	Status	Tests
0	Covered	T26,T27,T28
1	Covered	T26,T27,T28

 LINE       75
 SUB-EXPRESSION ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1)))
                 ------------1-----------

-1-	Status	Tests
0	Covered	T26,T27,T28
1	Covered	T26,T27,T28

 LINE       79
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---

-1-	Status	Tests
0	Covered	T26,T27,T28
1	Covered	T32,T34,T35

---

Branch Coverage for Instance : tb.dut.gen_filter[27].u_filter

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	75	3	3	100.00
TERNARY	79	2	2	100.00
IF	50	2	2	100.00
IF	58	3	3	100.00
IF	66	2	2	100.00

75           assign diff_ctr_d = (filter_synced != filter_q) ? '0       :           // restart
                                                             -1-  
                                                             ==>  
76                               (diff_ctr_q >= thresh_i)    ? thresh_i :           // saturate
                                                             -2-  
                                                             ==>  
                                                             ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T26,T27,T28
0	1	Covered	T26,T27,T28
0	0	Covered	T26,T27,T28

79           assign filter_o = enable_i ? stored_value_q : filter_synced;
                                        -1-  
                                        ==>  
                                        ==>  

Branches:

-1-	Status	Tests
1	Covered	T32,T34,T35
0	Covered	T26,T27,T28

50             if (!rst_ni) begin
               -1-  
51               filter_q <= 1'b0;
                 ==>
52             end else begin
53               filter_q <= filter_synced;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T26,T27,T28
0	Covered	T26,T27,T28

58             if (!rst_ni) begin
               -1-  
59               stored_value_q <= 1'b0;
                 ==>
60             end else if (update_stored_value) begin
                        -2-  
61               stored_value_q <= filter_synced;
                 ==>
62             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T26,T27,T28
0	1	Covered	T26,T27,T28
0	0	Covered	T26,T27,T28

66             if (!rst_ni) begin
               -1-  
67               diff_ctr_q <= '0;
                 ==>
68             end else begin
69               diff_ctr_q <= diff_ctr_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T26,T27,T28
0	Covered	T26,T27,T28

Line Coverage for Instance : tb.dut.gen_filter[28].u_filter

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
CONT_ASSIGN	46	1	1	100.00
ALWAYS	50	3	3	100.00
ALWAYS	58	4	4	100.00
ALWAYS	66	3	3	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	79	1	1	100.00

45                        end else begin : gen_sync
46         1/1              assign filter_synced = filter_i;
           Tests:       T26 T27 T28 
47                        end
48                      
49                        always_ff @(posedge clk_i or negedge rst_ni) begin
50         1/1              if (!rst_ni) begin
           Tests:       T26 T27 T28 
51         1/1                filter_q <= 1'b0;
           Tests:       T26 T27 T28 
52                          end else begin
53         1/1                filter_q <= filter_synced;
           Tests:       T26 T27 T28 
54                          end
55                        end
56                      
57                        always_ff @(posedge clk_i or negedge rst_ni) begin
58         1/1              if (!rst_ni) begin
           Tests:       T26 T27 T28 
59         1/1                stored_value_q <= 1'b0;
           Tests:       T26 T27 T28 
60         1/1              end else if (update_stored_value) begin
           Tests:       T26 T27 T28 
61         1/1                stored_value_q <= filter_synced;
           Tests:       T26 T27 T28 
62                          end
                        MISSING_ELSE
63                        end
64                      
65                        always_ff @(posedge clk_i or negedge rst_ni) begin
66         1/1              if (!rst_ni) begin
           Tests:       T26 T27 T28 
67         1/1                diff_ctr_q <= '0;
           Tests:       T26 T27 T28 
68                          end else begin
69         1/1                diff_ctr_q <= diff_ctr_d;
           Tests:       T26 T27 T28 
70                          end
71                        end
72                      
73                        // always look for differences, even if not filter enabled
74         1/1            assign update_stored_value = (diff_ctr_d == thresh_i);
           Tests:       T26 T27 T28 
75         1/1            assign diff_ctr_d = (filter_synced != filter_q) ? '0       :           // restart
           Tests:       T26 T27 T28 
76                                            (diff_ctr_q >= thresh_i)    ? thresh_i :           // saturate
77                                                                          (diff_ctr_q + 1'b1); // count up
78                      
79         1/1            assign filter_o = enable_i ? stored_value_q : filter_synced;
           Tests:       T26 T27 T28 

---

Cond Coverage for Instance : tb.dut.gen_filter[28].u_filter

	Total	Covered	Percent
Conditions	10	10	100.00
Logical	10	10	100.00
Non-Logical	0	0
Event	0	0

 LINE       74
 EXPRESSION (diff_ctr_d == thresh_i)
            ------------1-----------

-1-	Status	Tests
0	Covered	T26,T27,T28
1	Covered	T26,T27,T28

 LINE       75
 EXPRESSION ((filter_synced != filter_q) ? '0 : ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1))))
             -------------1-------------

-1-	Status	Tests
0	Covered	T26,T27,T28
1	Covered	T26,T27,T28

 LINE       75
 SUB-EXPRESSION (filter_synced != filter_q)
                -------------1-------------

-1-	Status	Tests
0	Covered	T26,T27,T28
1	Covered	T26,T27,T28

 LINE       75
 SUB-EXPRESSION ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1)))
                 ------------1-----------

-1-	Status	Tests
0	Covered	T26,T27,T28
1	Covered	T26,T27,T28

 LINE       79
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---

-1-	Status	Tests
0	Covered	T26,T27,T28
1	Covered	T32,T34,T35

---

Branch Coverage for Instance : tb.dut.gen_filter[28].u_filter

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	75	3	3	100.00
TERNARY	79	2	2	100.00
IF	50	2	2	100.00
IF	58	3	3	100.00
IF	66	2	2	100.00

75           assign diff_ctr_d = (filter_synced != filter_q) ? '0       :           // restart
                                                             -1-  
                                                             ==>  
76                               (diff_ctr_q >= thresh_i)    ? thresh_i :           // saturate
                                                             -2-  
                                                             ==>  
                                                             ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T26,T27,T28
0	1	Covered	T26,T27,T28
0	0	Covered	T26,T27,T28

79           assign filter_o = enable_i ? stored_value_q : filter_synced;
                                        -1-  
                                        ==>  
                                        ==>  

Branches:

-1-	Status	Tests
1	Covered	T32,T34,T35
0	Covered	T26,T27,T28

50             if (!rst_ni) begin
               -1-  
51               filter_q <= 1'b0;
                 ==>
52             end else begin
53               filter_q <= filter_synced;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T26,T27,T28
0	Covered	T26,T27,T28

58             if (!rst_ni) begin
               -1-  
59               stored_value_q <= 1'b0;
                 ==>
60             end else if (update_stored_value) begin
                        -2-  
61               stored_value_q <= filter_synced;
                 ==>
62             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T26,T27,T28
0	1	Covered	T26,T27,T28
0	0	Covered	T26,T27,T28

66             if (!rst_ni) begin
               -1-  
67               diff_ctr_q <= '0;
                 ==>
68             end else begin
69               diff_ctr_q <= diff_ctr_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T26,T27,T28
0	Covered	T26,T27,T28

Line Coverage for Instance : tb.dut.gen_filter[29].u_filter

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
CONT_ASSIGN	46	1	1	100.00
ALWAYS	50	3	3	100.00
ALWAYS	58	4	4	100.00
ALWAYS	66	3	3	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	79	1	1	100.00

45                        end else begin : gen_sync
46         1/1              assign filter_synced = filter_i;
           Tests:       T26 T27 T28 
47                        end
48                      
49                        always_ff @(posedge clk_i or negedge rst_ni) begin
50         1/1              if (!rst_ni) begin
           Tests:       T26 T27 T28 
51         1/1                filter_q <= 1'b0;
           Tests:       T26 T27 T28 
52                          end else begin
53         1/1                filter_q <= filter_synced;
           Tests:       T26 T27 T28 
54                          end
55                        end
56                      
57                        always_ff @(posedge clk_i or negedge rst_ni) begin
58         1/1              if (!rst_ni) begin
           Tests:       T26 T27 T28 
59         1/1                stored_value_q <= 1'b0;
           Tests:       T26 T27 T28 
60         1/1              end else if (update_stored_value) begin
           Tests:       T26 T27 T28 
61         1/1                stored_value_q <= filter_synced;
           Tests:       T26 T27 T28 
62                          end
                        MISSING_ELSE
63                        end
64                      
65                        always_ff @(posedge clk_i or negedge rst_ni) begin
66         1/1              if (!rst_ni) begin
           Tests:       T26 T27 T28 
67         1/1                diff_ctr_q <= '0;
           Tests:       T26 T27 T28 
68                          end else begin
69         1/1                diff_ctr_q <= diff_ctr_d;
           Tests:       T26 T27 T28 
70                          end
71                        end
72                      
73                        // always look for differences, even if not filter enabled
74         1/1            assign update_stored_value = (diff_ctr_d == thresh_i);
           Tests:       T26 T27 T28 
75         1/1            assign diff_ctr_d = (filter_synced != filter_q) ? '0       :           // restart
           Tests:       T26 T27 T28 
76                                            (diff_ctr_q >= thresh_i)    ? thresh_i :           // saturate
77                                                                          (diff_ctr_q + 1'b1); // count up
78                      
79         1/1            assign filter_o = enable_i ? stored_value_q : filter_synced;
           Tests:       T26 T27 T28 

---

Cond Coverage for Instance : tb.dut.gen_filter[29].u_filter

	Total	Covered	Percent
Conditions	10	10	100.00
Logical	10	10	100.00
Non-Logical	0	0
Event	0	0

 LINE       74
 EXPRESSION (diff_ctr_d == thresh_i)
            ------------1-----------

-1-	Status	Tests
0	Covered	T26,T27,T28
1	Covered	T26,T27,T28

 LINE       75
 EXPRESSION ((filter_synced != filter_q) ? '0 : ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1))))
             -------------1-------------

-1-	Status	Tests
0	Covered	T26,T27,T28
1	Covered	T26,T27,T28

 LINE       75
 SUB-EXPRESSION (filter_synced != filter_q)
                -------------1-------------

-1-	Status	Tests
0	Covered	T26,T27,T28
1	Covered	T26,T27,T28

 LINE       75
 SUB-EXPRESSION ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1)))
                 ------------1-----------

-1-	Status	Tests
0	Covered	T26,T27,T28
1	Covered	T26,T27,T28

 LINE       79
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---

-1-	Status	Tests
0	Covered	T26,T27,T28
1	Covered	T32,T34,T35

---

Branch Coverage for Instance : tb.dut.gen_filter[29].u_filter

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	75	3	3	100.00
TERNARY	79	2	2	100.00
IF	50	2	2	100.00
IF	58	3	3	100.00
IF	66	2	2	100.00

75           assign diff_ctr_d = (filter_synced != filter_q) ? '0       :           // restart
                                                             -1-  
                                                             ==>  
76                               (diff_ctr_q >= thresh_i)    ? thresh_i :           // saturate
                                                             -2-  
                                                             ==>  
                                                             ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T26,T27,T28
0	1	Covered	T26,T27,T28
0	0	Covered	T26,T27,T28

79           assign filter_o = enable_i ? stored_value_q : filter_synced;
                                        -1-  
                                        ==>  
                                        ==>  

Branches:

-1-	Status	Tests
1	Covered	T32,T34,T35
0	Covered	T26,T27,T28

50             if (!rst_ni) begin
               -1-  
51               filter_q <= 1'b0;
                 ==>
52             end else begin
53               filter_q <= filter_synced;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T26,T27,T28
0	Covered	T26,T27,T28

58             if (!rst_ni) begin
               -1-  
59               stored_value_q <= 1'b0;
                 ==>
60             end else if (update_stored_value) begin
                        -2-  
61               stored_value_q <= filter_synced;
                 ==>
62             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T26,T27,T28
0	1	Covered	T26,T27,T28
0	0	Covered	T26,T27,T28

66             if (!rst_ni) begin
               -1-  
67               diff_ctr_q <= '0;
                 ==>
68             end else begin
69               diff_ctr_q <= diff_ctr_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T26,T27,T28
0	Covered	T26,T27,T28

Line Coverage for Instance : tb.dut.gen_filter[30].u_filter

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
CONT_ASSIGN	46	1	1	100.00
ALWAYS	50	3	3	100.00
ALWAYS	58	4	4	100.00
ALWAYS	66	3	3	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	79	1	1	100.00

45                        end else begin : gen_sync
46         1/1              assign filter_synced = filter_i;
           Tests:       T26 T27 T28 
47                        end
48                      
49                        always_ff @(posedge clk_i or negedge rst_ni) begin
50         1/1              if (!rst_ni) begin
           Tests:       T26 T27 T28 
51         1/1                filter_q <= 1'b0;
           Tests:       T26 T27 T28 
52                          end else begin
53         1/1                filter_q <= filter_synced;
           Tests:       T26 T27 T28 
54                          end
55                        end
56                      
57                        always_ff @(posedge clk_i or negedge rst_ni) begin
58         1/1              if (!rst_ni) begin
           Tests:       T26 T27 T28 
59         1/1                stored_value_q <= 1'b0;
           Tests:       T26 T27 T28 
60         1/1              end else if (update_stored_value) begin
           Tests:       T26 T27 T28 
61         1/1                stored_value_q <= filter_synced;
           Tests:       T26 T27 T28 
62                          end
                        MISSING_ELSE
63                        end
64                      
65                        always_ff @(posedge clk_i or negedge rst_ni) begin
66         1/1              if (!rst_ni) begin
           Tests:       T26 T27 T28 
67         1/1                diff_ctr_q <= '0;
           Tests:       T26 T27 T28 
68                          end else begin
69         1/1                diff_ctr_q <= diff_ctr_d;
           Tests:       T26 T27 T28 
70                          end
71                        end
72                      
73                        // always look for differences, even if not filter enabled
74         1/1            assign update_stored_value = (diff_ctr_d == thresh_i);
           Tests:       T26 T27 T28 
75         1/1            assign diff_ctr_d = (filter_synced != filter_q) ? '0       :           // restart
           Tests:       T26 T27 T28 
76                                            (diff_ctr_q >= thresh_i)    ? thresh_i :           // saturate
77                                                                          (diff_ctr_q + 1'b1); // count up
78                      
79         1/1            assign filter_o = enable_i ? stored_value_q : filter_synced;
           Tests:       T26 T27 T28 

---

Cond Coverage for Instance : tb.dut.gen_filter[30].u_filter

	Total	Covered	Percent
Conditions	10	10	100.00
Logical	10	10	100.00
Non-Logical	0	0
Event	0	0

 LINE       74
 EXPRESSION (diff_ctr_d == thresh_i)
            ------------1-----------

-1-	Status	Tests
0	Covered	T26,T27,T28
1	Covered	T26,T27,T28

 LINE       75
 EXPRESSION ((filter_synced != filter_q) ? '0 : ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1))))
             -------------1-------------

-1-	Status	Tests
0	Covered	T26,T27,T28
1	Covered	T26,T27,T28

 LINE       75
 SUB-EXPRESSION (filter_synced != filter_q)
                -------------1-------------

-1-	Status	Tests
0	Covered	T26,T27,T28
1	Covered	T26,T27,T28

 LINE       75
 SUB-EXPRESSION ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1)))
                 ------------1-----------

-1-	Status	Tests
0	Covered	T26,T27,T28
1	Covered	T26,T27,T28

 LINE       79
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---

-1-	Status	Tests
0	Covered	T26,T27,T28
1	Covered	T32,T34,T35

---

Branch Coverage for Instance : tb.dut.gen_filter[30].u_filter

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	75	3	3	100.00
TERNARY	79	2	2	100.00
IF	50	2	2	100.00
IF	58	3	3	100.00
IF	66	2	2	100.00

75           assign diff_ctr_d = (filter_synced != filter_q) ? '0       :           // restart
                                                             -1-  
                                                             ==>  
76                               (diff_ctr_q >= thresh_i)    ? thresh_i :           // saturate
                                                             -2-  
                                                             ==>  
                                                             ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T26,T27,T28
0	1	Covered	T26,T27,T28
0	0	Covered	T26,T27,T28

79           assign filter_o = enable_i ? stored_value_q : filter_synced;
                                        -1-  
                                        ==>  
                                        ==>  

Branches:

-1-	Status	Tests
1	Covered	T32,T34,T35
0	Covered	T26,T27,T28

50             if (!rst_ni) begin
               -1-  
51               filter_q <= 1'b0;
                 ==>
52             end else begin
53               filter_q <= filter_synced;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T26,T27,T28
0	Covered	T26,T27,T28

58             if (!rst_ni) begin
               -1-  
59               stored_value_q <= 1'b0;
                 ==>
60             end else if (update_stored_value) begin
                        -2-  
61               stored_value_q <= filter_synced;
                 ==>
62             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T26,T27,T28
0	1	Covered	T26,T27,T28
0	0	Covered	T26,T27,T28

66             if (!rst_ni) begin
               -1-  
67               diff_ctr_q <= '0;
                 ==>
68             end else begin
69               diff_ctr_q <= diff_ctr_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T26,T27,T28
0	Covered	T26,T27,T28

Line Coverage for Instance : tb.dut.gen_filter[31].u_filter

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
CONT_ASSIGN	46	1	1	100.00
ALWAYS	50	3	3	100.00
ALWAYS	58	4	4	100.00
ALWAYS	66	3	3	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	79	1	1	100.00

45                        end else begin : gen_sync
46         1/1              assign filter_synced = filter_i;
           Tests:       T26 T27 T28 
47                        end
48                      
49                        always_ff @(posedge clk_i or negedge rst_ni) begin
50         1/1              if (!rst_ni) begin
           Tests:       T26 T27 T28 
51         1/1                filter_q <= 1'b0;
           Tests:       T26 T27 T28 
52                          end else begin
53         1/1                filter_q <= filter_synced;
           Tests:       T26 T27 T28 
54                          end
55                        end
56                      
57                        always_ff @(posedge clk_i or negedge rst_ni) begin
58         1/1              if (!rst_ni) begin
           Tests:       T26 T27 T28 
59         1/1                stored_value_q <= 1'b0;
           Tests:       T26 T27 T28 
60         1/1              end else if (update_stored_value) begin
           Tests:       T26 T27 T28 
61         1/1                stored_value_q <= filter_synced;
           Tests:       T26 T27 T28 
62                          end
                        MISSING_ELSE
63                        end
64                      
65                        always_ff @(posedge clk_i or negedge rst_ni) begin
66         1/1              if (!rst_ni) begin
           Tests:       T26 T27 T28 
67         1/1                diff_ctr_q <= '0;
           Tests:       T26 T27 T28 
68                          end else begin
69         1/1                diff_ctr_q <= diff_ctr_d;
           Tests:       T26 T27 T28 
70                          end
71                        end
72                      
73                        // always look for differences, even if not filter enabled
74         1/1            assign update_stored_value = (diff_ctr_d == thresh_i);
           Tests:       T26 T27 T28 
75         1/1            assign diff_ctr_d = (filter_synced != filter_q) ? '0       :           // restart
           Tests:       T26 T27 T28 
76                                            (diff_ctr_q >= thresh_i)    ? thresh_i :           // saturate
77                                                                          (diff_ctr_q + 1'b1); // count up
78                      
79         1/1            assign filter_o = enable_i ? stored_value_q : filter_synced;
           Tests:       T26 T27 T28 

---

Cond Coverage for Instance : tb.dut.gen_filter[31].u_filter

	Total	Covered	Percent
Conditions	10	10	100.00
Logical	10	10	100.00
Non-Logical	0	0
Event	0	0

 LINE       74
 EXPRESSION (diff_ctr_d == thresh_i)
            ------------1-----------

-1-	Status	Tests
0	Covered	T26,T27,T28
1	Covered	T26,T27,T28

 LINE       75
 EXPRESSION ((filter_synced != filter_q) ? '0 : ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1))))
             -------------1-------------

-1-	Status	Tests
0	Covered	T26,T27,T28
1	Covered	T26,T27,T28

 LINE       75
 SUB-EXPRESSION (filter_synced != filter_q)
                -------------1-------------

-1-	Status	Tests
0	Covered	T26,T27,T28
1	Covered	T26,T27,T28

 LINE       75
 SUB-EXPRESSION ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1)))
                 ------------1-----------

-1-	Status	Tests
0	Covered	T26,T27,T28
1	Covered	T26,T27,T28

 LINE       79
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---

-1-	Status	Tests
0	Covered	T26,T27,T28
1	Covered	T32,T34,T35

---

Branch Coverage for Instance : tb.dut.gen_filter[31].u_filter

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	75	3	3	100.00
TERNARY	79	2	2	100.00
IF	50	2	2	100.00
IF	58	3	3	100.00
IF	66	2	2	100.00

75           assign diff_ctr_d = (filter_synced != filter_q) ? '0       :           // restart
                                                             -1-  
                                                             ==>  
76                               (diff_ctr_q >= thresh_i)    ? thresh_i :           // saturate
                                                             -2-  
                                                             ==>  
                                                             ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T26,T27,T28
0	1	Covered	T26,T27,T28
0	0	Covered	T26,T27,T28

79           assign filter_o = enable_i ? stored_value_q : filter_synced;
                                        -1-  
                                        ==>  
                                        ==>  

Branches:

-1-	Status	Tests
1	Covered	T32,T34,T35
0	Covered	T26,T27,T28

50             if (!rst_ni) begin
               -1-  
51               filter_q <= 1'b0;
                 ==>
52             end else begin
53               filter_q <= filter_synced;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T26,T27,T28
0	Covered	T26,T27,T28

58             if (!rst_ni) begin
               -1-  
59               stored_value_q <= 1'b0;
                 ==>
60             end else if (update_stored_value) begin
                        -2-  
61               stored_value_q <= filter_synced;
                 ==>
62             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T26,T27,T28
0	1	Covered	T26,T27,T28
0	0	Covered	T26,T27,T28

66             if (!rst_ni) begin
               -1-  
67               diff_ctr_q <= '0;
                 ==>
68             end else begin
69               diff_ctr_q <= diff_ctr_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T26,T27,T28
0	Covered	T26,T27,T28