Unified Coverage Report :: Module :: gpio_csr_assert_fpv

Module : gpio_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/gpio-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_gpio_csr_assert_0/gpio_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gpio_csr_assert	85.71						85.71

---

Module Instance : tb.dut.gpio_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : gpio_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	6	85.71
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	6	85.71

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	47395936	0	0	0
ctrl_en_input_filter_rd_A	47395936	51526	0	0
intr_ctrl_en_falling_rd_A	47395936	51559	0	0
intr_ctrl_en_lvlhigh_rd_A	47395936	51472	0	0
intr_ctrl_en_lvllow_rd_A	47395936	51601	0	0
intr_ctrl_en_rising_rd_A	47395936	50914	0	0
intr_enable_rd_A	47395936	51035	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	47395936	0	0	0

ctrl_en_input_filter_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	47395936	51526	0	0
T1	6200	1	0	0
T2	21273	141	0	0
T3	0	9	0	0
T4	0	324	0	0
T5	0	304	0	0
T6	0	4	0	0
T7	0	272	0	0
T8	0	135	0	0
T9	0	1	0	0
T10	0	64	0	0
T11	23077	0	0	0
T12	8553	0	0	0
T13	6241	0	0	0
T14	1353	0	0	0
T15	4515	0	0	0
T16	10648	0	0	0
T17	3900	0	0	0
T18	3615	0	0	0

intr_ctrl_en_falling_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	47395936	51559	0	0
T1	6200	17	0	0
T2	21273	124	0	0
T4	0	293	0	0
T5	0	426	0	0
T6	0	6	0	0
T7	0	207	0	0
T8	0	140	0	0
T10	0	136	0	0
T11	23077	0	0	0
T12	8553	0	0	0
T13	6241	0	0	0
T14	1353	0	0	0
T15	4515	0	0	0
T16	10648	0	0	0
T17	3900	0	0	0
T18	3615	0	0	0
T19	0	1	0	0
T20	0	1294	0	0

intr_ctrl_en_lvlhigh_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	47395936	51472	0	0
T1	6200	6	0	0
T2	21273	115	0	0
T3	0	11	0	0
T4	0	325	0	0
T5	0	369	0	0
T6	0	4	0	0
T7	0	303	0	0
T8	0	163	0	0
T10	0	73	0	0
T11	23077	0	0	0
T12	8553	0	0	0
T13	6241	0	0	0
T14	1353	0	0	0
T15	4515	0	0	0
T16	10648	0	0	0
T17	3900	0	0	0
T18	3615	0	0	0
T20	0	1345	0	0

intr_ctrl_en_lvllow_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	47395936	51601	0	0
T1	6200	14	0	0
T2	21273	97	0	0
T4	0	342	0	0
T5	0	394	0	0
T7	0	223	0	0
T8	0	134	0	0
T9	0	9	0	0
T10	0	85	0	0
T11	23077	0	0	0
T12	8553	0	0	0
T13	6241	0	0	0
T14	1353	0	0	0
T15	4515	0	0	0
T16	10648	0	0	0
T17	3900	0	0	0
T18	3615	0	0	0
T19	0	1	0	0
T21	0	1	0	0

intr_ctrl_en_rising_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	47395936	50914	0	0
T2	21273	143	0	0
T3	0	3	0	0
T4	0	406	0	0
T5	0	452	0	0
T6	0	12	0	0
T7	0	248	0	0
T8	0	134	0	0
T9	0	19	0	0
T13	6241	0	0	0
T14	1353	0	0	0
T15	4515	0	0	0
T16	10648	0	0	0
T17	3900	0	0	0
T18	3615	0	0	0
T19	0	4	0	0
T22	0	10	0	0
T23	4119	0	0	0
T24	6880	0	0	0
T25	6533	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	47395936	51035	0	0
T1	6200	18	0	0
T2	21273	142	0	0
T4	0	332	0	0
T5	0	481	0	0
T7	0	219	0	0
T8	0	144	0	0
T10	0	76	0	0
T11	23077	0	0	0
T12	8553	0	0	0
T13	6241	0	0	0
T14	1353	0	0	0
T15	4515	0	0	0
T16	10648	0	0	0
T17	3900	0	0	0
T18	3615	0	0	0
T19	0	1	0	0
T20	0	1215	0	0
T22	0	5	0	0