Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/gpio-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1348882	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4790561

1

T33

69

T34

181

T35

197

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2744420	1			T33	17		T34	133		T35	198
values[0x0]	1692357	1			T33	35		T34	55		T35	46
values[0x1]	1702666	1			T33	25		T34	63		T35	64

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1072103	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5067340

1

T33

69

T34

192

T35

218

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	17821	1			T33	1		T36	3		T39	1
valid_sources[0x01]	17537	1			T36	5		T39	2		T41	6
valid_sources[0x02]	18348	1			T36	2		T39	2		T41	6
valid_sources[0x03]	19133	1			T34	1		T39	2		T41	3
valid_sources[0x04]	17877	1			T34	1		T36	1		T41	5
valid_sources[0x05]	22238	1			T39	2		T41	5		T42	8
valid_sources[0x06]	17598	1			T34	1		T39	1		T41	11
valid_sources[0x07]	17776	1			T34	1		T39	1		T41	8
valid_sources[0x08]	18382	1			T34	1		T36	4		T41	8
valid_sources[0x09]	16902	1			T34	1		T36	1		T39	2
valid_sources[0x0a]	19305	1			T34	1		T36	2		T41	10
valid_sources[0x0b]	17707	1			T36	1		T39	3		T41	12
valid_sources[0x0c]	16998	1			T34	2		T39	1		T41	9
valid_sources[0x0d]	19154	1			T36	1		T39	1		T41	5
valid_sources[0x0e]	17929	1			T34	2		T42	15		T66	6
valid_sources[0x0f]	18250	1			T34	2		T36	4		T39	4
valid_sources[0x10]	19480	1			T39	1		T41	8		T42	5
valid_sources[0x11]	18710	1			T34	2		T39	1		T41	2
valid_sources[0x12]	16937	1			T34	1		T39	2		T41	4
valid_sources[0x13]	19501	1			T39	2		T41	7		T42	1
valid_sources[0x14]	19363	1			T34	1		T36	1		T39	3
valid_sources[0x15]	17318	1			T36	2		T39	1		T41	12
valid_sources[0x16]	23088	1			T36	2		T39	3		T41	6
valid_sources[0x17]	18167	1			T34	2		T36	2		T39	2
valid_sources[0x18]	17755	1			T34	1		T36	2		T39	3
valid_sources[0x19]	20381	1			T33	8		T34	1		T36	2
valid_sources[0x1a]	18857	1			T34	2		T36	2		T41	3
valid_sources[0x1b]	19030	1			T36	5		T41	7		T42	6
valid_sources[0x1c]	20099	1			T33	1		T36	1		T39	3
valid_sources[0x1d]	17181	1			T34	3		T39	1		T41	9
valid_sources[0x1e]	17944	1			T34	2		T36	2		T41	6
valid_sources[0x1f]	17484	1			T34	2		T39	2		T41	4
valid_sources[0x20]	70102	1			T33	7		T34	1		T39	1
valid_sources[0x21]	166834	1			T34	5		T36	2		T39	2
valid_sources[0x22]	21201	1			T36	2		T39	2		T41	11
valid_sources[0x23]	17865	1			T39	2		T41	2		T42	6
valid_sources[0x24]	18660	1			T33	4		T34	2		T39	2
valid_sources[0x25]	19676	1			T34	2		T36	1		T39	1
valid_sources[0x26]	16863	1			T34	1		T36	1		T39	7
valid_sources[0x27]	18710	1			T34	1		T36	1		T38	37
valid_sources[0x28]	21599	1			T34	3		T36	3		T41	6
valid_sources[0x29]	18636	1			T36	1		T39	2		T41	6
valid_sources[0x2a]	17909	1			T34	2		T39	3		T41	2
valid_sources[0x2b]	17226	1			T34	2		T36	3		T39	1
valid_sources[0x2c]	18513	1			T34	5		T36	1		T39	3
valid_sources[0x2d]	17611	1			T36	2		T39	2		T41	4
valid_sources[0x2e]	17235	1			T34	1		T41	6		T42	6
valid_sources[0x2f]	22867	1			T36	3		T39	3		T41	5
valid_sources[0x30]	18490	1			T34	4		T36	3		T41	6
valid_sources[0x31]	17249	1			T39	6		T41	3		T42	8
valid_sources[0x32]	17463	1			T34	1		T36	4		T38	22
valid_sources[0x33]	18935	1			T34	2		T41	9		T42	2
valid_sources[0x34]	18732	1			T34	2		T36	2		T41	6
valid_sources[0x35]	149980	1			T34	1		T39	4		T41	7
valid_sources[0x36]	21329	1			T36	2		T39	5		T41	10
valid_sources[0x37]	18173	1			T34	2		T41	6		T42	6
valid_sources[0x38]	16694	1			T36	1		T39	4		T41	6
valid_sources[0x39]	20389	1			T34	2		T39	2		T41	2
valid_sources[0x3a]	17098	1			T39	2		T41	9		T42	14
valid_sources[0x3b]	21103	1			T34	1		T39	1		T41	3
valid_sources[0x3c]	21480	1			T36	3		T39	2		T41	6
valid_sources[0x3d]	19332	1			T34	2		T39	4		T41	3
valid_sources[0x3e]	19197	1			T34	2		T36	5		T39	4
valid_sources[0x3f]	17836	1			T34	1		T41	5		T42	8
valid_sources[0x40]	18355	1			T34	2		T36	2		T39	2
valid_sources[0x41]	22410	1			T34	2		T36	5		T41	6
valid_sources[0x42]	19120	1			T34	1		T39	5		T41	8
valid_sources[0x43]	18406	1			T34	2		T36	2		T39	1
valid_sources[0x44]	20648	1			T39	4		T41	3		T42	11
valid_sources[0x45]	17502	1			T36	1		T38	18		T39	1
valid_sources[0x46]	19728	1			T36	2		T39	6		T41	8
valid_sources[0x47]	17119	1			T34	2		T36	1		T39	1
valid_sources[0x48]	17746	1			T36	1		T39	1		T41	2
valid_sources[0x49]	17990	1			T34	3		T39	1		T41	7
valid_sources[0x4a]	18756	1			T36	1		T41	4		T42	6
valid_sources[0x4b]	17490	1			T41	8		T42	7		T66	1
valid_sources[0x4c]	19957	1			T36	3		T39	1		T41	6
valid_sources[0x4d]	16722	1			T36	1		T39	1		T41	10
valid_sources[0x4e]	16869	1			T34	1		T39	2		T41	7
valid_sources[0x4f]	17411	1			T34	1		T36	2		T39	3
valid_sources[0x50]	18464	1			T34	1		T36	1		T39	3
valid_sources[0x51]	97101	1			T34	1		T39	1		T41	7
valid_sources[0x52]	17528	1			T34	1		T39	2		T41	4
valid_sources[0x53]	21315	1			T34	1		T39	3		T41	4
valid_sources[0x54]	17769	1			T34	1		T39	1		T41	7
valid_sources[0x55]	17933	1			T34	1		T39	3		T41	4
valid_sources[0x56]	18709	1			T34	1		T36	2		T39	6
valid_sources[0x57]	20589	1			T39	5		T41	8		T42	12
valid_sources[0x58]	18041	1			T34	1		T39	5		T41	7
valid_sources[0x59]	17114	1			T39	4		T41	6		T42	10
valid_sources[0x5a]	17366	1			T34	1		T41	8		T42	4
valid_sources[0x5b]	19660	1			T36	3		T39	3		T41	9
valid_sources[0x5c]	167513	1			T34	1		T36	2		T39	1
valid_sources[0x5d]	20004	1			T34	1		T39	2		T41	4
valid_sources[0x5e]	16857	1			T36	2		T39	2		T41	8
valid_sources[0x5f]	19209	1			T36	1		T39	3		T41	7
valid_sources[0x60]	17574	1			T34	1		T39	1		T41	7
valid_sources[0x61]	22317	1			T36	4		T39	4		T41	17
valid_sources[0x62]	16954	1			T36	3		T41	11		T42	4
valid_sources[0x63]	18563	1			T34	1		T41	4		T42	5
valid_sources[0x64]	18065	1			T34	2		T36	2		T41	5
valid_sources[0x65]	20705	1			T39	2		T41	7		T42	7
valid_sources[0x66]	17434	1			T34	2		T39	2		T41	9
valid_sources[0x67]	18730	1			T34	3		T39	2		T41	2
valid_sources[0x68]	18352	1			T34	1		T39	1		T41	1
valid_sources[0x69]	17634	1			T34	2		T39	2		T41	4
valid_sources[0x6a]	17582	1			T39	1		T41	7		T42	5
valid_sources[0x6b]	17607	1			T39	2		T41	7		T42	9
valid_sources[0x6c]	17507	1			T34	1		T36	6		T39	1
valid_sources[0x6d]	16979	1			T39	2		T41	10		T42	10
valid_sources[0x6e]	17731	1			T34	1		T36	3		T39	2
valid_sources[0x6f]	18977	1			T39	2		T41	7		T42	9
valid_sources[0x70]	18364	1			T34	1		T41	5		T42	6
valid_sources[0x71]	93298	1			T36	5		T39	3		T41	6
valid_sources[0x72]	17693	1			T34	3		T39	2		T41	4
valid_sources[0x73]	17733	1			T39	5		T41	13		T42	5
valid_sources[0x74]	18060	1			T34	1		T36	10		T39	1
valid_sources[0x75]	19155	1			T34	1		T36	9		T41	6
valid_sources[0x76]	20332	1			T36	1		T39	2		T41	4
valid_sources[0x77]	17720	1			T41	7		T42	8		T66	3
valid_sources[0x78]	17726	1			T36	1		T41	9		T42	6
valid_sources[0x79]	20482	1			T34	1		T39	2		T41	7
valid_sources[0x7a]	17650	1			T36	1		T39	3		T41	10
valid_sources[0x7b]	20399	1			T34	1		T39	3		T41	4
valid_sources[0x7c]	20457	1			T34	1		T39	1		T41	7
valid_sources[0x7d]	24578	1			T34	1		T36	1		T39	3
valid_sources[0x7e]	17824	1			T33	15		T34	1		T36	1
valid_sources[0x7f]	17840	1			T34	2		T36	1		T39	3
valid_sources[0x80]	17042	1			T39	3		T41	10		T42	12

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1410686

1

T33

9

T34

63

T35

87

values[0x0]

all_enables

biggest_size

1690649

1

T33

35

T34

55

T35

46

values[0x1]

all_enables

biggest_size

1689226

1

T33

25

T34

63

T35

64