Unified Coverage Report :: Module :: gpio_csr_assert_fpv

Module : gpio_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/gpio-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_gpio_csr_assert_0/gpio_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gpio_csr_assert	85.71						85.71

---

Module Instance : tb.dut.gpio_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : gpio_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	6	85.71
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	6	85.71

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	50951490	0	0	0
ctrl_en_input_filter_rd_A	50951490	59099	0	0
intr_ctrl_en_falling_rd_A	50951490	59172	0	0
intr_ctrl_en_lvlhigh_rd_A	50951490	58613	0	0
intr_ctrl_en_lvllow_rd_A	50951490	58785	0	0
intr_ctrl_en_rising_rd_A	50951490	59211	0	0
intr_enable_rd_A	50951490	60162	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50951490	0	0	0

ctrl_en_input_filter_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50951490	59099	0	0
T1	26580	111	0	0
T2	0	65	0	0
T3	0	168	0	0
T4	0	171	0	0
T5	0	853	0	0
T6	0	60	0	0
T7	0	225	0	0
T8	0	8	0	0
T9	0	136	0	0
T10	0	476	0	0
T11	2788	0	0	0
T12	2660	0	0	0
T13	2127	0	0	0
T14	1831	0	0	0
T15	4597	0	0	0
T16	142182	0	0	0
T17	4864	0	0	0
T18	5868	0	0	0
T19	11907	0	0	0

intr_ctrl_en_falling_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50951490	59172	0	0
T1	0	107	0	0
T2	0	80	0	0
T3	0	233	0	0
T4	0	240	0	0
T5	0	932	0	0
T6	0	95	0	0
T7	0	181	0	0
T20	5086	2	0	0
T21	0	7	0	0
T22	0	2	0	0
T23	8152	0	0	0
T24	1260	0	0	0
T25	3304	0	0	0
T26	9056	0	0	0
T27	5272	0	0	0
T28	9203	0	0	0
T29	2599	0	0	0
T30	5970	0	0	0
T31	3436	0	0	0

intr_ctrl_en_lvlhigh_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50951490	58613	0	0
T1	26580	139	0	0
T2	0	48	0	0
T3	0	193	0	0
T4	0	140	0	0
T5	0	952	0	0
T6	0	136	0	0
T7	0	188	0	0
T8	0	14	0	0
T9	0	140	0	0
T11	2788	0	0	0
T12	2660	0	0	0
T13	2127	0	0	0
T14	1831	0	0	0
T15	4597	0	0	0
T16	142182	0	0	0
T17	4864	0	0	0
T18	5868	0	0	0
T19	11907	0	0	0
T21	0	6	0	0

intr_ctrl_en_lvllow_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50951490	58785	0	0
T1	0	69	0	0
T2	0	100	0	0
T3	0	168	0	0
T4	0	192	0	0
T5	0	910	0	0
T6	0	132	0	0
T7	0	153	0	0
T8	0	1	0	0
T20	5086	1	0	0
T23	8152	0	0	0
T24	1260	0	0	0
T25	3304	0	0	0
T26	9056	0	0	0
T27	5272	0	0	0
T28	9203	0	0	0
T29	2599	0	0	0
T30	5970	0	0	0
T31	3436	0	0	0
T32	0	10	0	0

intr_ctrl_en_rising_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50951490	59211	0	0
T1	26580	137	0	0
T2	0	68	0	0
T3	0	118	0	0
T4	0	220	0	0
T5	0	844	0	0
T6	0	131	0	0
T7	0	163	0	0
T9	0	177	0	0
T11	2788	0	0	0
T12	2660	0	0	0
T13	2127	0	0	0
T14	1831	0	0	0
T15	4597	0	0	0
T16	142182	0	0	0
T17	4864	0	0	0
T18	5868	0	0	0
T19	11907	0	0	0
T21	0	2	0	0
T32	0	6	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50951490	60162	0	0
T1	26580	119	0	0
T2	0	99	0	0
T3	0	128	0	0
T4	0	241	0	0
T5	0	979	0	0
T6	0	196	0	0
T7	0	238	0	0
T9	0	171	0	0
T10	0	533	0	0
T11	2788	0	0	0
T12	2660	0	0	0
T13	2127	0	0	0
T14	1831	0	0	0
T15	4597	0	0	0
T16	142182	0	0	0
T17	4864	0	0	0
T18	5868	0	0	0
T19	11907	0	0	0
T32	0	3	0	0