Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/gpio-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1362732	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4736996

1

T33

319

T34

330

T35

431

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2755224	1			T33	81		T34	145		T35	87
values[0x0]	1669292	1			T33	133		T34	121		T35	176
values[0x1]	1675212	1			T33	143		T34	139		T35	205

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1084858	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5014870

1

T33

323

T34

344

T35

437

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	18666	1			T34	5		T35	1		T37	3
valid_sources[0x01]	17225	1			T34	5		T35	2		T38	2
valid_sources[0x02]	18914	1			T33	8		T34	23		T37	1
valid_sources[0x03]	17756	1			T35	3		T38	2		T39	1
valid_sources[0x04]	18088	1			T34	2		T35	2		T38	2
valid_sources[0x05]	18654	1			T34	6		T38	1		T39	1
valid_sources[0x06]	17883	1			T35	1		T38	2		T39	6
valid_sources[0x07]	17316	1			T35	2		T36	5		T38	2
valid_sources[0x08]	17575	1			T34	11		T35	5		T38	1
valid_sources[0x09]	17622	1			T34	3		T35	2		T38	3
valid_sources[0x0a]	17272	1			T35	1		T38	2		T39	4
valid_sources[0x0b]	17199	1			T38	2		T39	4		T23	1
valid_sources[0x0c]	17392	1			T35	1		T37	2		T38	1
valid_sources[0x0d]	23507	1			T34	1		T35	4		T36	3
valid_sources[0x0e]	18065	1			T35	1		T38	4		T25	6
valid_sources[0x0f]	20971	1			T34	13		T38	1		T25	9
valid_sources[0x10]	18520	1			T34	1		T35	4		T38	1
valid_sources[0x11]	18951	1			T38	2		T39	7		T25	10
valid_sources[0x12]	17236	1			T33	3		T35	1		T38	2
valid_sources[0x13]	19098	1			T36	1		T38	3		T39	4
valid_sources[0x14]	17378	1			T36	1		T38	7		T39	1
valid_sources[0x15]	19547	1			T37	3		T38	5		T39	4
valid_sources[0x16]	16694	1			T35	1		T38	3		T39	1
valid_sources[0x17]	16954	1			T35	6		T38	2		T39	3
valid_sources[0x18]	18192	1			T35	1		T38	2		T39	1
valid_sources[0x19]	19216	1			T37	6		T38	1		T25	4
valid_sources[0x1a]	19700	1			T35	1		T38	3		T39	4
valid_sources[0x1b]	17414	1			T35	2		T36	9		T37	3
valid_sources[0x1c]	17691	1			T34	5		T35	1		T36	1
valid_sources[0x1d]	17646	1			T34	3		T35	2		T38	2
valid_sources[0x1e]	18310	1			T33	8		T34	1		T38	2
valid_sources[0x1f]	16696	1			T34	18		T35	1		T38	1
valid_sources[0x20]	18327	1			T36	6		T25	11		T27	1
valid_sources[0x21]	18481	1			T35	3		T37	3		T38	3
valid_sources[0x22]	23964	1			T37	3		T39	4		T25	7
valid_sources[0x23]	18654	1			T35	2		T37	2		T38	3
valid_sources[0x24]	17930	1			T33	29		T35	2		T38	1
valid_sources[0x25]	20030	1			T33	4		T34	1		T35	1
valid_sources[0x26]	18449	1			T34	4		T35	5		T25	4
valid_sources[0x27]	157582	1			T33	3		T34	4		T38	1
valid_sources[0x28]	18119	1			T36	2		T37	5		T39	2
valid_sources[0x29]	17665	1			T33	4		T35	4		T38	1
valid_sources[0x2a]	16846	1			T33	7		T35	1		T38	3
valid_sources[0x2b]	16264	1			T35	2		T38	1		T39	4
valid_sources[0x2c]	17125	1			T35	4		T38	3		T25	9
valid_sources[0x2d]	18448	1			T35	1		T37	5		T38	1
valid_sources[0x2e]	17738	1			T33	7		T35	1		T37	1
valid_sources[0x2f]	18565	1			T35	1		T38	1		T27	2
valid_sources[0x30]	17386	1			T34	10		T35	4		T38	1
valid_sources[0x31]	17319	1			T33	7		T38	1		T39	2
valid_sources[0x32]	18026	1			T35	1		T37	7		T39	2
valid_sources[0x33]	17812	1			T35	2		T37	1		T39	5
valid_sources[0x34]	18227	1			T34	5		T35	1		T37	1
valid_sources[0x35]	17430	1			T35	3		T36	3		T37	4
valid_sources[0x36]	20730	1			T35	3		T38	2		T39	3
valid_sources[0x37]	17182	1			T35	3		T38	3		T25	8
valid_sources[0x38]	176946	1			T34	4		T39	1		T21	199
valid_sources[0x39]	17486	1			T34	2		T38	3		T25	10
valid_sources[0x3a]	17563	1			T34	5		T36	1		T25	8
valid_sources[0x3b]	16924	1			T35	2		T38	2		T39	3
valid_sources[0x3c]	16557	1			T37	4		T38	1		T39	5
valid_sources[0x3d]	22377	1			T38	1		T39	2		T25	1
valid_sources[0x3e]	20037	1			T35	7		T38	2		T39	3
valid_sources[0x3f]	17358	1			T35	4		T38	4		T23	1
valid_sources[0x40]	17287	1			T35	4		T37	2		T38	2
valid_sources[0x41]	18012	1			T35	3		T38	2		T39	4
valid_sources[0x42]	18473	1			T35	1		T37	2		T38	1
valid_sources[0x43]	17013	1			T33	6		T38	6		T39	2
valid_sources[0x44]	18398	1			T35	2		T37	6		T38	1
valid_sources[0x45]	17823	1			T35	4		T37	2		T38	1
valid_sources[0x46]	17779	1			T38	1		T39	1		T25	3
valid_sources[0x47]	19363	1			T35	7		T38	5		T25	15
valid_sources[0x48]	17613	1			T35	3		T37	1		T38	4
valid_sources[0x49]	17010	1			T35	3		T37	4		T39	1
valid_sources[0x4a]	22192	1			T34	3		T35	8		T38	5
valid_sources[0x4b]	17874	1			T34	2		T35	1		T39	6
valid_sources[0x4c]	18347	1			T39	3		T25	7		T26	1
valid_sources[0x4d]	17396	1			T35	1		T36	6		T38	2
valid_sources[0x4e]	17028	1			T34	4		T35	2		T38	1
valid_sources[0x4f]	17619	1			T35	4		T38	1		T39	1
valid_sources[0x50]	19721	1			T38	6		T25	14		T26	1
valid_sources[0x51]	17678	1			T35	2		T38	4		T25	3
valid_sources[0x52]	18423	1			T39	2		T25	9		T26	5
valid_sources[0x53]	18386	1			T39	1		T25	28		T26	2
valid_sources[0x54]	17286	1			T35	4		T39	1		T25	14
valid_sources[0x55]	18639	1			T35	2		T37	1		T38	2
valid_sources[0x56]	17596	1			T33	1		T35	3		T38	1
valid_sources[0x57]	20870	1			T34	6		T39	2		T25	20
valid_sources[0x58]	17220	1			T34	2		T35	3		T37	5
valid_sources[0x59]	17576	1			T37	2		T38	2		T39	1
valid_sources[0x5a]	18346	1			T34	9		T38	1		T39	4
valid_sources[0x5b]	18550	1			T35	1		T39	5		T25	7
valid_sources[0x5c]	17221	1			T33	7		T34	1		T38	3
valid_sources[0x5d]	18555	1			T35	1		T36	7		T37	1
valid_sources[0x5e]	17666	1			T35	2		T39	6		T25	7
valid_sources[0x5f]	18457	1			T37	8		T38	3		T39	6
valid_sources[0x60]	17284	1			T35	1		T37	2		T39	4
valid_sources[0x61]	84245	1			T35	1		T38	1		T39	5
valid_sources[0x62]	17507	1			T35	4		T37	1		T38	1
valid_sources[0x63]	17718	1			T37	1		T38	1		T39	2
valid_sources[0x64]	17390	1			T33	4		T36	15		T38	2
valid_sources[0x65]	19775	1			T33	12		T35	3		T39	2
valid_sources[0x66]	19195	1			T33	8		T35	2		T39	2
valid_sources[0x67]	17742	1			T34	5		T38	2		T39	1
valid_sources[0x68]	17289	1			T38	1		T39	1		T25	2
valid_sources[0x69]	16888	1			T35	1		T38	1		T25	3
valid_sources[0x6a]	22355	1			T35	2		T37	2		T25	2
valid_sources[0x6b]	18472	1			T35	1		T38	1		T39	3
valid_sources[0x6c]	17008	1			T34	9		T35	4		T37	1
valid_sources[0x6d]	18250	1			T33	7		T35	1		T37	1
valid_sources[0x6e]	17551	1			T33	19		T35	3		T37	1
valid_sources[0x6f]	17366	1			T35	7		T37	1		T38	1
valid_sources[0x70]	173377	1			T35	2		T36	4		T38	3
valid_sources[0x71]	17466	1			T38	4		T39	2		T25	15
valid_sources[0x72]	18063	1			T35	1		T36	9		T39	1
valid_sources[0x73]	17881	1			T38	4		T39	7		T25	5
valid_sources[0x74]	17557	1			T35	2		T38	2		T39	5
valid_sources[0x75]	16819	1			T33	3		T34	3		T35	1
valid_sources[0x76]	18290	1			T34	11		T38	3		T39	3
valid_sources[0x77]	17333	1			T33	37		T38	1		T25	8
valid_sources[0x78]	17407	1			T38	5		T39	1		T25	7
valid_sources[0x79]	18200	1			T35	2		T38	3		T39	5
valid_sources[0x7a]	141436	1			T35	1		T38	3		T25	1
valid_sources[0x7b]	20208	1			T34	4		T35	1		T37	3
valid_sources[0x7c]	18609	1			T37	2		T38	1		T39	1
valid_sources[0x7d]	20581	1			T37	1		T38	3		T39	2
valid_sources[0x7e]	18703	1			T35	2		T36	14		T37	1
valid_sources[0x7f]	18492	1			T34	14		T35	1		T37	1
valid_sources[0x80]	20846	1			T38	2		T39	3		T27	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1403005

1

T33

43

T34

70

T35

50

values[0x0]

all_enables

biggest_size

1667968

1

T33

133

T34

121

T35

176

values[0x1]

all_enables

biggest_size

1666023

1

T33

143

T34

139

T35

205