Unified Coverage Report :: Module :: gpio_csr_assert_fpv

Module : gpio_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/gpio-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_gpio_csr_assert_0/gpio_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gpio_csr_assert	85.71						85.71

---

Module Instance : tb.dut.gpio_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : gpio_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	6	85.71
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	6	85.71

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	54297919	0	0	0
ctrl_en_input_filter_rd_A	54297919	74510	0	0
intr_ctrl_en_falling_rd_A	54297919	74750	0	0
intr_ctrl_en_lvlhigh_rd_A	54297919	73834	0	0
intr_ctrl_en_lvllow_rd_A	54297919	74161	0	0
intr_ctrl_en_rising_rd_A	54297919	73849	0	0
intr_enable_rd_A	54297919	74999	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54297919	0	0	0

ctrl_en_input_filter_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54297919	74510	0	0
T1	47130	206	0	0
T2	0	211	0	0
T3	0	117	0	0
T4	0	1	0	0
T5	0	57	0	0
T6	0	13	0	0
T7	0	287	0	0
T8	0	348	0	0
T9	0	192	0	0
T10	0	203	0	0
T11	1318	0	0	0
T12	10016	0	0	0
T13	4502	0	0	0
T14	7447	0	0	0
T15	3406	0	0	0
T16	2494	0	0	0
T17	2003	0	0	0
T18	3510	0	0	0
T19	3681	0	0	0

intr_ctrl_en_falling_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54297919	74750	0	0
T1	47130	278	0	0
T2	0	296	0	0
T3	0	95	0	0
T4	0	6	0	0
T5	0	48	0	0
T7	0	426	0	0
T8	0	457	0	0
T9	0	278	0	0
T10	0	192	0	0
T11	1318	0	0	0
T12	10016	0	0	0
T13	4502	0	0	0
T14	7447	0	0	0
T15	3406	0	0	0
T16	2494	0	0	0
T17	2003	0	0	0
T18	3510	0	0	0
T19	3681	0	0	0
T20	0	132	0	0

intr_ctrl_en_lvlhigh_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54297919	73834	0	0
T1	0	204	0	0
T2	0	299	0	0
T3	0	104	0	0
T5	0	42	0	0
T6	0	8	0	0
T7	0	277	0	0
T8	0	273	0	0
T9	0	202	0	0
T21	5822	8	0	0
T22	0	9	0	0
T23	1192	0	0	0
T24	3013	0	0	0
T25	6825	0	0	0
T26	2729	0	0	0
T27	3198	0	0	0
T28	7400	0	0	0
T29	1092	0	0	0
T30	4274	0	0	0
T31	4814	0	0	0

intr_ctrl_en_lvllow_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54297919	74161	0	0
T1	0	215	0	0
T2	0	281	0	0
T3	0	96	0	0
T4	0	10	0	0
T5	0	57	0	0
T7	0	273	0	0
T8	0	419	0	0
T9	0	290	0	0
T10	0	189	0	0
T21	5822	3	0	0
T23	1192	0	0	0
T24	3013	0	0	0
T25	6825	0	0	0
T26	2729	0	0	0
T27	3198	0	0	0
T28	7400	0	0	0
T29	1092	0	0	0
T30	4274	0	0	0
T31	4814	0	0	0

intr_ctrl_en_rising_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54297919	73849	0	0
T1	0	203	0	0
T2	0	283	0	0
T3	0	149	0	0
T5	0	12	0	0
T6	0	5	0	0
T7	0	342	0	0
T8	0	385	0	0
T9	0	182	0	0
T10	0	154	0	0
T21	5822	4	0	0
T23	1192	0	0	0
T24	3013	0	0	0
T25	6825	0	0	0
T26	2729	0	0	0
T27	3198	0	0	0
T28	7400	0	0	0
T29	1092	0	0	0
T30	4274	0	0	0
T31	4814	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54297919	74999	0	0
T1	47130	172	0	0
T2	0	282	0	0
T3	0	110	0	0
T5	0	47	0	0
T6	0	2	0	0
T7	0	333	0	0
T8	0	380	0	0
T9	0	326	0	0
T10	0	273	0	0
T11	1318	0	0	0
T12	10016	0	0	0
T13	4502	0	0	0
T14	7447	0	0	0
T15	3406	0	0	0
T16	2494	0	0	0
T17	2003	0	0	0
T18	3510	0	0	0
T19	3681	0	0	0
T32	0	5	0	0