Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/gpio-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1409145	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4981200

1

T43

36

T44

153

T45

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2859663	1			T43	22		T44	30		T45	1
values[0x0]	1761113	1			T43	8		T44	67		T45	4
values[0x1]	1769569	1			T43	17		T44	75		T45	6

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1121110	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5269235

1

T43

40

T44

154

T45

1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	22739	1			T43	2		T34	1		T36	2
valid_sources[0x01]	23437	1			T44	2		T38	2		T40	1
valid_sources[0x02]	131162	1			T34	3		T36	1		T37	2
valid_sources[0x03]	22090	1			T43	1		T44	4		T47	4
valid_sources[0x04]	22062	1			T33	6		T36	1		T40	1
valid_sources[0x05]	22123	1			T43	1		T34	2		T36	1
valid_sources[0x06]	22202	1			T47	2		T36	1		T39	1
valid_sources[0x07]	27193	1			T43	1		T47	3		T34	3
valid_sources[0x08]	21335	1			T38	2		T40	2		T60	15
valid_sources[0x09]	26654	1			T47	1		T34	4		T37	2
valid_sources[0x0a]	22846	1			T36	1		T37	2		T38	3
valid_sources[0x0b]	22585	1			T36	3		T37	1		T38	3
valid_sources[0x0c]	22009	1			T38	1		T39	1		T40	1
valid_sources[0x0d]	23405	1			T34	1		T40	2		T70	11
valid_sources[0x0e]	29044	1			T43	1		T46	19		T38	2
valid_sources[0x0f]	22694	1			T43	2		T34	2		T37	3
valid_sources[0x10]	21386	1			T47	1		T34	1		T36	1
valid_sources[0x11]	23862	1			T43	1		T34	1		T37	2
valid_sources[0x12]	22852	1			T34	2		T39	1		T40	1
valid_sources[0x13]	21689	1			T43	1		T44	1		T47	1
valid_sources[0x14]	21941	1			T36	1		T37	2		T39	1
valid_sources[0x15]	22774	1			T47	1		T36	2		T38	1
valid_sources[0x16]	22043	1			T36	1		T37	1		T38	2
valid_sources[0x17]	23915	1			T34	3		T36	1		T37	1
valid_sources[0x18]	22947	1			T36	2		T37	2		T38	3
valid_sources[0x19]	22353	1			T43	2		T37	5		T39	2
valid_sources[0x1a]	22689	1			T47	2		T33	7		T34	1
valid_sources[0x1b]	22211	1			T46	7		T33	8		T34	4
valid_sources[0x1c]	22103	1			T34	2		T37	2		T49	1
valid_sources[0x1d]	25755	1			T44	7		T47	3		T34	3
valid_sources[0x1e]	23680	1			T39	1		T60	10		T49	3
valid_sources[0x1f]	25277	1			T44	1		T46	5		T47	1
valid_sources[0x20]	22181	1			T43	2		T37	1		T39	2
valid_sources[0x21]	25479	1			T34	1		T36	1		T37	2
valid_sources[0x22]	22178	1			T36	1		T37	3		T38	4
valid_sources[0x23]	23737	1			T44	3		T34	2		T36	2
valid_sources[0x24]	24115	1			T34	1		T37	2		T39	1
valid_sources[0x25]	23774	1			T43	3		T34	1		T38	1
valid_sources[0x26]	23434	1			T44	3		T47	4		T34	1
valid_sources[0x27]	22861	1			T43	1		T47	2		T34	1
valid_sources[0x28]	22661	1			T44	5		T34	4		T37	1
valid_sources[0x29]	22869	1			T36	1		T37	1		T38	5
valid_sources[0x2a]	22850	1			T47	3		T36	1		T37	3
valid_sources[0x2b]	21503	1			T34	1		T36	3		T37	4
valid_sources[0x2c]	22573	1			T44	6		T36	3		T37	1
valid_sources[0x2d]	23055	1			T34	1		T37	2		T38	1
valid_sources[0x2e]	22245	1			T34	1		T37	3		T40	2
valid_sources[0x2f]	22918	1			T34	4		T37	3		T38	1
valid_sources[0x30]	22485	1			T44	1		T37	2		T38	4
valid_sources[0x31]	22246	1			T34	2		T36	1		T38	2
valid_sources[0x32]	22356	1			T46	11		T34	1		T36	2
valid_sources[0x33]	21823	1			T47	1		T34	2		T36	2
valid_sources[0x34]	21334	1			T44	6		T47	1		T34	3
valid_sources[0x35]	23509	1			T46	8		T34	1		T36	1
valid_sources[0x36]	22597	1			T34	2		T37	2		T38	1
valid_sources[0x37]	23554	1			T47	2		T34	2		T38	3
valid_sources[0x38]	22675	1			T36	1		T38	1		T39	1
valid_sources[0x39]	22456	1			T47	2		T37	1		T38	2
valid_sources[0x3a]	22979	1			T44	4		T36	1		T37	3
valid_sources[0x3b]	24211	1			T37	7		T39	2		T40	1
valid_sources[0x3c]	22117	1			T44	2		T36	1		T37	2
valid_sources[0x3d]	23023	1			T34	1		T38	2		T39	3
valid_sources[0x3e]	29102	1			T37	1		T38	5		T39	1
valid_sources[0x3f]	22348	1			T44	1		T34	5		T36	1
valid_sources[0x40]	22896	1			T34	1		T36	2		T38	1
valid_sources[0x41]	23490	1			T37	3		T40	2		T41	1
valid_sources[0x42]	22222	1			T36	1		T37	1		T39	1
valid_sources[0x43]	21590	1			T47	1		T37	2		T38	7
valid_sources[0x44]	23271	1			T47	10		T34	3		T36	1
valid_sources[0x45]	21624	1			T46	1		T47	4		T34	3
valid_sources[0x46]	22378	1			T34	1		T38	4		T39	1
valid_sources[0x47]	26051	1			T44	14		T34	1		T37	1
valid_sources[0x48]	22694	1			T34	3		T36	1		T37	2
valid_sources[0x49]	21791	1			T44	6		T47	2		T34	1
valid_sources[0x4a]	22874	1			T47	5		T34	1		T36	1
valid_sources[0x4b]	23178	1			T47	1		T34	1		T36	1
valid_sources[0x4c]	22075	1			T34	1		T36	1		T37	1
valid_sources[0x4d]	22369	1			T36	1		T37	2		T38	1
valid_sources[0x4e]	27332	1			T34	2		T36	2		T37	1
valid_sources[0x4f]	22839	1			T34	2		T36	2		T37	1
valid_sources[0x50]	23969	1			T43	1		T44	5		T47	2
valid_sources[0x51]	23431	1			T47	6		T36	2		T37	2
valid_sources[0x52]	23111	1			T47	1		T34	4		T38	1
valid_sources[0x53]	22839	1			T43	1		T36	3		T37	1
valid_sources[0x54]	21647	1			T36	1		T37	1		T38	7
valid_sources[0x55]	22204	1			T37	2		T38	5		T40	1
valid_sources[0x56]	24987	1			T36	1		T37	2		T38	2
valid_sources[0x57]	22842	1			T34	1		T37	2		T60	1
valid_sources[0x58]	23411	1			T34	1		T37	1		T39	3
valid_sources[0x59]	21950	1			T47	3		T34	2		T37	2
valid_sources[0x5a]	24133	1			T37	1		T40	1		T55	1
valid_sources[0x5b]	22669	1			T46	1		T34	1		T36	3
valid_sources[0x5c]	22594	1			T47	1		T33	7		T34	1
valid_sources[0x5d]	23294	1			T44	1		T47	1		T34	1
valid_sources[0x5e]	22478	1			T44	2		T34	1		T37	2
valid_sources[0x5f]	23750	1			T43	2		T47	5		T36	3
valid_sources[0x60]	22686	1			T44	3		T34	2		T37	1
valid_sources[0x61]	23207	1			T47	1		T33	2		T37	2
valid_sources[0x62]	23730	1			T43	1		T47	2		T34	2
valid_sources[0x63]	21966	1			T34	3		T37	2		T38	2
valid_sources[0x64]	22350	1			T33	1		T38	3		T39	2
valid_sources[0x65]	22783	1			T34	2		T38	2		T40	1
valid_sources[0x66]	23000	1			T34	2		T38	4		T39	3
valid_sources[0x67]	22139	1			T34	1		T36	1		T37	3
valid_sources[0x68]	23286	1			T34	1		T38	3		T60	1
valid_sources[0x69]	22443	1			T44	2		T34	2		T37	1
valid_sources[0x6a]	21909	1			T34	1		T36	1		T37	1
valid_sources[0x6b]	22183	1			T43	1		T36	1		T38	3
valid_sources[0x6c]	22385	1			T36	1		T37	1		T39	1
valid_sources[0x6d]	23284	1			T36	2		T37	2		T40	2
valid_sources[0x6e]	22767	1			T33	3		T34	1		T37	4
valid_sources[0x6f]	21793	1			T33	13		T34	2		T37	1
valid_sources[0x70]	22762	1			T34	1		T36	1		T39	2
valid_sources[0x71]	22603	1			T38	2		T40	2		T60	1
valid_sources[0x72]	25722	1			T38	8		T39	3		T40	1
valid_sources[0x73]	27308	1			T36	2		T37	1		T40	3
valid_sources[0x74]	22935	1			T33	27		T36	2		T37	1
valid_sources[0x75]	22320	1			T37	1		T38	5		T40	2
valid_sources[0x76]	22382	1			T44	4		T47	3		T60	3
valid_sources[0x77]	24457	1			T34	1		T37	2		T39	3
valid_sources[0x78]	23335	1			T34	4		T38	2		T40	1
valid_sources[0x79]	22204	1			T44	5		T34	3		T36	1
valid_sources[0x7a]	23905	1			T43	1		T34	1		T36	1
valid_sources[0x7b]	26849	1			T45	11		T37	2		T39	1
valid_sources[0x7c]	21633	1			T37	3		T38	4		T40	3
valid_sources[0x7d]	43006	1			T33	2		T37	1		T40	2
valid_sources[0x7e]	23704	1			T44	1		T33	1		T36	1
valid_sources[0x7f]	22290	1			T47	3		T34	1		T36	1
valid_sources[0x80]	24474	1			T47	3		T37	2		T39	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1463967

1

T43

11

T44

11

T45

1

values[0x0]

all_enables

biggest_size

1759507

1

T43

8

T44

67

T46

26

values[0x1]

all_enables

biggest_size

1757726

1

T43

17

T44

75

T46

28