Unified Coverage Report :: Module :: gpio_csr_assert_fpv

Module : gpio_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/gpio-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_gpio_csr_assert_0/gpio_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gpio_csr_assert	85.71						85.71

---

Module Instance : tb.dut.gpio_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : gpio_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	6	85.71
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	6	85.71

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	52083605	0	0	0
ctrl_en_input_filter_rd_A	52083605	63234	0	0
intr_ctrl_en_falling_rd_A	52083605	63717	0	0
intr_ctrl_en_lvlhigh_rd_A	52083605	63671	0	0
intr_ctrl_en_lvllow_rd_A	52083605	63615	0	0
intr_ctrl_en_rising_rd_A	52083605	62825	0	0
intr_enable_rd_A	52083605	64315	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52083605	0	0	0

ctrl_en_input_filter_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52083605	63234	0	0
T1	41819	218	0	0
T2	0	341	0	0
T3	0	389	0	0
T4	0	9	0	0
T5	0	182	0	0
T6	0	2654	0	0
T7	0	839	0	0
T8	0	1830	0	0
T9	0	287	0	0
T10	0	8	0	0
T11	8862	0	0	0
T12	2727	0	0	0
T13	2614	0	0	0
T14	3144	0	0	0
T15	3500	0	0	0
T16	1021	0	0	0
T17	2855	0	0	0
T18	16848	0	0	0
T19	6483	0	0	0

intr_ctrl_en_falling_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52083605	63717	0	0
T1	0	210	0	0
T2	0	464	0	0
T3	0	388	0	0
T4	0	12	0	0
T5	0	152	0	0
T6	0	2715	0	0
T7	0	904	0	0
T8	0	1693	0	0
T20	5549	2	0	0
T21	0	19	0	0
T22	872	0	0	0
T23	2137	0	0	0
T24	10476	0	0	0
T25	5510	0	0	0
T26	2267	0	0	0
T27	4546	0	0	0
T28	4310	0	0	0
T29	3544	0	0	0
T30	6873	0	0	0

intr_ctrl_en_lvlhigh_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52083605	63671	0	0
T1	0	161	0	0
T2	0	336	0	0
T3	0	333	0	0
T5	0	209	0	0
T6	0	2606	0	0
T7	0	1009	0	0
T8	0	2012	0	0
T9	0	389	0	0
T31	4079	4	0	0
T32	0	7	0	0
T33	4040	0	0	0
T34	3361	0	0	0
T35	1831	0	0	0
T36	3774	0	0	0
T37	2516	0	0	0
T38	3870	0	0	0
T39	3565	0	0	0
T40	6823	0	0	0
T41	1220	0	0	0

intr_ctrl_en_lvllow_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52083605	63615	0	0
T1	41819	237	0	0
T2	0	376	0	0
T3	0	320	0	0
T4	0	5	0	0
T5	0	92	0	0
T6	0	2415	0	0
T7	0	1085	0	0
T8	0	1973	0	0
T9	0	332	0	0
T10	0	1	0	0
T11	8862	0	0	0
T12	2727	0	0	0
T13	2614	0	0	0
T14	3144	0	0	0
T15	3500	0	0	0
T16	1021	0	0	0
T17	2855	0	0	0
T18	16848	0	0	0
T19	6483	0	0	0

intr_ctrl_en_rising_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52083605	62825	0	0
T1	41819	169	0	0
T2	0	360	0	0
T3	0	396	0	0
T5	0	192	0	0
T6	0	2487	0	0
T7	0	1046	0	0
T8	0	1856	0	0
T9	0	259	0	0
T10	0	5	0	0
T11	8862	0	0	0
T12	2727	0	0	0
T13	2614	0	0	0
T14	3144	0	0	0
T15	3500	0	0	0
T16	1021	0	0	0
T17	2855	0	0	0
T18	16848	0	0	0
T19	6483	0	0	0
T42	0	4	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52083605	64315	0	0
T1	41819	225	0	0
T2	0	307	0	0
T3	0	384	0	0
T5	0	110	0	0
T6	0	2507	0	0
T7	0	844	0	0
T8	0	1884	0	0
T9	0	260	0	0
T10	0	4	0	0
T11	8862	0	0	0
T12	2727	0	0	0
T13	2614	0	0	0
T14	3144	0	0	0
T15	3500	0	0	0
T16	1021	0	0	0
T17	2855	0	0	0
T18	16848	0	0	0
T19	6483	0	0	0
T32	0	3	0	0