Module Definition
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Module : prim_subreg_arb
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.44 83.33 100.00 100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/gpio-sim-vcs/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_reg.u_data_in.wr_en_data_arb 50.00 50.00
tb.dut.u_reg.u_intr_state.wr_en_data_arb 100.00 100.00 100.00
tb.dut.u_reg.u_intr_enable.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_intr_ctrl_en_rising.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_intr_ctrl_en_falling.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_intr_ctrl_en_lvlhigh.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_intr_ctrl_en_lvllow.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_ctrl_en_input_filter.wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_data_in.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
50.00 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
50.00 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
70.24 85.71 50.00 75.00 u_data_in


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_intr_state.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_intr_state


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_intr_enable.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_intr_enable


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_intr_ctrl_en_rising.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_intr_ctrl_en_rising


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_intr_ctrl_en_falling.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_intr_ctrl_en_falling


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_intr_ctrl_en_lvlhigh.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_intr_ctrl_en_lvlhigh


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_intr_ctrl_en_lvllow.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_intr_ctrl_en_lvllow


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_ctrl_en_input_filter.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_ctrl_en_input_filter


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : prim_subreg_arb ( parameter DW=32,SwAccess=3,Mubi=0 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_reg.u_intr_state.wr_en_data_arb

Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN8811100.00
CONT_ASSIGN11011100.00


87                          // If both try to set/clr at the same bit pos, SW wins.
88         1/1              assign wr_en   = we | de;
           Tests:       T43 T44 T45 
89                          if (Mubi) begin : gen_mubi
90                            if (DW == 4) begin : gen_mubi4
91                              assign wr_data = prim_mubi_pkg::mubi4_and_hi(prim_mubi_pkg::mubi4_t'(de ? d : q),
92                                                                           (we ? prim_mubi_pkg::mubi4_t'(~wd) :
93                                                                                 prim_mubi_pkg::MuBi4True));
94                            end else if (DW == 8) begin : gen_mubi8
95                              assign wr_data = prim_mubi_pkg::mubi8_and_hi(prim_mubi_pkg::mubi8_t'(de ? d : q),
96                                                                           (we ? prim_mubi_pkg::mubi8_t'(~wd) :
97                                                                                 prim_mubi_pkg::MuBi8True));
98                            end else if (DW == 12) begin : gen_mubi12
99                              assign wr_data = prim_mubi_pkg::mubi12_and_hi(prim_mubi_pkg::mubi12_t'(de ? d : q),
100                                                                           (we ? prim_mubi_pkg::mubi12_t'(~wd) :
101                                                                                 prim_mubi_pkg::MuBi12True));
102                           end else if (DW == 16) begin : gen_mubi16
103                             assign wr_data = prim_mubi_pkg::mubi16_and_hi(prim_mubi_pkg::mubi16_t'(de ? d : q),
104                                                                           (we ? prim_mubi_pkg::mubi16_t'(~wd) :
105                                                                                 prim_mubi_pkg::MuBi16True));
106                           end else begin : gen_invalid_mubi
107                             $error("%m: Invalid width for MuBi");
108                           end
109                         end else begin : gen_non_mubi
110        1/1                assign wr_data = (de ? d : q) & (we ? ~wd : '1);
           Tests:       T43 T44 T45 
Line Coverage for Module : prim_subreg_arb ( parameter DW=32,SwAccess=0,Mubi=0 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_reg.u_intr_enable.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_intr_ctrl_en_rising.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_intr_ctrl_en_falling.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_intr_ctrl_en_lvlhigh.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_intr_ctrl_en_lvllow.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_ctrl_en_input_filter.wr_en_data_arb

Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3900


32                        if (SwAccess inside {SwAccessRW, SwAccessWO}) begin : gen_w
33         1/1              assign wr_en   = we | de;
           Tests:       T31 T38 T39 
34         1/1              assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
           Tests:       T43 T44 T45 
35                          // Unused q - Prevent lint errors.
36                          logic [DW-1:0] unused_q;
37                          //VCS coverage off
38                          // pragma coverage off
39         unreachable      assign unused_q = q;
Line Coverage for Module : prim_subreg_arb ( parameter DW=32,SwAccess=1,Mubi=0 )
Line Coverage for Module self-instances :
SCORELINE
50.00 50.00
tb.dut.u_reg.u_data_in.wr_en_data_arb

Line No.TotalCoveredPercent
TOTAL2150.00
CONT_ASSIGN43100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN5100
CONT_ASSIGN5200
CONT_ASSIGN5300


42                        end else if (SwAccess == SwAccessRO) begin : gen_ro
43         0/1     ==>      assign wr_en   = de;
44         1/1              assign wr_data = d;
           Tests:       T43 T44 T45 
45                          // Unused we, wd, q - Prevent lint errors.
46                          logic          unused_we;
47                          logic [DW-1:0] unused_wd;
48                          logic [DW-1:0] unused_q;
49                          //VCS coverage off
50                          // pragma coverage off
51         unreachable      assign unused_we = we;
52         unreachable      assign unused_wd = wd;
53         unreachable      assign unused_q  = q;
Cond Coverage for Module : prim_subreg_arb ( parameter DW=32,SwAccess=3,Mubi=0 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_reg.u_intr_state.wr_en_data_arb

TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       88
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT43,T44,T45
01CoveredT31,T38,T39
10CoveredT31,T39,T48
Cond Coverage for Module : prim_subreg_arb ( parameter DW=32,SwAccess=0,Mubi=0 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_reg.u_intr_enable.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_intr_ctrl_en_rising.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_intr_ctrl_en_falling.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_intr_ctrl_en_lvlhigh.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_intr_ctrl_en_lvllow.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_ctrl_en_input_filter.wr_en_data_arb

TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT43,T44,T45
01Unreachable
10CoveredT31,T38,T39 

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT43,T44,T45
1CoveredT31,T38,T39 

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT43,T44,T45
1CoveredT31,T38,T39
Branch Coverage for Module : prim_subreg_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 34 2 2 100.00 



34             assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
                                             -1-  
                                             ==>  
                                             ==>

Branches:
-1-StatusTests
1 Covered T31,T38,T39
0 Covered T43,T44,T45

Line Coverage for Instance : tb.dut.u_reg.u_data_in.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL2150.00
CONT_ASSIGN43100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN5100
CONT_ASSIGN5200
CONT_ASSIGN5300


42                        end else if (SwAccess == SwAccessRO) begin : gen_ro
43         0/1     ==>      assign wr_en   = de;
44         1/1              assign wr_data = d;
           Tests:       T43 T44 T45 
45                          // Unused we, wd, q - Prevent lint errors.
46                          logic          unused_we;
47                          logic [DW-1:0] unused_wd;
48                          logic [DW-1:0] unused_q;
49                          //VCS coverage off
50                          // pragma coverage off
51         unreachable      assign unused_we = we;
52         unreachable      assign unused_wd = wd;
53         unreachable      assign unused_q  = q;
Line Coverage for Instance : tb.dut.u_reg.u_intr_state.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN8811100.00
CONT_ASSIGN11011100.00


87                          // If both try to set/clr at the same bit pos, SW wins.
88         1/1              assign wr_en   = we | de;
           Tests:       T43 T44 T45 
89                          if (Mubi) begin : gen_mubi
90                            if (DW == 4) begin : gen_mubi4
91                              assign wr_data = prim_mubi_pkg::mubi4_and_hi(prim_mubi_pkg::mubi4_t'(de ? d : q),
92                                                                           (we ? prim_mubi_pkg::mubi4_t'(~wd) :
93                                                                                 prim_mubi_pkg::MuBi4True));
94                            end else if (DW == 8) begin : gen_mubi8
95                              assign wr_data = prim_mubi_pkg::mubi8_and_hi(prim_mubi_pkg::mubi8_t'(de ? d : q),
96                                                                           (we ? prim_mubi_pkg::mubi8_t'(~wd) :
97                                                                                 prim_mubi_pkg::MuBi8True));
98                            end else if (DW == 12) begin : gen_mubi12
99                              assign wr_data = prim_mubi_pkg::mubi12_and_hi(prim_mubi_pkg::mubi12_t'(de ? d : q),
100                                                                           (we ? prim_mubi_pkg::mubi12_t'(~wd) :
101                                                                                 prim_mubi_pkg::MuBi12True));
102                           end else if (DW == 16) begin : gen_mubi16
103                             assign wr_data = prim_mubi_pkg::mubi16_and_hi(prim_mubi_pkg::mubi16_t'(de ? d : q),
104                                                                           (we ? prim_mubi_pkg::mubi16_t'(~wd) :
105                                                                                 prim_mubi_pkg::MuBi16True));
106                           end else begin : gen_invalid_mubi
107                             $error("%m: Invalid width for MuBi");
108                           end
109                         end else begin : gen_non_mubi
110        1/1                assign wr_data = (de ? d : q) & (we ? ~wd : '1);
           Tests:       T43 T44 T45 
Cond Coverage for Instance : tb.dut.u_reg.u_intr_state.wr_en_data_arb
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       88
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT43,T44,T45
01CoveredT31,T38,T39
10CoveredT31,T39,T48
Line Coverage for Instance : tb.dut.u_reg.u_intr_enable.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3900


32                        if (SwAccess inside {SwAccessRW, SwAccessWO}) begin : gen_w
33         1/1              assign wr_en   = we | de;
           Tests:       T31 T38 T39 
34         1/1              assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
           Tests:       T43 T44 T45 
35                          // Unused q - Prevent lint errors.
36                          logic [DW-1:0] unused_q;
37                          //VCS coverage off
38                          // pragma coverage off
39         unreachable      assign unused_q = q;
Cond Coverage for Instance : tb.dut.u_reg.u_intr_enable.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT43,T44,T45
01Unreachable
10CoveredT31,T38,T39 

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT43,T44,T45
1CoveredT31,T38,T39 

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT43,T44,T45
1CoveredT31,T38,T39
Branch Coverage for Instance : tb.dut.u_reg.u_intr_enable.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 34 2 2 100.00 



34             assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
                                             -1-  
                                             ==>  
                                             ==>

Branches:
-1-StatusTests
1 Covered T31,T38,T39
0 Covered T43,T44,T45

Line Coverage for Instance : tb.dut.u_reg.u_intr_ctrl_en_rising.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3900


32                        if (SwAccess inside {SwAccessRW, SwAccessWO}) begin : gen_w
33         1/1              assign wr_en   = we | de;
           Tests:       T31 T38 T39 
34         1/1              assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
           Tests:       T43 T44 T45 
35                          // Unused q - Prevent lint errors.
36                          logic [DW-1:0] unused_q;
37                          //VCS coverage off
38                          // pragma coverage off
39         unreachable      assign unused_q = q;
Cond Coverage for Instance : tb.dut.u_reg.u_intr_ctrl_en_rising.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT43,T44,T45
01Unreachable
10CoveredT31,T38,T39 

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT43,T44,T45
1CoveredT31,T38,T39 

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT43,T44,T45
1CoveredT31,T38,T39
Branch Coverage for Instance : tb.dut.u_reg.u_intr_ctrl_en_rising.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 34 2 2 100.00 



34             assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
                                             -1-  
                                             ==>  
                                             ==>

Branches:
-1-StatusTests
1 Covered T31,T38,T39
0 Covered T43,T44,T45

Line Coverage for Instance : tb.dut.u_reg.u_intr_ctrl_en_falling.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3900


32                        if (SwAccess inside {SwAccessRW, SwAccessWO}) begin : gen_w
33         1/1              assign wr_en   = we | de;
           Tests:       T31 T38 T39 
34         1/1              assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
           Tests:       T43 T44 T45 
35                          // Unused q - Prevent lint errors.
36                          logic [DW-1:0] unused_q;
37                          //VCS coverage off
38                          // pragma coverage off
39         unreachable      assign unused_q = q;
Cond Coverage for Instance : tb.dut.u_reg.u_intr_ctrl_en_falling.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT43,T44,T45
01Unreachable
10CoveredT31,T38,T39 

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT43,T44,T45
1CoveredT31,T38,T39 

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT43,T44,T45
1CoveredT31,T38,T39
Branch Coverage for Instance : tb.dut.u_reg.u_intr_ctrl_en_falling.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 34 2 2 100.00 



34             assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
                                             -1-  
                                             ==>  
                                             ==>

Branches:
-1-StatusTests
1 Covered T31,T38,T39
0 Covered T43,T44,T45

Line Coverage for Instance : tb.dut.u_reg.u_intr_ctrl_en_lvlhigh.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3900


32                        if (SwAccess inside {SwAccessRW, SwAccessWO}) begin : gen_w
33         1/1              assign wr_en   = we | de;
           Tests:       T31 T38 T39 
34         1/1              assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
           Tests:       T43 T44 T45 
35                          // Unused q - Prevent lint errors.
36                          logic [DW-1:0] unused_q;
37                          //VCS coverage off
38                          // pragma coverage off
39         unreachable      assign unused_q = q;
Cond Coverage for Instance : tb.dut.u_reg.u_intr_ctrl_en_lvlhigh.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT43,T44,T45
01Unreachable
10CoveredT31,T38,T39 

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT43,T44,T45
1CoveredT31,T38,T39 

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT43,T44,T45
1CoveredT31,T38,T39
Branch Coverage for Instance : tb.dut.u_reg.u_intr_ctrl_en_lvlhigh.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 34 2 2 100.00 



34             assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
                                             -1-  
                                             ==>  
                                             ==>

Branches:
-1-StatusTests
1 Covered T31,T38,T39
0 Covered T43,T44,T45

Line Coverage for Instance : tb.dut.u_reg.u_intr_ctrl_en_lvllow.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3900


32                        if (SwAccess inside {SwAccessRW, SwAccessWO}) begin : gen_w
33         1/1              assign wr_en   = we | de;
           Tests:       T31 T38 T39 
34         1/1              assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
           Tests:       T43 T44 T45 
35                          // Unused q - Prevent lint errors.
36                          logic [DW-1:0] unused_q;
37                          //VCS coverage off
38                          // pragma coverage off
39         unreachable      assign unused_q = q;
Cond Coverage for Instance : tb.dut.u_reg.u_intr_ctrl_en_lvllow.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT43,T44,T45
01Unreachable
10CoveredT31,T38,T39 

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT43,T44,T45
1CoveredT31,T38,T39 

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT43,T44,T45
1CoveredT31,T38,T39
Branch Coverage for Instance : tb.dut.u_reg.u_intr_ctrl_en_lvllow.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 34 2 2 100.00 



34             assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
                                             -1-  
                                             ==>  
                                             ==>

Branches:
-1-StatusTests
1 Covered T31,T38,T39
0 Covered T43,T44,T45

Line Coverage for Instance : tb.dut.u_reg.u_ctrl_en_input_filter.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3900


32                        if (SwAccess inside {SwAccessRW, SwAccessWO}) begin : gen_w
33         1/1              assign wr_en   = we | de;
           Tests:       T31 T49 T48 
34         1/1              assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
           Tests:       T43 T44 T45 
35                          // Unused q - Prevent lint errors.
36                          logic [DW-1:0] unused_q;
37                          //VCS coverage off
38                          // pragma coverage off
39         unreachable      assign unused_q = q;
Cond Coverage for Instance : tb.dut.u_reg.u_ctrl_en_input_filter.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT43,T44,T45
01Unreachable
10CoveredT31,T49,T48 

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT43,T44,T45
1CoveredT31,T49,T48 

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT43,T44,T45
1CoveredT31,T49,T48
Branch Coverage for Instance : tb.dut.u_reg.u_ctrl_en_input_filter.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 34 2 2 100.00 



34             assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
                                             -1-  
                                             ==>  
                                             ==>

Branches:
-1-StatusTests
1 Covered T31,T49,T48
0 Covered T43,T44,T45

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%