Unified Coverage Report :: Module :: gpio_csr_assert_fpv

Module : gpio_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/gpio-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_gpio_csr_assert_0/gpio_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gpio_csr_assert	85.71						85.71

---

Module Instance : tb.dut.gpio_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : gpio_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	6	85.71
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	6	85.71

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	55868486	0	0	0
ctrl_en_input_filter_rd_A	55868486	86440	0	0
intr_ctrl_en_falling_rd_A	55868486	87115	0	0
intr_ctrl_en_lvlhigh_rd_A	55868486	84737	0	0
intr_ctrl_en_lvllow_rd_A	55868486	85258	0	0
intr_ctrl_en_rising_rd_A	55868486	85485	0	0
intr_enable_rd_A	55868486	86628	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55868486	0	0	0

ctrl_en_input_filter_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55868486	86440	0	0
T1	13183	48	0	0
T2	0	209	0	0
T3	0	398	0	0
T4	0	244	0	0
T5	0	944	0	0
T6	0	31	0	0
T7	0	1312	0	0
T8	0	5	0	0
T9	0	196	0	0
T10	0	43	0	0
T11	1223	0	0	0
T12	30352	0	0	0
T13	15907	0	0	0
T14	2345	0	0	0
T15	3233	0	0	0
T16	2621	0	0	0
T17	941	0	0	0
T18	3510	0	0	0
T19	2224	0	0	0

intr_ctrl_en_falling_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55868486	87115	0	0
T1	13183	197	0	0
T2	0	159	0	0
T3	0	391	0	0
T4	0	262	0	0
T5	0	878	0	0
T11	1223	0	0	0
T12	30352	0	0	0
T13	15907	0	0	0
T14	2345	0	0	0
T15	3233	0	0	0
T16	2621	0	0	0
T17	941	0	0	0
T18	3510	0	0	0
T19	2224	10	0	0
T20	0	5	0	0
T21	0	1	0	0
T22	0	5	0	0
T23	0	7	0	0

intr_ctrl_en_lvlhigh_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55868486	84737	0	0
T1	13183	121	0	0
T2	0	145	0	0
T3	0	448	0	0
T4	0	298	0	0
T5	0	912	0	0
T6	0	25	0	0
T7	0	1395	0	0
T11	1223	0	0	0
T12	30352	0	0	0
T13	15907	0	0	0
T14	2345	0	0	0
T15	3233	0	0	0
T16	2621	0	0	0
T17	941	0	0	0
T18	3510	0	0	0
T19	2224	0	0	0
T22	0	11	0	0
T23	0	1	0	0
T24	0	6	0	0

intr_ctrl_en_lvllow_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55868486	85258	0	0
T1	13183	106	0	0
T2	0	157	0	0
T3	0	419	0	0
T4	0	276	0	0
T5	0	901	0	0
T6	0	21	0	0
T7	0	1345	0	0
T11	1223	0	0	0
T12	30352	0	0	0
T13	15907	0	0	0
T14	2345	0	0	0
T15	3233	0	0	0
T16	2621	0	0	0
T17	941	0	0	0
T18	3510	0	0	0
T19	2224	0	0	0
T21	0	7	0	0
T23	0	3	0	0
T24	0	1	0	0

intr_ctrl_en_rising_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55868486	85485	0	0
T1	13183	129	0	0
T2	0	156	0	0
T3	0	407	0	0
T4	0	284	0	0
T5	0	915	0	0
T6	0	43	0	0
T7	0	1409	0	0
T8	0	2	0	0
T11	1223	0	0	0
T12	30352	0	0	0
T13	15907	0	0	0
T14	2345	0	0	0
T15	3233	0	0	0
T16	2621	0	0	0
T17	941	0	0	0
T18	3510	0	0	0
T19	2224	0	0	0
T22	0	4	0	0
T24	0	3	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55868486	86628	0	0
T1	13183	86	0	0
T2	0	169	0	0
T3	0	446	0	0
T4	0	282	0	0
T5	0	906	0	0
T6	0	9	0	0
T11	1223	0	0	0
T12	30352	0	0	0
T13	15907	0	0	0
T14	2345	0	0	0
T15	3233	0	0	0
T16	2621	0	0	0
T17	941	0	0	0
T18	3510	0	0	0
T19	2224	0	0	0
T20	0	2	0	0
T21	0	4	0	0
T22	0	13	0	0
T23	0	1	0	0