Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	32	0	32	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	128	0	128	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	11407897	1			T41	259		T42	306		T43	55
all_values[1]	11407897	1			T41	259		T42	306		T43	55
all_values[2]	11407897	1			T41	259		T42	306		T43	55
all_values[3]	11407897	1			T41	259		T42	306		T43	55
all_values[4]	11407897	1			T41	259		T42	306		T43	55
all_values[5]	11407897	1			T41	259		T42	306		T43	55
all_values[6]	11407897	1			T41	259		T42	306		T43	55
all_values[7]	11407897	1			T41	259		T42	306		T43	55
all_values[8]	11407897	1			T41	259		T42	306		T43	55
all_values[9]	11407897	1			T41	259		T42	306		T43	55
all_values[10]	11407897	1			T41	259		T42	306		T43	55
all_values[11]	11407897	1			T41	259		T42	306		T43	55
all_values[12]	11407897	1			T41	259		T42	306		T43	55
all_values[13]	11407897	1			T41	259		T42	306		T43	55
all_values[14]	11407897	1			T41	259		T42	306		T43	55
all_values[15]	11407897	1			T41	259		T42	306		T43	55
all_values[16]	11407897	1			T41	259		T42	306		T43	55
all_values[17]	11407897	1			T41	259		T42	306		T43	55
all_values[18]	11407897	1			T41	259		T42	306		T43	55
all_values[19]	11407897	1			T41	259		T42	306		T43	55
all_values[20]	11407897	1			T41	259		T42	306		T43	55
all_values[21]	11407897	1			T41	259		T42	306		T43	55
all_values[22]	11407897	1			T41	259		T42	306		T43	55
all_values[23]	11407897	1			T41	259		T42	306		T43	55
all_values[24]	11407897	1			T41	259		T42	306		T43	55
all_values[25]	11407897	1			T41	259		T42	306		T43	55
all_values[26]	11407897	1			T41	259		T42	306		T43	55
all_values[27]	11407897	1			T41	259		T42	306		T43	55
all_values[28]	11407897	1			T41	259		T42	306		T43	55
all_values[29]	11407897	1			T41	259		T42	306		T43	55
all_values[30]	11407897	1			T41	259		T42	306		T43	55
all_values[31]	11407897	1			T41	259		T42	306		T43	55

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

215512931

1

T41

8288

T42

9792

T43

1760

auto[1]

149539773

1

T46

863

T47

2432

T51

39210

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

94929144

1

T41

8288

T42

9792

T43

1760

auto[1]

270123560

1

T46

1273

T47

3861

T51

72595

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2512197	1			T41	259		T42	306		T43	55
all_values[0]	auto[0]	auto[1]	4214045	1			T46	21		T47	94		T51	1225
all_values[0]	auto[1]	auto[0]	451197	1			T46	7		T47	3		T51	95
all_values[0]	auto[1]	auto[1]	4230458	1			T46	16		T47	18		T51	1157
all_values[1]	auto[0]	auto[0]	2512014	1			T41	259		T42	306		T43	55
all_values[1]	auto[0]	auto[1]	4269781	1			T46	20		T47	26		T51	1079
all_values[1]	auto[1]	auto[0]	457859	1			T46	7		T47	17		T51	122
all_values[1]	auto[1]	auto[1]	4168243	1			T46	8		T47	98		T51	1181
all_values[2]	auto[0]	auto[0]	2523547	1			T41	259		T42	306		T43	55
all_values[2]	auto[0]	auto[1]	4238637	1			T46	18		T47	27		T51	929
all_values[2]	auto[1]	auto[0]	454122	1			T46	16		T47	1		T51	118
all_values[2]	auto[1]	auto[1]	4191591	1			T46	27		T47	108		T51	1381
all_values[3]	auto[0]	auto[0]	2507028	1			T41	259		T42	306		T43	55
all_values[3]	auto[0]	auto[1]	4206780	1			T46	43		T47	52		T51	1076
all_values[3]	auto[1]	auto[0]	458097	1			T46	17		T47	17		T51	94
all_values[3]	auto[1]	auto[1]	4235992	1			T46	7		T47	48		T51	1187
all_values[4]	auto[0]	auto[0]	2509490	1			T41	259		T42	306		T43	55
all_values[4]	auto[0]	auto[1]	4217979	1			T46	26		T47	68		T51	1083
all_values[4]	auto[1]	auto[0]	449633	1			T46	10		T47	5		T51	134
all_values[4]	auto[1]	auto[1]	4230795	1			T46	14		T47	59		T51	1099
all_values[5]	auto[0]	auto[0]	2506748	1			T41	259		T42	306		T43	55
all_values[5]	auto[0]	auto[1]	4231190	1			T46	35		T47	98		T51	1286
all_values[5]	auto[1]	auto[0]	453351	1			T46	17		T47	12		T51	97
all_values[5]	auto[1]	auto[1]	4216608	1			T46	8		T47	27		T51	1038
all_values[6]	auto[0]	auto[0]	2503489	1			T41	259		T42	306		T43	55
all_values[6]	auto[0]	auto[1]	4195948	1			T46	23		T47	63		T51	1269
all_values[6]	auto[1]	auto[0]	455218	1			T46	26		T47	20		T51	124
all_values[6]	auto[1]	auto[1]	4253242	1			T46	13		T47	59		T51	964
all_values[7]	auto[0]	auto[0]	2512167	1			T41	259		T42	306		T43	55
all_values[7]	auto[0]	auto[1]	4227618	1			T46	24		T47	74		T51	1234
all_values[7]	auto[1]	auto[0]	455463	1			T46	13		T47	5		T51	78
all_values[7]	auto[1]	auto[1]	4212649	1			T46	11		T47	54		T51	1142
all_values[8]	auto[0]	auto[0]	2512584	1			T41	259		T42	306		T43	55
all_values[8]	auto[0]	auto[1]	4234146	1			T46	20		T47	99		T51	1200
all_values[8]	auto[1]	auto[0]	450750	1			T46	9		T47	4		T51	111
all_values[8]	auto[1]	auto[1]	4210417	1			T46	5		T47	36		T51	1076
all_values[9]	auto[0]	auto[0]	2509393	1			T41	259		T42	306		T43	55
all_values[9]	auto[0]	auto[1]	4228112	1			T46	22		T47	37		T51	1068
all_values[9]	auto[1]	auto[0]	460774	1			T46	16		T47	21		T51	178
all_values[9]	auto[1]	auto[1]	4209618	1			T46	7		T47	83		T51	1119
all_values[10]	auto[0]	auto[0]	2520891	1			T41	259		T42	306		T43	55
all_values[10]	auto[0]	auto[1]	4239478	1			T46	17		T47	43		T51	1211
all_values[10]	auto[1]	auto[0]	456936	1			T46	36		T47	10		T51	74
all_values[10]	auto[1]	auto[1]	4190592	1			T46	13		T47	88		T51	1109
all_values[11]	auto[0]	auto[0]	2507031	1			T41	259		T42	306		T43	55
all_values[11]	auto[0]	auto[1]	4197317	1			T46	28		T47	21		T51	1341
all_values[11]	auto[1]	auto[0]	451548	1			T46	13		T47	9		T51	115
all_values[11]	auto[1]	auto[1]	4252001	1			T46	26		T47	108		T51	877
all_values[12]	auto[0]	auto[0]	2510167	1			T41	259		T42	306		T43	55
all_values[12]	auto[0]	auto[1]	4218826	1			T46	23		T47	88		T51	724
all_values[12]	auto[1]	auto[0]	455711	1			T46	20		T47	9		T51	159
all_values[12]	auto[1]	auto[1]	4223193	1			T46	9		T47	40		T51	1459
all_values[13]	auto[0]	auto[0]	2510073	1			T41	259		T42	306		T43	55
all_values[13]	auto[0]	auto[1]	4223948	1			T46	22		T47	8		T51	1235
all_values[13]	auto[1]	auto[0]	458386	1			T46	13		T47	5		T51	99
all_values[13]	auto[1]	auto[1]	4215490	1			T46	20		T47	129		T51	1062
all_values[14]	auto[0]	auto[0]	2506151	1			T41	259		T42	306		T43	55
all_values[14]	auto[0]	auto[1]	4250772	1			T46	32		T47	69		T51	1210
all_values[14]	auto[1]	auto[0]	458180	1			T46	6		T47	7		T51	146
all_values[14]	auto[1]	auto[1]	4192794	1			T46	15		T47	53		T51	1015
all_values[15]	auto[0]	auto[0]	2507700	1			T41	259		T42	306		T43	55
all_values[15]	auto[0]	auto[1]	4221810	1			T46	36		T47	15		T51	1348
all_values[15]	auto[1]	auto[0]	457276	1			T46	14		T47	18		T51	149
all_values[15]	auto[1]	auto[1]	4221111	1			T46	4		T47	100		T51	893
all_values[16]	auto[0]	auto[0]	2514937	1			T41	259		T42	306		T43	55
all_values[16]	auto[0]	auto[1]	4212185	1			T46	24		T47	66		T51	1325
all_values[16]	auto[1]	auto[0]	465782	1			T46	10		T47	2		T51	108
all_values[16]	auto[1]	auto[1]	4214993	1			T46	6		T47	68		T51	939
all_values[17]	auto[0]	auto[0]	2507282	1			T41	259		T42	306		T43	55
all_values[17]	auto[0]	auto[1]	4235779	1			T46	21		T47	66		T51	1173
all_values[17]	auto[1]	auto[0]	454086	1			T46	13		T47	12		T51	149
all_values[17]	auto[1]	auto[1]	4210750	1			T46	12		T47	52		T51	1015
all_values[18]	auto[0]	auto[0]	2505207	1			T41	259		T42	306		T43	55
all_values[18]	auto[0]	auto[1]	4233916	1			T46	26		T47	34		T51	1272
all_values[18]	auto[1]	auto[0]	458011	1			T46	13		T47	14		T51	90
all_values[18]	auto[1]	auto[1]	4210763	1			T46	6		T47	84		T51	1060
all_values[19]	auto[0]	auto[0]	2502343	1			T41	259		T42	306		T43	55
all_values[19]	auto[0]	auto[1]	4221174	1			T46	42		T47	76		T51	1081
all_values[19]	auto[1]	auto[0]	458184	1			T46	8		T47	21		T51	156
all_values[19]	auto[1]	auto[1]	4226196	1			T46	5		T47	31		T51	1197
all_values[20]	auto[0]	auto[0]	2508121	1			T41	259		T42	306		T43	55
all_values[20]	auto[0]	auto[1]	4214224	1			T46	42		T47	50		T51	1269
all_values[20]	auto[1]	auto[0]	455734	1			T46	14		T47	14		T51	53
all_values[20]	auto[1]	auto[1]	4229818	1			T46	6		T47	61		T51	1081
all_values[21]	auto[0]	auto[0]	2510796	1			T41	259		T42	306		T43	55
all_values[21]	auto[0]	auto[1]	4207010	1			T46	44		T47	116		T51	1293
all_values[21]	auto[1]	auto[0]	456615	1			T46	11		T51	164		T64	5
all_values[21]	auto[1]	auto[1]	4233476	1			T46	13		T47	19		T51	925
all_values[22]	auto[0]	auto[0]	2508776	1			T41	259		T42	306		T43	55
all_values[22]	auto[0]	auto[1]	4228371	1			T46	25		T47	39		T51	1070
all_values[22]	auto[1]	auto[0]	460142	1			T46	15		T47	24		T51	122
all_values[22]	auto[1]	auto[1]	4210608	1			T46	33		T47	77		T51	1172
all_values[23]	auto[0]	auto[0]	2503968	1			T41	259		T42	306		T43	55
all_values[23]	auto[0]	auto[1]	4235366	1			T46	26		T47	37		T51	1219
all_values[23]	auto[1]	auto[0]	457433	1			T46	8		T47	21		T51	153
all_values[23]	auto[1]	auto[1]	4211130	1			T46	20		T47	78		T51	1020
all_values[24]	auto[0]	auto[0]	2507404	1			T41	259		T42	306		T43	55
all_values[24]	auto[0]	auto[1]	4210586	1			T46	22		T47	48		T51	1006
all_values[24]	auto[1]	auto[0]	457713	1			T46	21		T47	14		T51	90
all_values[24]	auto[1]	auto[1]	4232194	1			T46	18		T47	79		T51	1327
all_values[25]	auto[0]	auto[0]	2509419	1			T41	259		T42	306		T43	55
all_values[25]	auto[0]	auto[1]	4206714	1			T46	24		T47	69		T51	1095
all_values[25]	auto[1]	auto[0]	456947	1			T46	14		T47	23		T51	133
all_values[25]	auto[1]	auto[1]	4234817	1			T46	16		T47	26		T51	1234
all_values[26]	auto[0]	auto[0]	2512790	1			T41	259		T42	306		T43	55
all_values[26]	auto[0]	auto[1]	4238204	1			T46	38		T47	57		T51	1213
all_values[26]	auto[1]	auto[0]	453022	1			T46	17		T47	25		T51	106
all_values[26]	auto[1]	auto[1]	4203881	1			T46	11		T47	57		T51	1064
all_values[27]	auto[0]	auto[0]	2514049	1			T41	259		T42	306		T43	55
all_values[27]	auto[0]	auto[1]	4254723	1			T46	13		T47	18		T51	981
all_values[27]	auto[1]	auto[0]	459434	1			T46	14		T47	11		T51	85
all_values[27]	auto[1]	auto[1]	4179691	1			T46	11		T47	104		T51	1278
all_values[28]	auto[0]	auto[0]	2510865	1			T41	259		T42	306		T43	55
all_values[28]	auto[0]	auto[1]	4203765	1			T46	21		T47	108		T51	987
all_values[28]	auto[1]	auto[0]	458256	1			T46	21		T47	3		T51	146
all_values[28]	auto[1]	auto[1]	4235011	1			T46	21		T47	15		T51	1290
all_values[29]	auto[0]	auto[0]	2517013	1			T41	259		T42	306		T43	55
all_values[29]	auto[0]	auto[1]	4229631	1			T46	28		T47	29		T51	1178
all_values[29]	auto[1]	auto[0]	458023	1			T46	8		T47	43		T51	73
all_values[29]	auto[1]	auto[1]	4203230	1			T46	13		T47	68		T51	1126
all_values[30]	auto[0]	auto[0]	2507145	1			T41	259		T42	306		T43	55
all_values[30]	auto[0]	auto[1]	4215302	1			T46	31		T47	69		T51	1262
all_values[30]	auto[1]	auto[0]	456539	1			T46	11		T47	8		T51	131
all_values[30]	auto[1]	auto[1]	4228911	1			T46	4		T47	33		T51	905
all_values[31]	auto[0]	auto[0]	2513050	1			T41	259		T42	306		T43	55
all_values[31]	auto[0]	auto[1]	4225759	1			T46	18		T47	63		T51	1217
all_values[31]	auto[1]	auto[0]	454887	1			T46	7		T51	122		T64	25
all_values[31]	auto[1]	auto[1]	4214201	1			T46	20		T47	74		T51	1044