Design Module List
dashboard | hierarchy | modlist | groups | tests | asserts
Total Module Definition Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.76 99.76 100.00 100.00 100.00 99.04


Total modules in report: 25
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gpio_csr_assert_fpv 85.71 85.71
prim_onehot_check 85.71 100.00 71.43
prim_subreg_arb 96.30 88.89 100.00 100.00
prim_subreg_arb 100.00 100.00 100.00
prim_subreg_arb ( parameter DW=32,SwAccess=0 ) 100.00 100.00
prim_subreg_arb ( parameter DW=32,SwAccess=1 ) 66.67 66.67
prim_subreg_arb ( parameter DW=32,SwAccess=3 ) 100.00 100.00
prim_filter_ctr 100.00 100.00 100.00 100.00
gpio 100.00 100.00 100.00 100.00 100.00
tlul_data_integ_dec 100.00 100.00
tlul_cmd_intg_chk 100.00 100.00 100.00
prim_alert_sender 100.00 100.00
tlul_rsp_intg_gen 100.00 100.00 100.00
tlul_assert 100.00 100.00 100.00 100.00
prim_subreg 100.00 100.00 100.00 100.00
gpio_reg_top 100.00 100.00 100.00 100.00 100.00
prim_secded_inv_39_32_dec 100.00 100.00
prim_generic_buf 100.00 100.00
prim_intr_hw 100.00 100.00 100.00
tlul_adapter_reg 100.00 100.00 100.00 100.00 100.00
prim_subreg_ext 100.00 100.00
prim_secded_inv_39_32_enc 100.00 100.00
tlul_err 100.00 100.00 100.00 100.00 100.00
prim_secded_inv_64_57_enc 100.00 100.00
prim_secded_inv_64_57_dec 100.00 100.00
tlul_data_integ_enc
prim_reg_we_check
prim_buf
tb
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