dashboard | hierarchy | modlist | groups | tests | asserts

Group Instance : masked_out_upper_mask_data_cov_obj_pin3
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance masked_out_upper_mask_data_cov_obj_pin3

CATEGORY   EXPECTED   UNCOVERED   COVERED   PERCENT   
Variables 4 0 4 100.00
Crosses 4 0 4 100.00


Variables for Group Instance masked_out_upper_mask_data_cov_obj_pin3
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
cp_var1 2 0 2 100.00 100 1 1 2
cp_var2 2 0 2 100.00 100 1 1 2


Crosses for Group Instance masked_out_upper_mask_data_cov_obj_pin3
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cp_var1_var2_cross 4 0 4 100.00 100 1 1 0



Group Instance : masked_out_upper_mask_data_cov_obj_pin4
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance masked_out_upper_mask_data_cov_obj_pin4

CATEGORY   EXPECTED   UNCOVERED   COVERED   PERCENT   
Variables 4 0 4 100.00
Crosses 4 0 4 100.00


Variables for Group Instance masked_out_upper_mask_data_cov_obj_pin4
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
cp_var1 2 0 2 100.00 100 1 1 2
cp_var2 2 0 2 100.00 100 1 1 2


Crosses for Group Instance masked_out_upper_mask_data_cov_obj_pin4
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cp_var1_var2_cross 4 0 4 100.00 100 1 1 0



Group Instance : masked_out_upper_mask_data_cov_obj_pin5
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance masked_out_upper_mask_data_cov_obj_pin5

CATEGORY   EXPECTED   UNCOVERED   COVERED   PERCENT   
Variables 4 0 4 100.00
Crosses 4 0 4 100.00


Variables for Group Instance masked_out_upper_mask_data_cov_obj_pin5
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
cp_var1 2 0 2 100.00 100 1 1 2
cp_var2 2 0 2 100.00 100 1 1 2


Crosses for Group Instance masked_out_upper_mask_data_cov_obj_pin5
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cp_var1_var2_cross 4 0 4 100.00 100 1 1 0



Group Instance : masked_out_upper_mask_data_cov_obj_pin6
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance masked_out_upper_mask_data_cov_obj_pin6

CATEGORY   EXPECTED   UNCOVERED   COVERED   PERCENT   
Variables 4 0 4 100.00
Crosses 4 0 4 100.00


Variables for Group Instance masked_out_upper_mask_data_cov_obj_pin6
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
cp_var1 2 0 2 100.00 100 1 1 2
cp_var2 2 0 2 100.00 100 1 1 2


Crosses for Group Instance masked_out_upper_mask_data_cov_obj_pin6
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cp_var1_var2_cross 4 0 4 100.00 100 1 1 0



Group Instance : masked_out_upper_mask_data_cov_obj_pin7
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance masked_out_upper_mask_data_cov_obj_pin7

CATEGORY   EXPECTED   UNCOVERED   COVERED   PERCENT   
Variables 4 0 4 100.00
Crosses 4 0 4 100.00


Variables for Group Instance masked_out_upper_mask_data_cov_obj_pin7
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
cp_var1 2 0 2 100.00 100 1 1 2
cp_var2 2 0 2 100.00 100 1 1 2


Crosses for Group Instance masked_out_upper_mask_data_cov_obj_pin7
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cp_var1_var2_cross 4 0 4 100.00 100 1 1 0



Group Instance : masked_out_upper_mask_data_cov_obj_pin8
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance masked_out_upper_mask_data_cov_obj_pin8

CATEGORY   EXPECTED   UNCOVERED   COVERED   PERCENT   
Variables 4 0 4 100.00
Crosses 4 0 4 100.00


Variables for Group Instance masked_out_upper_mask_data_cov_obj_pin8
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
cp_var1 2 0 2 100.00 100 1 1 2
cp_var2 2 0 2 100.00 100 1 1 2


Crosses for Group Instance masked_out_upper_mask_data_cov_obj_pin8
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cp_var1_var2_cross 4 0 4 100.00 100 1 1 0



Group Instance : masked_out_upper_mask_data_cov_obj_pin9
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance masked_out_upper_mask_data_cov_obj_pin9

CATEGORY   EXPECTED   UNCOVERED   COVERED   PERCENT   
Variables 4 0 4 100.00
Crosses 4 0 4 100.00


Variables for Group Instance masked_out_upper_mask_data_cov_obj_pin9
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
cp_var1 2 0 2 100.00 100 1 1 2
cp_var2 2 0 2 100.00 100 1 1 2


Crosses for Group Instance masked_out_upper_mask_data_cov_obj_pin9
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cp_var1_var2_cross 4 0 4 100.00 100 1 1 0

Go back
Group Instances:
masked_out_upper_mask_data_cov_obj_pin3
masked_out_upper_mask_data_cov_obj_pin4
masked_out_upper_mask_data_cov_obj_pin5
masked_out_upper_mask_data_cov_obj_pin6
masked_out_upper_mask_data_cov_obj_pin7
masked_out_upper_mask_data_cov_obj_pin8
masked_out_upper_mask_data_cov_obj_pin9

Summary for Variable cp_var1

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var1

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 162952 1 T44 2 T45 7 T46 7
auto[1] 163746 1 T43 3 T44 3 T45 5



Summary for Variable cp_var2

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var2

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 163112 1 T43 1 T44 4 T45 8
auto[1] 163586 1 T43 2 T44 1 T45 4



Summary for Cross cp_var1_var2_cross

Samples crossed: cp_var1 cp_var2
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cp_var1_var2_cross

Bins
cp_var1   cp_var2   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] auto[0] 81666 1 T44 1 T45 3 T46 4
auto[0] auto[1] 81286 1 T44 1 T45 4 T46 3
auto[1] auto[0] 81446 1 T43 1 T44 3 T45 5
auto[1] auto[1] 82300 1 T43 2 T46 6 T50 2


Summary for Variable cp_var1

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var1

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 163869 1 T43 2 T44 3 T45 7
auto[1] 162829 1 T43 1 T44 2 T45 5



Summary for Variable cp_var2

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var2

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 163581 1 T43 1 T44 2 T45 4
auto[1] 163117 1 T43 2 T44 3 T45 8



Summary for Cross cp_var1_var2_cross

Samples crossed: cp_var1 cp_var2
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cp_var1_var2_cross

Bins
cp_var1   cp_var2   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] auto[0] 81808 1 T43 1 T44 1 T45 4
auto[0] auto[1] 82061 1 T43 1 T44 2 T45 3
auto[1] auto[0] 81773 1 T44 1 T46 3 T50 4
auto[1] auto[1] 81056 1 T43 1 T44 1 T45 5


Summary for Variable cp_var1

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var1

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 163206 1 T43 2 T44 2 T45 6
auto[1] 163492 1 T43 1 T44 3 T45 6



Summary for Variable cp_var2

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var2

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 163403 1 T43 1 T45 7 T46 9
auto[1] 163295 1 T43 2 T44 5 T45 5



Summary for Cross cp_var1_var2_cross

Samples crossed: cp_var1 cp_var2
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cp_var1_var2_cross

Bins
cp_var1   cp_var2   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] auto[0] 81519 1 T43 1 T45 3 T46 6
auto[0] auto[1] 81687 1 T43 1 T44 2 T45 3
auto[1] auto[0] 81884 1 T45 4 T46 3 T50 2
auto[1] auto[1] 81608 1 T43 1 T44 3 T45 2


Summary for Variable cp_var1

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var1

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 163345 1 T43 2 T44 3 T45 7
auto[1] 163353 1 T43 1 T44 2 T45 5



Summary for Variable cp_var2

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var2

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 163235 1 T43 2 T44 1 T45 5
auto[1] 163463 1 T43 1 T44 4 T45 7



Summary for Cross cp_var1_var2_cross

Samples crossed: cp_var1 cp_var2
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cp_var1_var2_cross

Bins
cp_var1   cp_var2   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] auto[0] 81766 1 T43 2 T45 2 T46 9
auto[0] auto[1] 81579 1 T44 3 T45 5 T46 3
auto[1] auto[0] 81469 1 T44 1 T45 3 T46 3
auto[1] auto[1] 81884 1 T43 1 T44 1 T45 2


Summary for Variable cp_var1

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var1

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 163424 1 T43 2 T44 1 T45 8
auto[1] 163274 1 T43 1 T44 4 T45 4



Summary for Variable cp_var2

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var2

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 163239 1 T43 1 T44 2 T45 6
auto[1] 163459 1 T43 2 T44 3 T45 6



Summary for Cross cp_var1_var2_cross

Samples crossed: cp_var1 cp_var2
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cp_var1_var2_cross

Bins
cp_var1   cp_var2   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] auto[0] 81727 1 T43 1 T44 1 T45 4
auto[0] auto[1] 81697 1 T43 1 T45 4 T46 5
auto[1] auto[0] 81512 1 T44 1 T45 2 T46 3
auto[1] auto[1] 81762 1 T43 1 T44 3 T45 2


Summary for Variable cp_var1

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var1

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 163391 1 T43 1 T44 1 T45 5
auto[1] 163307 1 T43 2 T44 4 T45 7



Summary for Variable cp_var2

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var2

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 162819 1 T43 2 T44 3 T45 7
auto[1] 163879 1 T43 1 T44 2 T45 5



Summary for Cross cp_var1_var2_cross

Samples crossed: cp_var1 cp_var2
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cp_var1_var2_cross

Bins
cp_var1   cp_var2   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] auto[0] 81519 1 T43 1 T45 4 T46 5
auto[0] auto[1] 81872 1 T44 1 T45 1 T46 6
auto[1] auto[0] 81300 1 T43 1 T44 3 T45 3
auto[1] auto[1] 82007 1 T43 1 T44 1 T45 4


Summary for Variable cp_var1

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var1

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 163443 1 T43 1 T44 3 T45 6
auto[1] 163255 1 T43 2 T44 2 T45 6



Summary for Variable cp_var2

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var2

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 163655 1 T43 2 T44 3 T45 7
auto[1] 163043 1 T43 1 T44 2 T45 5



Summary for Cross cp_var1_var2_cross

Samples crossed: cp_var1 cp_var2
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cp_var1_var2_cross

Bins
cp_var1   cp_var2   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] auto[0] 81784 1 T43 1 T44 2 T45 3
auto[0] auto[1] 81659 1 T44 1 T45 3 T46 6
auto[1] auto[0] 81871 1 T43 1 T44 1 T45 4
auto[1] auto[1] 81384 1 T43 1 T44 1 T45 2