Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	32	0	32	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	128	0	128	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	3332488	1			T41	1		T42	1		T43	1
all_pins[1]	3332488	1			T41	1		T42	1		T43	1
all_pins[2]	3332488	1			T41	1		T42	1		T43	1
all_pins[3]	3332488	1			T41	1		T42	1		T43	1
all_pins[4]	3332488	1			T41	1		T42	1		T43	1
all_pins[5]	3332488	1			T41	1		T42	1		T43	1
all_pins[6]	3332488	1			T41	1		T42	1		T43	1
all_pins[7]	3332488	1			T41	1		T42	1		T43	1
all_pins[8]	3332488	1			T41	1		T42	1		T43	1
all_pins[9]	3332488	1			T41	1		T42	1		T43	1
all_pins[10]	3332488	1			T41	1		T42	1		T43	1
all_pins[11]	3332488	1			T41	1		T42	1		T43	1
all_pins[12]	3332488	1			T41	1		T42	1		T43	1
all_pins[13]	3332488	1			T41	1		T42	1		T43	1
all_pins[14]	3332488	1			T41	1		T42	1		T43	1
all_pins[15]	3332488	1			T41	1		T42	1		T43	1
all_pins[16]	3332488	1			T41	1		T42	1		T43	1
all_pins[17]	3332488	1			T41	1		T42	1		T43	1
all_pins[18]	3332488	1			T41	1		T42	1		T43	1
all_pins[19]	3332488	1			T41	1		T42	1		T43	1
all_pins[20]	3332488	1			T41	1		T42	1		T43	1
all_pins[21]	3332488	1			T41	1		T42	1		T43	1
all_pins[22]	3332488	1			T41	1		T42	1		T43	1
all_pins[23]	3332488	1			T41	1		T42	1		T43	1
all_pins[24]	3332488	1			T41	1		T42	1		T43	1
all_pins[25]	3332488	1			T41	1		T42	1		T43	1
all_pins[26]	3332488	1			T41	1		T42	1		T43	1
all_pins[27]	3332488	1			T41	1		T42	1		T43	1
all_pins[28]	3332488	1			T41	1		T42	1		T43	1
all_pins[29]	3332488	1			T41	1		T42	1		T43	1
all_pins[30]	3332488	1			T41	1		T42	1		T43	1
all_pins[31]	3332488	1			T41	1		T42	1		T43	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	66268586	1			T41	32		T42	32		T43	32
values[0x1]	40371030	1			T46	307		T47	1076		T48	918
transitions[0x0=>0x1]	24201181	1			T46	229		T47	641		T48	471
transitions[0x1=>0x0]	24201022	1			T46	229		T47	640		T48	471

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2071047	1			T41	1		T42	1		T43	1
all_pins[0]	values[0x1]	1261441	1			T46	13		T47	8		T48	30
all_pins[0]	transitions[0x0=>0x1]	783218	1			T46	13		T47	5		T48	20
all_pins[0]	transitions[0x1=>0x0]	781494	1			T46	15		T47	32		T48	10
all_pins[1]	values[0x0]	2077562	1			T41	1		T42	1		T43	1
all_pins[1]	values[0x1]	1254926	1			T46	8		T47	50		T48	35
all_pins[1]	transitions[0x0=>0x1]	749429	1			T46	1		T47	47		T48	18
all_pins[1]	transitions[0x1=>0x0]	755944	1			T46	6		T47	5		T48	13
all_pins[2]	values[0x0]	2072416	1			T41	1		T42	1		T43	1
all_pins[2]	values[0x1]	1260072	1			T46	21		T47	58		T48	29
all_pins[2]	transitions[0x0=>0x1]	758467	1			T46	15		T47	24		T48	10
all_pins[2]	transitions[0x1=>0x0]	753321	1			T46	2		T47	16		T48	16
all_pins[3]	values[0x0]	2067475	1			T41	1		T42	1		T43	1
all_pins[3]	values[0x1]	1265013	1			T46	5		T47	21		T48	30
all_pins[3]	transitions[0x0=>0x1]	756597	1			T47	6		T48	14		T51	203
all_pins[3]	transitions[0x1=>0x0]	751656	1			T46	16		T47	43		T48	13
all_pins[4]	values[0x0]	2073121	1			T41	1		T42	1		T43	1
all_pins[4]	values[0x1]	1259367	1			T46	11		T47	30		T48	31
all_pins[4]	transitions[0x0=>0x1]	754025	1			T46	9		T47	25		T48	13
all_pins[4]	transitions[0x1=>0x0]	759671	1			T46	3		T47	16		T48	12
all_pins[5]	values[0x0]	2068195	1			T41	1		T42	1		T43	1
all_pins[5]	values[0x1]	1264293	1			T46	7		T47	13		T48	29
all_pins[5]	transitions[0x0=>0x1]	758884	1			T46	4		T47	9		T48	11
all_pins[5]	transitions[0x1=>0x0]	753958	1			T46	8		T47	26		T48	13
all_pins[6]	values[0x0]	2067120	1			T41	1		T42	1		T43	1
all_pins[6]	values[0x1]	1265368	1			T46	9		T47	31		T48	30
all_pins[6]	transitions[0x0=>0x1]	755425	1			T46	8		T47	24		T48	15
all_pins[6]	transitions[0x1=>0x0]	754350	1			T46	6		T47	6		T48	14
all_pins[7]	values[0x0]	2071672	1			T41	1		T42	1		T43	1
all_pins[7]	values[0x1]	1260816	1			T46	9		T47	33		T48	28
all_pins[7]	transitions[0x0=>0x1]	755076	1			T46	8		T47	22		T48	16
all_pins[7]	transitions[0x1=>0x0]	759628	1			T46	8		T47	20		T48	18
all_pins[8]	values[0x0]	2071944	1			T41	1		T42	1		T43	1
all_pins[8]	values[0x1]	1260544	1			T46	5		T47	23		T48	33
all_pins[8]	transitions[0x0=>0x1]	752702	1			T46	5		T47	14		T48	20
all_pins[8]	transitions[0x1=>0x0]	752974	1			T46	9		T47	24		T48	15
all_pins[9]	values[0x0]	2066395	1			T41	1		T42	1		T43	1
all_pins[9]	values[0x1]	1266093	1			T46	5		T47	42		T48	26
all_pins[9]	transitions[0x0=>0x1]	759383	1			T46	4		T47	28		T48	11
all_pins[9]	transitions[0x1=>0x0]	753834	1			T46	4		T47	9		T48	18
all_pins[10]	values[0x0]	2075313	1			T41	1		T42	1		T43	1
all_pins[10]	values[0x1]	1257175	1			T46	13		T47	39		T48	31
all_pins[10]	transitions[0x0=>0x1]	751235	1			T46	10		T47	17		T48	16
all_pins[10]	transitions[0x1=>0x0]	760153	1			T46	2		T47	20		T48	11
all_pins[11]	values[0x0]	2066964	1			T41	1		T42	1		T43	1
all_pins[11]	values[0x1]	1265524	1			T46	18		T47	55		T48	29
all_pins[11]	transitions[0x0=>0x1]	759291	1			T46	17		T47	32		T48	16
all_pins[11]	transitions[0x1=>0x0]	750942	1			T46	12		T47	16		T48	18
all_pins[12]	values[0x0]	2075799	1			T41	1		T42	1		T43	1
all_pins[12]	values[0x1]	1256689	1			T46	5		T47	28		T48	35
all_pins[12]	transitions[0x0=>0x1]	750969	1			T46	3		T47	10		T48	19
all_pins[12]	transitions[0x1=>0x0]	759804	1			T46	16		T47	37		T48	13
all_pins[13]	values[0x0]	2066190	1			T41	1		T42	1		T43	1
all_pins[13]	values[0x1]	1266298	1			T46	12		T47	66		T48	26
all_pins[13]	transitions[0x0=>0x1]	760771	1			T46	10		T47	42		T48	8
all_pins[13]	transitions[0x1=>0x0]	751162	1			T46	3		T47	4		T48	17
all_pins[14]	values[0x0]	2074485	1			T41	1		T42	1		T43	1
all_pins[14]	values[0x1]	1258003	1			T46	10		T47	28		T48	23
all_pins[14]	transitions[0x0=>0x1]	750185	1			T46	5		T47	1		T48	13
all_pins[14]	transitions[0x1=>0x0]	758480	1			T46	7		T47	39		T48	16
all_pins[15]	values[0x0]	2068834	1			T41	1		T42	1		T43	1
all_pins[15]	values[0x1]	1263654	1			T46	3		T47	51		T48	25
all_pins[15]	transitions[0x0=>0x1]	756840	1			T46	3		T47	37		T48	17
all_pins[15]	transitions[0x1=>0x0]	751189	1			T46	10		T47	14		T48	15
all_pins[16]	values[0x0]	2071321	1			T41	1		T42	1		T43	1
all_pins[16]	values[0x1]	1261167	1			T46	4		T47	36		T48	22
all_pins[16]	transitions[0x0=>0x1]	754536	1			T46	4		T47	15		T48	15
all_pins[16]	transitions[0x1=>0x0]	757023	1			T46	3		T47	30		T48	18
all_pins[17]	values[0x0]	2072099	1			T41	1		T42	1		T43	1
all_pins[17]	values[0x1]	1260389	1			T46	6		T47	33		T48	19
all_pins[17]	transitions[0x0=>0x1]	755860	1			T46	6		T47	15		T48	13
all_pins[17]	transitions[0x1=>0x0]	756638	1			T46	4		T47	18		T48	16
all_pins[18]	values[0x0]	2072670	1			T41	1		T42	1		T43	1
all_pins[18]	values[0x1]	1259818	1			T46	6		T47	41		T48	40
all_pins[18]	transitions[0x0=>0x1]	754662	1			T46	5		T47	22		T48	28
all_pins[18]	transitions[0x1=>0x0]	755233	1			T46	5		T47	14		T48	7
all_pins[19]	values[0x0]	2066496	1			T41	1		T42	1		T43	1
all_pins[19]	values[0x1]	1265992	1			T46	6		T47	15		T48	32
all_pins[19]	transitions[0x0=>0x1]	760619	1			T46	4		T47	9		T48	11
all_pins[19]	transitions[0x1=>0x0]	754445	1			T46	4		T47	35		T48	19
all_pins[20]	values[0x0]	2074348	1			T41	1		T42	1		T43	1
all_pins[20]	values[0x1]	1258140	1			T46	4		T47	32		T48	29
all_pins[20]	transitions[0x0=>0x1]	752178	1			T46	4		T47	20		T48	8
all_pins[20]	transitions[0x1=>0x0]	760030	1			T46	6		T47	3		T48	11
all_pins[21]	values[0x0]	2066845	1			T41	1		T42	1		T43	1
all_pins[21]	values[0x1]	1265643	1			T46	11		T47	12		T48	20
all_pins[21]	transitions[0x0=>0x1]	759308	1			T46	9		T47	7		T48	12
all_pins[21]	transitions[0x1=>0x0]	751805	1			T46	2		T47	27		T48	21
all_pins[22]	values[0x0]	2068443	1			T41	1		T42	1		T43	1
all_pins[22]	values[0x1]	1264045	1			T46	26		T47	39		T48	34
all_pins[22]	transitions[0x0=>0x1]	754983	1			T46	19		T47	39		T48	22
all_pins[22]	transitions[0x1=>0x0]	756581	1			T46	4		T47	12		T48	8
all_pins[23]	values[0x0]	2070621	1			T41	1		T42	1		T43	1
all_pins[23]	values[0x1]	1261867	1			T46	13		T47	43		T48	33
all_pins[23]	transitions[0x0=>0x1]	755425	1			T46	3		T47	20		T48	17
all_pins[23]	transitions[0x1=>0x0]	757603	1			T46	16		T47	16		T48	18
all_pins[24]	values[0x0]	2068812	1			T41	1		T42	1		T43	1
all_pins[24]	values[0x1]	1263676	1			T46	11		T47	42		T48	24
all_pins[24]	transitions[0x0=>0x1]	756061	1			T46	7		T47	14		T48	10
all_pins[24]	transitions[0x1=>0x0]	754252	1			T46	9		T47	15		T48	19
all_pins[25]	values[0x0]	2071189	1			T41	1		T42	1		T43	1
all_pins[25]	values[0x1]	1261299	1			T46	9		T47	17		T48	32
all_pins[25]	transitions[0x0=>0x1]	755635	1			T46	6		T47	1		T48	18
all_pins[25]	transitions[0x1=>0x0]	758012	1			T46	8		T47	26		T48	10
all_pins[26]	values[0x0]	2073434	1			T41	1		T42	1		T43	1
all_pins[26]	values[0x1]	1259054	1			T46	9		T47	33		T48	32
all_pins[26]	transitions[0x0=>0x1]	753535	1			T46	8		T47	25		T48	18
all_pins[26]	transitions[0x1=>0x0]	755780	1			T46	8		T47	9		T48	18
all_pins[27]	values[0x0]	2074147	1			T41	1		T42	1		T43	1
all_pins[27]	values[0x1]	1258341	1			T46	8		T47	49		T48	31
all_pins[27]	transitions[0x0=>0x1]	754441	1			T46	5		T47	26		T48	12
all_pins[27]	transitions[0x1=>0x0]	755154	1			T46	6		T47	10		T48	13
all_pins[28]	values[0x0]	2068300	1			T41	1		T42	1		T43	1
all_pins[28]	values[0x1]	1264188	1			T46	13		T47	6		T48	25
all_pins[28]	transitions[0x0=>0x1]	757231	1			T46	9		T47	5		T48	9
all_pins[28]	transitions[0x1=>0x0]	751384	1			T46	4		T47	48		T48	15
all_pins[29]	values[0x0]	2070150	1			T41	1		T42	1		T43	1
all_pins[29]	values[0x1]	1262338	1			T46	10		T47	42		T48	26
all_pins[29]	transitions[0x0=>0x1]	756176	1			T46	8		T47	38		T48	18
all_pins[29]	transitions[0x1=>0x0]	758026	1			T46	11		T47	2		T48	17
all_pins[30]	values[0x0]	2072567	1			T41	1		T42	1		T43	1
all_pins[30]	values[0x1]	1259921	1			T46	2		T47	24		T48	29
all_pins[30]	transitions[0x0=>0x1]	751836	1			T46	2		T47	7		T48	15
all_pins[30]	transitions[0x1=>0x0]	754253	1			T46	10		T47	25		T48	12
all_pins[31]	values[0x0]	2072612	1			T41	1		T42	1		T43	1
all_pins[31]	values[0x1]	1259876	1			T46	15		T47	36		T48	20
all_pins[31]	transitions[0x0=>0x1]	756198	1			T46	15		T47	35		T48	8
all_pins[31]	transitions[0x1=>0x0]	756243	1			T46	2		T47	23		T48	17