Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/gpio-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	32	0	32	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	128	0	128	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	1686296	1			T25	1		T26	1		T27	1
all_pins[1]	1686296	1			T25	1		T26	1		T27	1
all_pins[2]	1686296	1			T25	1		T26	1		T27	1
all_pins[3]	1686296	1			T25	1		T26	1		T27	1
all_pins[4]	1686296	1			T25	1		T26	1		T27	1
all_pins[5]	1686296	1			T25	1		T26	1		T27	1
all_pins[6]	1686296	1			T25	1		T26	1		T27	1
all_pins[7]	1686296	1			T25	1		T26	1		T27	1
all_pins[8]	1686296	1			T25	1		T26	1		T27	1
all_pins[9]	1686296	1			T25	1		T26	1		T27	1
all_pins[10]	1686296	1			T25	1		T26	1		T27	1
all_pins[11]	1686296	1			T25	1		T26	1		T27	1
all_pins[12]	1686296	1			T25	1		T26	1		T27	1
all_pins[13]	1686296	1			T25	1		T26	1		T27	1
all_pins[14]	1686296	1			T25	1		T26	1		T27	1
all_pins[15]	1686296	1			T25	1		T26	1		T27	1
all_pins[16]	1686296	1			T25	1		T26	1		T27	1
all_pins[17]	1686296	1			T25	1		T26	1		T27	1
all_pins[18]	1686296	1			T25	1		T26	1		T27	1
all_pins[19]	1686296	1			T25	1		T26	1		T27	1
all_pins[20]	1686296	1			T25	1		T26	1		T27	1
all_pins[21]	1686296	1			T25	1		T26	1		T27	1
all_pins[22]	1686296	1			T25	1		T26	1		T27	1
all_pins[23]	1686296	1			T25	1		T26	1		T27	1
all_pins[24]	1686296	1			T25	1		T26	1		T27	1
all_pins[25]	1686296	1			T25	1		T26	1		T27	1
all_pins[26]	1686296	1			T25	1		T26	1		T27	1
all_pins[27]	1686296	1			T25	1		T26	1		T27	1
all_pins[28]	1686296	1			T25	1		T26	1		T27	1
all_pins[29]	1686296	1			T25	1		T26	1		T27	1
all_pins[30]	1686296	1			T25	1		T26	1		T27	1
all_pins[31]	1686296	1			T25	1		T26	1		T27	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	33552320	1			T25	32		T26	32		T27	32
values[0x1]	20409152	1			T28	1047		T30	363		T32	299
transitions[0x0=>0x1]	12215345	1			T28	676		T30	234		T32	168
transitions[0x1=>0x0]	12215196	1			T28	675		T30	234		T32	168

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	1048776	1			T25	1		T26	1		T27	1
all_pins[0]	values[0x1]	637520	1			T28	46		T30	5		T32	9
all_pins[0]	transitions[0x0=>0x1]	393375	1			T28	39		T30	4		T32	2
all_pins[0]	transitions[0x1=>0x0]	394893	1			T28	5		T30	2		T32	9
all_pins[1]	values[0x0]	1050266	1			T25	1		T26	1		T27	1
all_pins[1]	values[0x1]	636030	1			T28	28		T30	11		T32	13
all_pins[1]	transitions[0x0=>0x1]	379815	1			T28	10		T30	8		T32	8
all_pins[1]	transitions[0x1=>0x0]	381305	1			T28	28		T30	2		T32	4
all_pins[2]	values[0x0]	1047623	1			T25	1		T26	1		T27	1
all_pins[2]	values[0x1]	638673	1			T28	36		T30	17		T32	13
all_pins[2]	transitions[0x0=>0x1]	383257	1			T28	23		T30	13		T32	5
all_pins[2]	transitions[0x1=>0x0]	380614	1			T28	15		T30	7		T32	5
all_pins[3]	values[0x0]	1048636	1			T25	1		T26	1		T27	1
all_pins[3]	values[0x1]	637660	1			T28	33		T30	20		T32	7
all_pins[3]	transitions[0x0=>0x1]	381544	1			T28	19		T30	14		T32	3
all_pins[3]	transitions[0x1=>0x0]	382557	1			T28	22		T30	11		T32	9
all_pins[4]	values[0x0]	1049844	1			T25	1		T26	1		T27	1
all_pins[4]	values[0x1]	636452	1			T28	19		T30	20		T32	8
all_pins[4]	transitions[0x0=>0x1]	380364	1			T28	17		T30	3		T32	5
all_pins[4]	transitions[0x1=>0x0]	381572	1			T28	31		T30	3		T32	4
all_pins[5]	values[0x0]	1044003	1			T25	1		T26	1		T27	1
all_pins[5]	values[0x1]	642293	1			T28	32		T30	24		T32	6
all_pins[5]	transitions[0x0=>0x1]	385012	1			T28	27		T30	11		T32	2
all_pins[5]	transitions[0x1=>0x0]	379171	1			T28	14		T30	7		T32	4
all_pins[6]	values[0x0]	1050332	1			T25	1		T26	1		T27	1
all_pins[6]	values[0x1]	635964	1			T28	41		T30	6		T32	14
all_pins[6]	transitions[0x0=>0x1]	378297	1			T28	32		T30	3		T32	10
all_pins[6]	transitions[0x1=>0x0]	384626	1			T28	23		T30	21		T32	2
all_pins[7]	values[0x0]	1048944	1			T25	1		T26	1		T27	1
all_pins[7]	values[0x1]	637352	1			T28	20		T30	14		T32	7
all_pins[7]	transitions[0x0=>0x1]	382522	1			T28	11		T30	11		T32	5
all_pins[7]	transitions[0x1=>0x0]	381134	1			T28	32		T30	3		T32	12
all_pins[8]	values[0x0]	1050846	1			T25	1		T26	1		T27	1
all_pins[8]	values[0x1]	635450	1			T28	33		T30	14		T32	5
all_pins[8]	transitions[0x0=>0x1]	380357	1			T28	17		T30	3		T32	2
all_pins[8]	transitions[0x1=>0x0]	382259	1			T28	4		T30	3		T32	4
all_pins[9]	values[0x0]	1046660	1			T25	1		T26	1		T27	1
all_pins[9]	values[0x1]	639636	1			T28	32		T30	4		T32	5
all_pins[9]	transitions[0x0=>0x1]	382505	1			T28	18		T30	3		T32	4
all_pins[9]	transitions[0x1=>0x0]	378319	1			T28	19		T30	13		T32	4
all_pins[10]	values[0x0]	1052716	1			T25	1		T26	1		T27	1
all_pins[10]	values[0x1]	633580	1			T28	22		T30	18		T32	8
all_pins[10]	transitions[0x0=>0x1]	377385	1			T28	15		T30	16		T32	7
all_pins[10]	transitions[0x1=>0x0]	383441	1			T28	25		T30	2		T32	4
all_pins[11]	values[0x0]	1052570	1			T25	1		T26	1		T27	1
all_pins[11]	values[0x1]	633726	1			T28	37		T30	10		T32	10
all_pins[11]	transitions[0x0=>0x1]	380626	1			T28	33		T30	4		T32	6
all_pins[11]	transitions[0x1=>0x0]	380480	1			T28	18		T30	12		T32	4
all_pins[12]	values[0x0]	1049976	1			T25	1		T26	1		T27	1
all_pins[12]	values[0x1]	636320	1			T28	30		T30	13		T32	7
all_pins[12]	transitions[0x0=>0x1]	381833	1			T28	24		T30	8		T32	3
all_pins[12]	transitions[0x1=>0x0]	379239	1			T28	31		T30	5		T32	6
all_pins[13]	values[0x0]	1045845	1			T25	1		T26	1		T27	1
all_pins[13]	values[0x1]	640451	1			T28	44		T30	17		T32	11
all_pins[13]	transitions[0x0=>0x1]	384663	1			T28	31		T30	11		T32	8
all_pins[13]	transitions[0x1=>0x0]	380532	1			T28	17		T30	7		T32	4
all_pins[14]	values[0x0]	1047432	1			T25	1		T26	1		T27	1
all_pins[14]	values[0x1]	638864	1			T28	29		T30	6		T32	14
all_pins[14]	transitions[0x0=>0x1]	380534	1			T28	6		T30	2		T32	5
all_pins[14]	transitions[0x1=>0x0]	382121	1			T28	21		T30	13		T32	2
all_pins[15]	values[0x0]	1050715	1			T25	1		T26	1		T27	1
all_pins[15]	values[0x1]	635581	1			T28	43		T30	1		T32	6
all_pins[15]	transitions[0x0=>0x1]	379981	1			T28	28		T32	2		T33	125
all_pins[15]	transitions[0x1=>0x0]	383264	1			T28	14		T30	5		T32	10
all_pins[16]	values[0x0]	1048347	1			T25	1		T26	1		T27	1
all_pins[16]	values[0x1]	637949	1			T28	53		T30	15		T32	10
all_pins[16]	transitions[0x0=>0x1]	382403	1			T28	25		T30	14		T32	7
all_pins[16]	transitions[0x1=>0x0]	380035	1			T28	15		T32	3		T33	89
all_pins[17]	values[0x0]	1047918	1			T25	1		T26	1		T27	1
all_pins[17]	values[0x1]	638378	1			T28	33		T30	16		T32	5
all_pins[17]	transitions[0x0=>0x1]	381587	1			T28	18		T30	10		T32	3
all_pins[17]	transitions[0x1=>0x0]	381158	1			T28	38		T30	9		T32	8
all_pins[18]	values[0x0]	1047435	1			T25	1		T26	1		T27	1
all_pins[18]	values[0x1]	638861	1			T28	19		T30	5		T32	12
all_pins[18]	transitions[0x0=>0x1]	381780	1			T28	5		T32	10		T33	64
all_pins[18]	transitions[0x1=>0x0]	381297	1			T28	19		T30	11		T32	3
all_pins[19]	values[0x0]	1049876	1			T25	1		T26	1		T27	1
all_pins[19]	values[0x1]	636420	1			T28	47		T30	11		T32	10
all_pins[19]	transitions[0x0=>0x1]	378601	1			T28	39		T30	9		T32	6
all_pins[19]	transitions[0x1=>0x0]	381042	1			T28	11		T30	3		T32	8
all_pins[20]	values[0x0]	1047514	1			T25	1		T26	1		T27	1
all_pins[20]	values[0x1]	638782	1			T28	35		T30	10		T32	14
all_pins[20]	transitions[0x0=>0x1]	382016	1			T28	18		T30	6		T32	6
all_pins[20]	transitions[0x1=>0x0]	379654	1			T28	30		T30	7		T32	2
all_pins[21]	values[0x0]	1048109	1			T25	1		T26	1		T27	1
all_pins[21]	values[0x1]	638187	1			T28	42		T30	15		T32	7
all_pins[21]	transitions[0x0=>0x1]	382163	1			T28	22		T30	11		T32	2
all_pins[21]	transitions[0x1=>0x0]	382758	1			T28	15		T30	6		T32	9
all_pins[22]	values[0x0]	1052391	1			T25	1		T26	1		T27	1
all_pins[22]	values[0x1]	633905	1			T28	18		T30	11		T32	14
all_pins[22]	transitions[0x0=>0x1]	376703	1			T28	10		T30	8		T32	10
all_pins[22]	transitions[0x1=>0x0]	380985	1			T28	34		T30	12		T32	3
all_pins[23]	values[0x0]	1047590	1			T25	1		T26	1		T27	1
all_pins[23]	values[0x1]	638706	1			T28	19		T30	2		T32	9
all_pins[23]	transitions[0x0=>0x1]	383644	1			T28	17		T30	2		T32	4
all_pins[23]	transitions[0x1=>0x0]	378843	1			T28	16		T30	11		T32	9
all_pins[24]	values[0x0]	1046715	1			T25	1		T26	1		T27	1
all_pins[24]	values[0x1]	639581	1			T28	23		T30	3		T32	6
all_pins[24]	transitions[0x0=>0x1]	382734	1			T28	15		T30	3		T32	4
all_pins[24]	transitions[0x1=>0x0]	381859	1			T28	11		T30	2		T32	7
all_pins[25]	values[0x0]	1048176	1			T25	1		T26	1		T27	1
all_pins[25]	values[0x1]	638120	1			T28	43		T30	13		T32	9
all_pins[25]	transitions[0x0=>0x1]	382035	1			T28	27		T30	12		T32	5
all_pins[25]	transitions[0x1=>0x0]	383496	1			T28	7		T30	2		T32	2
all_pins[26]	values[0x0]	1045773	1			T25	1		T26	1		T27	1
all_pins[26]	values[0x1]	640523	1			T28	17		T30	12		T32	16
all_pins[26]	transitions[0x0=>0x1]	381835	1			T28	13		T30	9		T32	10
all_pins[26]	transitions[0x1=>0x0]	379432	1			T28	39		T30	10		T32	3
all_pins[27]	values[0x0]	1048389	1			T25	1		T26	1		T27	1
all_pins[27]	values[0x1]	637907	1			T28	53		T30	14		T32	5
all_pins[27]	transitions[0x0=>0x1]	379236	1			T28	40		T30	14		T32	1
all_pins[27]	transitions[0x1=>0x0]	381852	1			T28	4		T30	12		T32	12
all_pins[28]	values[0x0]	1046752	1			T25	1		T26	1		T27	1
all_pins[28]	values[0x1]	639544	1			T28	33		T30	2		T32	8
all_pins[28]	transitions[0x0=>0x1]	382401	1			T28	17		T32	5		T33	151
all_pins[28]	transitions[0x1=>0x0]	380764	1			T28	37		T30	12		T32	2
all_pins[29]	values[0x0]	1046381	1			T25	1		T26	1		T27	1
all_pins[29]	values[0x1]	639915	1			T28	45		T30	22		T32	9
all_pins[29]	transitions[0x0=>0x1]	382887	1			T28	30		T30	20		T32	4
all_pins[29]	transitions[0x1=>0x0]	382516	1			T28	18		T32	3		T33	87
all_pins[30]	values[0x0]	1048661	1			T25	1		T26	1		T27	1
all_pins[30]	values[0x1]	637635	1			T28	29		T30	9		T32	6
all_pins[30]	transitions[0x0=>0x1]	380801	1			T28	20		T30	1		T32	2
all_pins[30]	transitions[0x1=>0x0]	383081	1			T28	36		T30	14		T32	5
all_pins[31]	values[0x0]	1047109	1			T25	1		T26	1		T27	1
all_pins[31]	values[0x1]	639187	1			T28	13		T30	3		T32	16
all_pins[31]	transitions[0x0=>0x1]	382449	1			T28	10		T30	1		T32	12
all_pins[31]	transitions[0x1=>0x0]	380897	1			T28	26		T30	7		T32	2