Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	32	0	32	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	192	0	192	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	11407897	1			T41	259		T42	306		T43	55
all_values[1]	11407897	1			T41	259		T42	306		T43	55
all_values[2]	11407897	1			T41	259		T42	306		T43	55
all_values[3]	11407897	1			T41	259		T42	306		T43	55
all_values[4]	11407897	1			T41	259		T42	306		T43	55
all_values[5]	11407897	1			T41	259		T42	306		T43	55
all_values[6]	11407897	1			T41	259		T42	306		T43	55
all_values[7]	11407897	1			T41	259		T42	306		T43	55
all_values[8]	11407897	1			T41	259		T42	306		T43	55
all_values[9]	11407897	1			T41	259		T42	306		T43	55
all_values[10]	11407897	1			T41	259		T42	306		T43	55
all_values[11]	11407897	1			T41	259		T42	306		T43	55
all_values[12]	11407897	1			T41	259		T42	306		T43	55
all_values[13]	11407897	1			T41	259		T42	306		T43	55
all_values[14]	11407897	1			T41	259		T42	306		T43	55
all_values[15]	11407897	1			T41	259		T42	306		T43	55
all_values[16]	11407897	1			T41	259		T42	306		T43	55
all_values[17]	11407897	1			T41	259		T42	306		T43	55
all_values[18]	11407897	1			T41	259		T42	306		T43	55
all_values[19]	11407897	1			T41	259		T42	306		T43	55
all_values[20]	11407897	1			T41	259		T42	306		T43	55
all_values[21]	11407897	1			T41	259		T42	306		T43	55
all_values[22]	11407897	1			T41	259		T42	306		T43	55
all_values[23]	11407897	1			T41	259		T42	306		T43	55
all_values[24]	11407897	1			T41	259		T42	306		T43	55
all_values[25]	11407897	1			T41	259		T42	306		T43	55
all_values[26]	11407897	1			T41	259		T42	306		T43	55
all_values[27]	11407897	1			T41	259		T42	306		T43	55
all_values[28]	11407897	1			T41	259		T42	306		T43	55
all_values[29]	11407897	1			T41	259		T42	306		T43	55
all_values[30]	11407897	1			T41	259		T42	306		T43	55
all_values[31]	11407897	1			T41	259		T42	306		T43	55

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

215512931

1

T41

8288

T42

9792

T43

1760

auto[1]

149539773

1

T46

863

T47

2432

T51

39210

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

94929144

1

T41

8288

T42

9792

T43

1760

auto[1]

270123560

1

T46

1273

T47

3861

T51

72595

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

361061192

1

T41

8288

T42

9792

T43

1760

auto[1]

3991512

1

T46

139

T64

325

T65

749

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	2512197	1			T41	259		T42	306		T43	55
all_values[0]	auto[0]	auto[0]	auto[1]	4151871	1			T46	19		T47	94		T51	1225
all_values[0]	auto[0]	auto[1]	auto[0]	451197	1			T46	7		T47	3		T51	95
all_values[0]	auto[0]	auto[1]	auto[1]	4168149	1			T46	15		T47	18		T51	1157
all_values[0]	auto[1]	auto[0]	auto[1]	62174	1			T46	2		T64	5		T65	13
all_values[0]	auto[1]	auto[1]	auto[1]	62309	1			T46	1		T64	4		T65	12
all_values[1]	auto[0]	auto[0]	auto[0]	2512014	1			T41	259		T42	306		T43	55
all_values[1]	auto[0]	auto[0]	auto[1]	4206760	1			T46	16		T47	26		T51	1079
all_values[1]	auto[0]	auto[1]	auto[0]	457859	1			T46	7		T47	17		T51	122
all_values[1]	auto[0]	auto[1]	auto[1]	4106311	1			T46	7		T47	98		T51	1181
all_values[1]	auto[1]	auto[0]	auto[1]	63021	1			T46	4		T64	7		T65	7
all_values[1]	auto[1]	auto[1]	auto[1]	61932	1			T46	1		T64	3		T65	14
all_values[2]	auto[0]	auto[0]	auto[0]	2523547	1			T41	259		T42	306		T43	55
all_values[2]	auto[0]	auto[0]	auto[1]	4175643	1			T46	18		T47	27		T51	929
all_values[2]	auto[0]	auto[1]	auto[0]	454122	1			T46	16		T47	1		T51	118
all_values[2]	auto[0]	auto[1]	auto[1]	4129733	1			T46	23		T47	108		T51	1381
all_values[2]	auto[1]	auto[0]	auto[1]	62994	1			T64	8		T65	14		T125	40
all_values[2]	auto[1]	auto[1]	auto[1]	61858	1			T46	4		T64	3		T65	6
all_values[3]	auto[0]	auto[0]	auto[0]	2507028	1			T41	259		T42	306		T43	55
all_values[3]	auto[0]	auto[0]	auto[1]	4144629	1			T46	37		T47	52		T51	1076
all_values[3]	auto[0]	auto[1]	auto[0]	458097	1			T46	17		T47	17		T51	94
all_values[3]	auto[0]	auto[1]	auto[1]	4173553	1			T46	5		T47	48		T51	1187
all_values[3]	auto[1]	auto[0]	auto[1]	62151	1			T46	6		T64	9		T65	8
all_values[3]	auto[1]	auto[1]	auto[1]	62439	1			T46	2		T64	2		T65	20
all_values[4]	auto[0]	auto[0]	auto[0]	2509490	1			T41	259		T42	306		T43	55
all_values[4]	auto[0]	auto[0]	auto[1]	4155287	1			T46	21		T47	68		T51	1083
all_values[4]	auto[0]	auto[1]	auto[0]	449633	1			T46	10		T47	5		T51	134
all_values[4]	auto[0]	auto[1]	auto[1]	4168619	1			T46	13		T47	59		T51	1099
all_values[4]	auto[1]	auto[0]	auto[1]	62692	1			T46	5		T64	12		T65	14
all_values[4]	auto[1]	auto[1]	auto[1]	62176	1			T46	1		T64	4		T65	12
all_values[5]	auto[0]	auto[0]	auto[0]	2506748	1			T41	259		T42	306		T43	55
all_values[5]	auto[0]	auto[0]	auto[1]	4168776	1			T46	30		T47	98		T51	1286
all_values[5]	auto[0]	auto[1]	auto[0]	453351	1			T46	17		T47	12		T51	97
all_values[5]	auto[0]	auto[1]	auto[1]	4153988	1			T46	6		T47	27		T51	1038
all_values[5]	auto[1]	auto[0]	auto[1]	62414	1			T46	5		T64	7		T65	13
all_values[5]	auto[1]	auto[1]	auto[1]	62620	1			T46	2		T64	4		T65	12
all_values[6]	auto[0]	auto[0]	auto[0]	2503489	1			T41	259		T42	306		T43	55
all_values[6]	auto[0]	auto[0]	auto[1]	4133445	1			T46	20		T47	63		T51	1269
all_values[6]	auto[0]	auto[1]	auto[0]	455218	1			T46	26		T47	20		T51	124
all_values[6]	auto[0]	auto[1]	auto[1]	4190693	1			T46	11		T47	59		T51	964
all_values[6]	auto[1]	auto[0]	auto[1]	62503	1			T46	3		T64	7		T65	12
all_values[6]	auto[1]	auto[1]	auto[1]	62549	1			T46	2		T64	5		T65	11
all_values[7]	auto[0]	auto[0]	auto[0]	2512167	1			T41	259		T42	306		T43	55
all_values[7]	auto[0]	auto[0]	auto[1]	4164937	1			T46	21		T47	74		T51	1234
all_values[7]	auto[0]	auto[1]	auto[0]	455463	1			T46	13		T47	5		T51	78
all_values[7]	auto[0]	auto[1]	auto[1]	4150397	1			T46	10		T47	54		T51	1142
all_values[7]	auto[1]	auto[0]	auto[1]	62681	1			T46	3		T64	3		T65	10
all_values[7]	auto[1]	auto[1]	auto[1]	62252	1			T46	1		T64	2		T65	19
all_values[8]	auto[0]	auto[0]	auto[0]	2512584	1			T41	259		T42	306		T43	55
all_values[8]	auto[0]	auto[0]	auto[1]	4171683	1			T46	18		T47	99		T51	1200
all_values[8]	auto[0]	auto[1]	auto[0]	450750	1			T46	9		T47	4		T51	111
all_values[8]	auto[0]	auto[1]	auto[1]	4148335	1			T46	4		T47	36		T51	1076
all_values[8]	auto[1]	auto[0]	auto[1]	62463	1			T46	2		T64	8		T65	16
all_values[8]	auto[1]	auto[1]	auto[1]	62082	1			T46	1		T64	4		T65	10
all_values[9]	auto[0]	auto[0]	auto[0]	2509393	1			T41	259		T42	306		T43	55
all_values[9]	auto[0]	auto[0]	auto[1]	4165769	1			T46	20		T47	37		T51	1068
all_values[9]	auto[0]	auto[1]	auto[0]	460774	1			T46	16		T47	21		T51	178
all_values[9]	auto[0]	auto[1]	auto[1]	4147172	1			T46	6		T47	83		T51	1119
all_values[9]	auto[1]	auto[0]	auto[1]	62343	1			T46	2		T64	4		T65	14
all_values[9]	auto[1]	auto[1]	auto[1]	62446	1			T46	1		T64	7		T65	15
all_values[10]	auto[0]	auto[0]	auto[0]	2520891	1			T41	259		T42	306		T43	55
all_values[10]	auto[0]	auto[0]	auto[1]	4176964	1			T46	15		T47	43		T51	1211
all_values[10]	auto[0]	auto[1]	auto[0]	456936	1			T46	36		T47	10		T51	74
all_values[10]	auto[0]	auto[1]	auto[1]	4128448	1			T46	10		T47	88		T51	1109
all_values[10]	auto[1]	auto[0]	auto[1]	62514	1			T46	2		T64	4		T65	13
all_values[10]	auto[1]	auto[1]	auto[1]	62144	1			T46	3		T64	7		T65	7
all_values[11]	auto[0]	auto[0]	auto[0]	2507031	1			T41	259		T42	306		T43	55
all_values[11]	auto[0]	auto[0]	auto[1]	4135387	1			T46	24		T47	21		T51	1341
all_values[11]	auto[0]	auto[1]	auto[0]	451548	1			T46	13		T47	9		T51	115
all_values[11]	auto[0]	auto[1]	auto[1]	4189262	1			T46	24		T47	108		T51	877
all_values[11]	auto[1]	auto[0]	auto[1]	61930	1			T46	4		T64	5		T65	7
all_values[11]	auto[1]	auto[1]	auto[1]	62739	1			T46	2		T64	2		T65	12
all_values[12]	auto[0]	auto[0]	auto[0]	2510167	1			T41	259		T42	306		T43	55
all_values[12]	auto[0]	auto[0]	auto[1]	4156375	1			T46	19		T47	88		T51	724
all_values[12]	auto[0]	auto[1]	auto[0]	455711	1			T46	20		T47	9		T51	159
all_values[12]	auto[0]	auto[1]	auto[1]	4160745	1			T46	9		T47	40		T51	1459
all_values[12]	auto[1]	auto[0]	auto[1]	62451	1			T46	4		T64	8		T65	12
all_values[12]	auto[1]	auto[1]	auto[1]	62448	1			T64	4		T65	10		T125	44
all_values[13]	auto[0]	auto[0]	auto[0]	2510073	1			T41	259		T42	306		T43	55
all_values[13]	auto[0]	auto[0]	auto[1]	4161574	1			T46	19		T47	8		T51	1235
all_values[13]	auto[0]	auto[1]	auto[0]	458386	1			T46	13		T47	5		T51	99
all_values[13]	auto[0]	auto[1]	auto[1]	4152851	1			T46	19		T47	129		T51	1062
all_values[13]	auto[1]	auto[0]	auto[1]	62374	1			T46	3		T64	3		T65	12
all_values[13]	auto[1]	auto[1]	auto[1]	62639	1			T46	1		T64	8		T65	19
all_values[14]	auto[0]	auto[0]	auto[0]	2506151	1			T41	259		T42	306		T43	55
all_values[14]	auto[0]	auto[0]	auto[1]	4187522	1			T46	29		T47	69		T51	1210
all_values[14]	auto[0]	auto[1]	auto[0]	458180	1			T46	6		T47	7		T51	146
all_values[14]	auto[0]	auto[1]	auto[1]	4130714	1			T46	14		T47	53		T51	1015
all_values[14]	auto[1]	auto[0]	auto[1]	63250	1			T46	3		T64	8		T65	10
all_values[14]	auto[1]	auto[1]	auto[1]	62080	1			T46	1		T64	3		T65	15
all_values[15]	auto[0]	auto[0]	auto[0]	2507700	1			T41	259		T42	306		T43	55
all_values[15]	auto[0]	auto[0]	auto[1]	4159539	1			T46	33		T47	15		T51	1348
all_values[15]	auto[0]	auto[1]	auto[0]	457276	1			T46	14		T47	18		T51	149
all_values[15]	auto[0]	auto[1]	auto[1]	4159038	1			T46	4		T47	100		T51	893
all_values[15]	auto[1]	auto[0]	auto[1]	62271	1			T46	3		T64	4		T65	15
all_values[15]	auto[1]	auto[1]	auto[1]	62073	1			T64	5		T65	7		T125	25
all_values[16]	auto[0]	auto[0]	auto[0]	2514937	1			T41	259		T42	306		T43	55
all_values[16]	auto[0]	auto[0]	auto[1]	4149509	1			T46	24		T47	66		T51	1325
all_values[16]	auto[0]	auto[1]	auto[0]	465782	1			T46	10		T47	2		T51	108
all_values[16]	auto[0]	auto[1]	auto[1]	4152790	1			T46	5		T47	68		T51	939
all_values[16]	auto[1]	auto[0]	auto[1]	62676	1			T64	5		T65	13		T125	33
all_values[16]	auto[1]	auto[1]	auto[1]	62203	1			T46	1		T64	6		T65	8
all_values[17]	auto[0]	auto[0]	auto[0]	2507282	1			T41	259		T42	306		T43	55
all_values[17]	auto[0]	auto[0]	auto[1]	4172938	1			T46	19		T47	66		T51	1173
all_values[17]	auto[0]	auto[1]	auto[0]	454086	1			T46	13		T47	12		T51	149
all_values[17]	auto[0]	auto[1]	auto[1]	4148354	1			T46	10		T47	52		T51	1015
all_values[17]	auto[1]	auto[0]	auto[1]	62841	1			T46	2		T64	4		T65	15
all_values[17]	auto[1]	auto[1]	auto[1]	62396	1			T46	2		T64	4		T65	10
all_values[18]	auto[0]	auto[0]	auto[0]	2505207	1			T41	259		T42	306		T43	55
all_values[18]	auto[0]	auto[0]	auto[1]	4171288	1			T46	23		T47	34		T51	1272
all_values[18]	auto[0]	auto[1]	auto[0]	458011	1			T46	13		T47	14		T51	90
all_values[18]	auto[0]	auto[1]	auto[1]	4148520	1			T46	4		T47	84		T51	1060
all_values[18]	auto[1]	auto[0]	auto[1]	62628	1			T46	3		T64	4		T65	13
all_values[18]	auto[1]	auto[1]	auto[1]	62243	1			T46	2		T64	6		T65	9
all_values[19]	auto[0]	auto[0]	auto[0]	2502343	1			T41	259		T42	306		T43	55
all_values[19]	auto[0]	auto[0]	auto[1]	4158240	1			T46	40		T47	76		T51	1081
all_values[19]	auto[0]	auto[1]	auto[0]	458184	1			T46	8		T47	21		T51	156
all_values[19]	auto[0]	auto[1]	auto[1]	4164048	1			T46	4		T47	31		T51	1197
all_values[19]	auto[1]	auto[0]	auto[1]	62934	1			T46	2		T64	8		T65	10
all_values[19]	auto[1]	auto[1]	auto[1]	62148	1			T46	1		T65	14		T125	27
all_values[20]	auto[0]	auto[0]	auto[0]	2508121	1			T41	259		T42	306		T43	55
all_values[20]	auto[0]	auto[0]	auto[1]	4151386	1			T46	37		T47	50		T51	1269
all_values[20]	auto[0]	auto[1]	auto[0]	455734	1			T46	14		T47	14		T51	53
all_values[20]	auto[0]	auto[1]	auto[1]	4167920	1			T46	5		T47	61		T51	1081
all_values[20]	auto[1]	auto[0]	auto[1]	62838	1			T46	5		T64	5		T65	8
all_values[20]	auto[1]	auto[1]	auto[1]	61898	1			T46	1		T64	5		T65	9
all_values[21]	auto[0]	auto[0]	auto[0]	2510796	1			T41	259		T42	306		T43	55
all_values[21]	auto[0]	auto[0]	auto[1]	4144441	1			T46	42		T47	116		T51	1293
all_values[21]	auto[0]	auto[1]	auto[0]	456615	1			T46	11		T51	164		T64	5
all_values[21]	auto[0]	auto[1]	auto[1]	4171212	1			T46	11		T47	19		T51	925
all_values[21]	auto[1]	auto[0]	auto[1]	62569	1			T46	2		T64	5		T65	8
all_values[21]	auto[1]	auto[1]	auto[1]	62264	1			T46	2		T64	5		T65	13
all_values[22]	auto[0]	auto[0]	auto[0]	2508776	1			T41	259		T42	306		T43	55
all_values[22]	auto[0]	auto[0]	auto[1]	4165874	1			T46	22		T47	39		T51	1070
all_values[22]	auto[0]	auto[1]	auto[0]	460142	1			T46	15		T47	24		T51	122
all_values[22]	auto[0]	auto[1]	auto[1]	4148110	1			T46	31		T47	77		T51	1172
all_values[22]	auto[1]	auto[0]	auto[1]	62497	1			T46	3		T64	4		T65	15
all_values[22]	auto[1]	auto[1]	auto[1]	62498	1			T46	2		T64	6		T65	11
all_values[23]	auto[0]	auto[0]	auto[0]	2503968	1			T41	259		T42	306		T43	55
all_values[23]	auto[0]	auto[0]	auto[1]	4173207	1			T46	22		T47	37		T51	1219
all_values[23]	auto[0]	auto[1]	auto[0]	457433	1			T46	8		T47	21		T51	153
all_values[23]	auto[0]	auto[1]	auto[1]	4148864	1			T46	19		T47	78		T51	1020
all_values[23]	auto[1]	auto[0]	auto[1]	62159	1			T46	4		T64	6		T65	10
all_values[23]	auto[1]	auto[1]	auto[1]	62266	1			T46	1		T64	6		T65	10
all_values[24]	auto[0]	auto[0]	auto[0]	2507404	1			T41	259		T42	306		T43	55
all_values[24]	auto[0]	auto[0]	auto[1]	4148070	1			T46	20		T47	48		T51	1006
all_values[24]	auto[0]	auto[1]	auto[0]	457713	1			T46	21		T47	14		T51	90
all_values[24]	auto[0]	auto[1]	auto[1]	4170370	1			T46	15		T47	79		T51	1327
all_values[24]	auto[1]	auto[0]	auto[1]	62516	1			T46	2		T64	6		T65	14
all_values[24]	auto[1]	auto[1]	auto[1]	61824	1			T46	3		T64	4		T65	6
all_values[25]	auto[0]	auto[0]	auto[0]	2509419	1			T41	259		T42	306		T43	55
all_values[25]	auto[0]	auto[0]	auto[1]	4144335	1			T46	20		T47	69		T51	1095
all_values[25]	auto[0]	auto[1]	auto[0]	456947	1			T46	14		T47	23		T51	133
all_values[25]	auto[0]	auto[1]	auto[1]	4172683	1			T46	15		T47	26		T51	1234
all_values[25]	auto[1]	auto[0]	auto[1]	62379	1			T46	4		T64	12		T65	9
all_values[25]	auto[1]	auto[1]	auto[1]	62134	1			T46	1		T64	2		T65	12
all_values[26]	auto[0]	auto[0]	auto[0]	2512790	1			T41	259		T42	306		T43	55
all_values[26]	auto[0]	auto[0]	auto[1]	4175954	1			T46	35		T47	57		T51	1213
all_values[26]	auto[0]	auto[1]	auto[0]	453022	1			T46	17		T47	25		T51	106
all_values[26]	auto[0]	auto[1]	auto[1]	4141690	1			T46	8		T47	57		T51	1064
all_values[26]	auto[1]	auto[0]	auto[1]	62250	1			T46	3		T64	4		T65	12
all_values[26]	auto[1]	auto[1]	auto[1]	62191	1			T46	3		T64	1		T65	11
all_values[27]	auto[0]	auto[0]	auto[0]	2514049	1			T41	259		T42	306		T43	55
all_values[27]	auto[0]	auto[0]	auto[1]	4192426	1			T46	10		T47	18		T51	981
all_values[27]	auto[0]	auto[1]	auto[0]	459434	1			T46	14		T47	11		T51	85
all_values[27]	auto[0]	auto[1]	auto[1]	4117928	1			T46	10		T47	104		T51	1278
all_values[27]	auto[1]	auto[0]	auto[1]	62297	1			T46	3		T64	7		T65	12
all_values[27]	auto[1]	auto[1]	auto[1]	61763	1			T46	1		T64	4		T65	9
all_values[28]	auto[0]	auto[0]	auto[0]	2510865	1			T41	259		T42	306		T43	55
all_values[28]	auto[0]	auto[0]	auto[1]	4141127	1			T46	17		T47	108		T51	987
all_values[28]	auto[0]	auto[1]	auto[0]	458256	1			T46	21		T47	3		T51	146
all_values[28]	auto[0]	auto[1]	auto[1]	4172817	1			T46	19		T47	15		T51	1290
all_values[28]	auto[1]	auto[0]	auto[1]	62638	1			T46	4		T64	5		T65	16
all_values[28]	auto[1]	auto[1]	auto[1]	62194	1			T46	2		T64	5		T65	6
all_values[29]	auto[0]	auto[0]	auto[0]	2517013	1			T41	259		T42	306		T43	55
all_values[29]	auto[0]	auto[0]	auto[1]	4167128	1			T46	26		T47	29		T51	1178
all_values[29]	auto[0]	auto[1]	auto[0]	458023	1			T46	8		T47	43		T51	73
all_values[29]	auto[0]	auto[1]	auto[1]	4141618	1			T46	12		T47	68		T51	1126
all_values[29]	auto[1]	auto[0]	auto[1]	62503	1			T46	2		T64	6		T65	18
all_values[29]	auto[1]	auto[1]	auto[1]	61612	1			T46	1		T64	5		T65	9
all_values[30]	auto[0]	auto[0]	auto[0]	2507145	1			T41	259		T42	306		T43	55
all_values[30]	auto[0]	auto[0]	auto[1]	4151941	1			T46	29		T47	69		T51	1262
all_values[30]	auto[0]	auto[1]	auto[0]	456539	1			T46	11		T47	8		T51	131
all_values[30]	auto[0]	auto[1]	auto[1]	4167229	1			T46	4		T47	33		T51	905
all_values[30]	auto[1]	auto[0]	auto[1]	63361	1			T46	2		T64	5		T65	14
all_values[30]	auto[1]	auto[1]	auto[1]	61682	1			T64	4		T65	12		T125	33
all_values[31]	auto[0]	auto[0]	auto[0]	2513050	1			T41	259		T42	306		T43	55
all_values[31]	auto[0]	auto[0]	auto[1]	4163329	1			T46	17		T47	63		T51	1217
all_values[31]	auto[0]	auto[1]	auto[0]	454887	1			T46	7		T51	122		T64	25
all_values[31]	auto[0]	auto[1]	auto[1]	4152533	1			T46	20		T47	74		T51	1044
all_values[31]	auto[1]	auto[0]	auto[1]	62430	1			T46	1		T64	4		T65	15
all_values[31]	auto[1]	auto[1]	auto[1]	61668	1			T64	3		T65	7		T125	22

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal