Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/gpio-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	32	0	32	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	192	0	192	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	6779557	1			T25	20		T26	103		T27	259
all_values[1]	6779557	1			T25	20		T26	103		T27	259
all_values[2]	6779557	1			T25	20		T26	103		T27	259
all_values[3]	6779557	1			T25	20		T26	103		T27	259
all_values[4]	6779557	1			T25	20		T26	103		T27	259
all_values[5]	6779557	1			T25	20		T26	103		T27	259
all_values[6]	6779557	1			T25	20		T26	103		T27	259
all_values[7]	6779557	1			T25	20		T26	103		T27	259
all_values[8]	6779557	1			T25	20		T26	103		T27	259
all_values[9]	6779557	1			T25	20		T26	103		T27	259
all_values[10]	6779557	1			T25	20		T26	103		T27	259
all_values[11]	6779557	1			T25	20		T26	103		T27	259
all_values[12]	6779557	1			T25	20		T26	103		T27	259
all_values[13]	6779557	1			T25	20		T26	103		T27	259
all_values[14]	6779557	1			T25	20		T26	103		T27	259
all_values[15]	6779557	1			T25	20		T26	103		T27	259
all_values[16]	6779557	1			T25	20		T26	103		T27	259
all_values[17]	6779557	1			T25	20		T26	103		T27	259
all_values[18]	6779557	1			T25	20		T26	103		T27	259
all_values[19]	6779557	1			T25	20		T26	103		T27	259
all_values[20]	6779557	1			T25	20		T26	103		T27	259
all_values[21]	6779557	1			T25	20		T26	103		T27	259
all_values[22]	6779557	1			T25	20		T26	103		T27	259
all_values[23]	6779557	1			T25	20		T26	103		T27	259
all_values[24]	6779557	1			T25	20		T26	103		T27	259
all_values[25]	6779557	1			T25	20		T26	103		T27	259
all_values[26]	6779557	1			T25	20		T26	103		T27	259
all_values[27]	6779557	1			T25	20		T26	103		T27	259
all_values[28]	6779557	1			T25	20		T26	103		T27	259
all_values[29]	6779557	1			T25	20		T26	103		T27	259
all_values[30]	6779557	1			T25	20		T26	103		T27	259
all_values[31]	6779557	1			T25	20		T26	103		T27	259

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

143171820

1

T25

640

T26

3296

T27

8288

auto[1]

73774004

1

T28

2325

T30

946

T33

21301

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

83906477

1

T25

640

T26

3296

T27

8288

auto[1]

133039347

1

T28

4368

T30

1799

T33

38543

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

214889759

1

T25

640

T26

3296

T27

8288

auto[1]

2056065

1

T30

212

T1

573

T19

13

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	2395004	1			T25	20		T26	103		T27	259
all_values[0]	auto[0]	auto[0]	auto[1]	2047969	1			T28	64		T30	26		T33	540
all_values[0]	auto[0]	auto[1]	auto[0]	232235	1			T28	9		T30	7		T33	43
all_values[0]	auto[0]	auto[1]	auto[1]	2039733	1			T28	77		T30	11		T33	710
all_values[0]	auto[1]	auto[0]	auto[1]	32405	1			T30	4		T1	9		T34	1
all_values[0]	auto[1]	auto[1]	auto[1]	32211	1			T30	3		T1	11		T103	17
all_values[1]	auto[0]	auto[0]	auto[0]	2387963	1			T25	20		T26	103		T27	259
all_values[1]	auto[0]	auto[0]	auto[1]	2056972	1			T28	75		T30	22		T33	471
all_values[1]	auto[0]	auto[1]	auto[0]	229611	1			T28	5		T30	5		T33	58
all_values[1]	auto[0]	auto[1]	auto[1]	2040796	1			T28	61		T30	24		T33	736
all_values[1]	auto[1]	auto[0]	auto[1]	32367	1			T30	5		T1	8		T19	1
all_values[1]	auto[1]	auto[1]	auto[1]	31848	1			T30	4		T1	7		T34	1
all_values[2]	auto[0]	auto[0]	auto[0]	2389260	1			T25	20		T26	103		T27	259
all_values[2]	auto[0]	auto[0]	auto[1]	2056832	1			T28	68		T30	41		T33	331
all_values[2]	auto[0]	auto[1]	auto[0]	229149	1			T28	10		T30	8		T33	122
all_values[2]	auto[0]	auto[1]	auto[1]	2040116	1			T28	59		T30	20		T33	813
all_values[2]	auto[1]	auto[0]	auto[1]	32145	1			T30	1		T1	8		T19	1
all_values[2]	auto[1]	auto[1]	auto[1]	32055	1			T30	3		T1	10		T34	1
all_values[3]	auto[0]	auto[0]	auto[0]	2394504	1			T25	20		T26	103		T27	259
all_values[3]	auto[0]	auto[0]	auto[1]	2047102	1			T28	68		T30	21		T33	860
all_values[3]	auto[0]	auto[1]	auto[0]	229966	1			T28	16		T30	13		T33	36
all_values[3]	auto[0]	auto[1]	auto[1]	2043648	1			T28	69		T30	30		T33	360
all_values[3]	auto[1]	auto[0]	auto[1]	32246	1			T30	5		T1	14		T19	1
all_values[3]	auto[1]	auto[1]	auto[1]	32091	1			T30	4		T1	10		T34	1
all_values[4]	auto[0]	auto[0]	auto[0]	2390682	1			T25	20		T26	103		T27	259
all_values[4]	auto[0]	auto[0]	auto[1]	2054951	1			T28	112		T30	21		T33	609
all_values[4]	auto[0]	auto[1]	auto[0]	231405	1			T28	8		T30	12		T33	41
all_values[4]	auto[0]	auto[1]	auto[1]	2038215	1			T28	32		T30	34		T33	652
all_values[4]	auto[1]	auto[0]	auto[1]	32560	1			T30	5		T1	12		T19	1
all_values[4]	auto[1]	auto[1]	auto[1]	31744	1			T30	3		T1	7		T34	1
all_values[5]	auto[0]	auto[0]	auto[0]	2387431	1			T25	20		T26	103		T27	259
all_values[5]	auto[0]	auto[0]	auto[1]	2040436	1			T28	56		T30	23		T33	585
all_values[5]	auto[0]	auto[1]	auto[0]	229940	1			T28	29		T30	16		T33	45
all_values[5]	auto[0]	auto[1]	auto[1]	2057622	1			T28	61		T30	30		T33	663
all_values[5]	auto[1]	auto[0]	auto[1]	32206	1			T30	6		T1	5		T19	1
all_values[5]	auto[1]	auto[1]	auto[1]	31922	1			T30	4		T1	11		T103	10
all_values[6]	auto[0]	auto[0]	auto[0]	2389395	1			T25	20		T26	103		T27	259
all_values[6]	auto[0]	auto[0]	auto[1]	2055859	1			T28	65		T30	35		T33	656
all_values[6]	auto[0]	auto[1]	auto[0]	233251	1			T28	3		T33	48		T1	5
all_values[6]	auto[0]	auto[1]	auto[1]	2037051	1			T28	78		T30	13		T33	586
all_values[6]	auto[1]	auto[0]	auto[1]	32182	1			T30	4		T1	17		T104	1
all_values[6]	auto[1]	auto[1]	auto[1]	31819	1			T30	3		T1	6		T104	1
all_values[7]	auto[0]	auto[0]	auto[0]	2394592	1			T25	20		T26	103		T27	259
all_values[7]	auto[0]	auto[0]	auto[1]	2035099	1			T28	98		T30	29		T33	418
all_values[7]	auto[0]	auto[1]	auto[0]	233209	1			T28	6		T30	17		T33	72
all_values[7]	auto[0]	auto[1]	auto[1]	2052611	1			T28	32		T30	23		T33	765
all_values[7]	auto[1]	auto[0]	auto[1]	32334	1			T30	6		T1	6		T19	1
all_values[7]	auto[1]	auto[1]	auto[1]	31712	1			T30	2		T1	10		T104	2
all_values[8]	auto[0]	auto[0]	auto[0]	2389137	1			T25	20		T26	103		T27	259
all_values[8]	auto[0]	auto[0]	auto[1]	2059465	1			T28	63		T30	21		T33	988
all_values[8]	auto[0]	auto[1]	auto[0]	230024	1			T28	25		T30	10		T33	11
all_values[8]	auto[0]	auto[1]	auto[1]	2036315	1			T28	62		T30	32		T33	267
all_values[8]	auto[1]	auto[0]	auto[1]	32798	1			T30	5		T1	9		T104	1
all_values[8]	auto[1]	auto[1]	auto[1]	31818	1			T30	2		T1	7		T34	1
all_values[9]	auto[0]	auto[0]	auto[0]	2389239	1			T25	20		T26	103		T27	259
all_values[9]	auto[0]	auto[0]	auto[1]	2039468	1			T28	77		T30	47		T33	599
all_values[9]	auto[0]	auto[1]	auto[0]	232352	1			T28	14		T30	6		T33	50
all_values[9]	auto[0]	auto[1]	auto[1]	2054082	1			T28	65		T30	5		T33	621
all_values[9]	auto[1]	auto[0]	auto[1]	32352	1			T30	3		T1	8		T19	1
all_values[9]	auto[1]	auto[1]	auto[1]	32064	1			T30	2		T1	11		T103	10
all_values[10]	auto[0]	auto[0]	auto[0]	2391757	1			T25	20		T26	103		T27	259
all_values[10]	auto[0]	auto[0]	auto[1]	2068139	1			T28	85		T30	24		T33	435
all_values[10]	auto[0]	auto[1]	auto[0]	232287	1			T28	20		T30	17		T33	32
all_values[10]	auto[0]	auto[1]	auto[1]	2023391	1			T28	49		T30	28		T33	733
all_values[10]	auto[1]	auto[0]	auto[1]	32399	1			T30	3		T1	9		T104	1
all_values[10]	auto[1]	auto[1]	auto[1]	31584	1			T30	2		T1	10		T34	1
all_values[11]	auto[0]	auto[0]	auto[0]	2392305	1			T25	20		T26	103		T27	259
all_values[11]	auto[0]	auto[0]	auto[1]	2061888	1			T28	67		T30	33		T33	572
all_values[11]	auto[0]	auto[1]	auto[0]	232175	1			T28	13		T30	2		T33	106
all_values[11]	auto[0]	auto[1]	auto[1]	2028671	1			T28	73		T30	17		T33	589
all_values[11]	auto[1]	auto[0]	auto[1]	32736	1			T30	7		T1	13		T104	1
all_values[11]	auto[1]	auto[1]	auto[1]	31782	1			T30	1		T1	2		T34	1
all_values[12]	auto[0]	auto[0]	auto[0]	2396941	1			T25	20		T26	103		T27	259
all_values[12]	auto[0]	auto[0]	auto[1]	2048195	1			T28	110		T30	25		T33	555
all_values[12]	auto[0]	auto[1]	auto[0]	230332	1			T30	3		T33	59		T1	13
all_values[12]	auto[0]	auto[1]	auto[1]	2039621	1			T28	51		T30	21		T33	664
all_values[12]	auto[1]	auto[0]	auto[1]	32370	1			T30	5		T1	10		T19	1
all_values[12]	auto[1]	auto[1]	auto[1]	32098	1			T30	3		T1	12		T103	9
all_values[13]	auto[0]	auto[0]	auto[0]	2391572	1			T25	20		T26	103		T27	259
all_values[13]	auto[0]	auto[0]	auto[1]	2046145	1			T28	46		T30	14		T33	608
all_values[13]	auto[0]	auto[1]	auto[0]	230825	1			T28	24		T30	13		T33	73
all_values[13]	auto[0]	auto[1]	auto[1]	2046627	1			T28	84		T30	31		T33	524
all_values[13]	auto[1]	auto[0]	auto[1]	32197	1			T30	4		T1	11		T19	1
all_values[13]	auto[1]	auto[1]	auto[1]	32191	1			T30	4		T1	12		T103	12
all_values[14]	auto[0]	auto[0]	auto[0]	2385198	1			T25	20		T26	103		T27	259
all_values[14]	auto[0]	auto[0]	auto[1]	2055685	1			T28	70		T30	40		T33	791
all_values[14]	auto[0]	auto[1]	auto[0]	227897	1			T28	18		T30	9		T33	34
all_values[14]	auto[0]	auto[1]	auto[1]	2046693	1			T28	56		T30	12		T33	425
all_values[14]	auto[1]	auto[0]	auto[1]	32234	1			T30	6		T1	10		T34	1
all_values[14]	auto[1]	auto[1]	auto[1]	31850	1			T30	3		T1	10		T104	1
all_values[15]	auto[0]	auto[0]	auto[0]	2393342	1			T25	20		T26	103		T27	259
all_values[15]	auto[0]	auto[0]	auto[1]	2057755	1			T28	84		T30	23		T33	530
all_values[15]	auto[0]	auto[1]	auto[0]	231768	1			T28	8		T30	19		T33	105
all_values[15]	auto[0]	auto[1]	auto[1]	2032253	1			T28	69		T30	2		T33	602
all_values[15]	auto[1]	auto[0]	auto[1]	32443	1			T30	5		T1	4		T104	2
all_values[15]	auto[1]	auto[1]	auto[1]	31996	1			T30	2		T1	10		T34	1
all_values[16]	auto[0]	auto[0]	auto[0]	2387203	1			T25	20		T26	103		T27	259
all_values[16]	auto[0]	auto[0]	auto[1]	2057203	1			T28	61		T30	28		T33	325
all_values[16]	auto[0]	auto[1]	auto[0]	231324	1			T28	5		T33	119		T1	15
all_values[16]	auto[0]	auto[1]	auto[1]	2039502	1			T28	90		T30	32		T33	823
all_values[16]	auto[1]	auto[0]	auto[1]	32738	1			T30	4		T1	6		T34	1
all_values[16]	auto[1]	auto[1]	auto[1]	31587	1			T30	3		T1	4		T103	11
all_values[17]	auto[0]	auto[0]	auto[0]	2389833	1			T25	20		T26	103		T27	259
all_values[17]	auto[0]	auto[0]	auto[1]	2062282	1			T28	59		T30	35		T33	525
all_values[17]	auto[0]	auto[1]	auto[0]	229071	1			T28	13		T30	12		T33	56
all_values[17]	auto[0]	auto[1]	auto[1]	2034130	1			T28	83		T30	26		T33	666
all_values[17]	auto[1]	auto[0]	auto[1]	32350	1			T30	5		T1	16		T104	1
all_values[17]	auto[1]	auto[1]	auto[1]	31891	1			T30	2		T1	3		T104	1
all_values[18]	auto[0]	auto[0]	auto[0]	2390796	1			T25	20		T26	103		T27	259
all_values[18]	auto[0]	auto[0]	auto[1]	2044865	1			T28	68		T30	50		T33	869
all_values[18]	auto[0]	auto[1]	auto[0]	229229	1			T28	9		T30	11		T33	18
all_values[18]	auto[0]	auto[1]	auto[1]	2050211	1			T28	34		T30	3		T33	380
all_values[18]	auto[1]	auto[0]	auto[1]	32553	1			T30	6		T1	8		T19	1
all_values[18]	auto[1]	auto[1]	auto[1]	31903	1			T30	1		T1	10		T34	1
all_values[19]	auto[0]	auto[0]	auto[0]	2387026	1			T25	20		T26	103		T27	259
all_values[19]	auto[0]	auto[0]	auto[1]	2052817	1			T28	50		T30	34		T33	558
all_values[19]	auto[0]	auto[1]	auto[0]	231569	1			T28	20		T30	17		T33	27
all_values[19]	auto[0]	auto[1]	auto[1]	2043946	1			T28	84		T30	9		T33	714
all_values[19]	auto[1]	auto[0]	auto[1]	32325	1			T30	2		T1	8		T19	1
all_values[19]	auto[1]	auto[1]	auto[1]	31874	1			T30	2		T1	6		T104	1
all_values[20]	auto[0]	auto[0]	auto[0]	2391183	1			T25	20		T26	103		T27	259
all_values[20]	auto[0]	auto[0]	auto[1]	2051855	1			T28	73		T30	34		T33	676
all_values[20]	auto[0]	auto[1]	auto[0]	230752	1			T28	11		T30	11		T33	30
all_values[20]	auto[0]	auto[1]	auto[1]	2041308	1			T28	71		T30	11		T33	533
all_values[20]	auto[1]	auto[0]	auto[1]	32591	1			T30	2		T1	12		T34	1
all_values[20]	auto[1]	auto[1]	auto[1]	31868	1			T30	2		T1	4		T103	12
all_values[21]	auto[0]	auto[0]	auto[0]	2388390	1			T25	20		T26	103		T27	259
all_values[21]	auto[0]	auto[0]	auto[1]	2058668	1			T28	59		T30	37		T33	429
all_values[21]	auto[0]	auto[1]	auto[0]	234633	1			T28	17		T30	5		T33	73
all_values[21]	auto[0]	auto[1]	auto[1]	2033818	1			T28	81		T30	21		T33	768
all_values[21]	auto[1]	auto[0]	auto[1]	32424	1			T30	4		T1	2		T104	1
all_values[21]	auto[1]	auto[1]	auto[1]	31624	1			T30	3		T1	12		T104	2
all_values[22]	auto[0]	auto[0]	auto[0]	2394663	1			T25	20		T26	103		T27	259
all_values[22]	auto[0]	auto[0]	auto[1]	2058483	1			T28	111		T30	35		T33	735
all_values[22]	auto[0]	auto[1]	auto[0]	232376	1			T28	14		T30	10		T33	73
all_values[22]	auto[0]	auto[1]	auto[1]	2030048	1			T28	34		T30	18		T33	432
all_values[22]	auto[1]	auto[0]	auto[1]	32422	1			T30	7		T1	8		T104	1
all_values[22]	auto[1]	auto[1]	auto[1]	31565	1			T30	2		T1	6		T103	3
all_values[23]	auto[0]	auto[0]	auto[0]	2394138	1			T25	20		T26	103		T27	259
all_values[23]	auto[0]	auto[0]	auto[1]	2048373	1			T28	81		T30	35		T33	340
all_values[23]	auto[0]	auto[1]	auto[0]	232467	1			T28	20		T30	13		T33	45
all_values[23]	auto[0]	auto[1]	auto[1]	2040202	1			T28	41		T30	8		T33	806
all_values[23]	auto[1]	auto[0]	auto[1]	32564	1			T30	7		T1	7		T34	1
all_values[23]	auto[1]	auto[1]	auto[1]	31813	1			T1	14		T103	10		T2	44
all_values[24]	auto[0]	auto[0]	auto[0]	2392742	1			T25	20		T26	103		T27	259
all_values[24]	auto[0]	auto[0]	auto[1]	2046761	1			T28	102		T30	36		T33	761
all_values[24]	auto[0]	auto[1]	auto[0]	232555	1			T28	11		T30	6		T33	33
all_values[24]	auto[0]	auto[1]	auto[1]	2043350	1			T28	40		T30	4		T33	440
all_values[24]	auto[1]	auto[0]	auto[1]	32208	1			T30	4		T1	10		T34	1
all_values[24]	auto[1]	auto[1]	auto[1]	31941	1			T1	10		T103	14		T2	38
all_values[25]	auto[0]	auto[0]	auto[0]	2394786	1			T25	20		T26	103		T27	259
all_values[25]	auto[0]	auto[0]	auto[1]	2034599	1			T28	80		T30	40		T33	688
all_values[25]	auto[0]	auto[1]	auto[0]	233188	1			T28	2		T30	3		T33	49
all_values[25]	auto[0]	auto[1]	auto[1]	2052811	1			T28	74		T30	19		T33	505
all_values[25]	auto[1]	auto[0]	auto[1]	32556	1			T30	4		T1	7		T104	1
all_values[25]	auto[1]	auto[1]	auto[1]	31617	1			T30	2		T1	8		T34	1
all_values[26]	auto[0]	auto[0]	auto[0]	2387293	1			T25	20		T26	103		T27	259
all_values[26]	auto[0]	auto[0]	auto[1]	2037109	1			T28	91		T30	35		T33	565
all_values[26]	auto[0]	auto[1]	auto[0]	229042	1			T28	13		T30	5		T33	51
all_values[26]	auto[0]	auto[1]	auto[1]	2061997	1			T28	31		T30	10		T33	612
all_values[26]	auto[1]	auto[0]	auto[1]	32286	1			T30	1		T1	4		T104	2
all_values[26]	auto[1]	auto[1]	auto[1]	31830	1			T30	2		T1	17		T34	1
all_values[27]	auto[0]	auto[0]	auto[0]	2390083	1			T25	20		T26	103		T27	259
all_values[27]	auto[0]	auto[0]	auto[1]	2054277	1			T28	60		T30	21		T33	584
all_values[27]	auto[0]	auto[1]	auto[0]	232495	1			T28	16		T30	5		T33	36
all_values[27]	auto[0]	auto[1]	auto[1]	2038357	1			T28	88		T30	25		T33	650
all_values[27]	auto[1]	auto[0]	auto[1]	32244	1			T30	5		T1	1		T19	1
all_values[27]	auto[1]	auto[1]	auto[1]	32101	1			T30	2		T1	11		T104	1
all_values[28]	auto[0]	auto[0]	auto[0]	2389104	1			T25	20		T26	103		T27	259
all_values[28]	auto[0]	auto[0]	auto[1]	2055425	1			T28	83		T30	50		T33	621
all_values[28]	auto[0]	auto[1]	auto[0]	233029	1			T28	16		T30	3		T33	27
all_values[28]	auto[0]	auto[1]	auto[1]	2038057	1			T28	50		T30	8		T33	613
all_values[28]	auto[1]	auto[0]	auto[1]	32282	1			T30	4		T1	8		T104	1
all_values[28]	auto[1]	auto[1]	auto[1]	31660	1			T1	14		T104	1		T103	9
all_values[29]	auto[0]	auto[0]	auto[0]	2391474	1			T25	20		T26	103		T27	259
all_values[29]	auto[0]	auto[0]	auto[1]	2045986	1			T28	61		T30	26		T33	480
all_values[29]	auto[0]	auto[1]	auto[0]	230498	1			T28	5		T30	6		T33	54
all_values[29]	auto[0]	auto[1]	auto[1]	2047435	1			T28	81		T30	38		T33	743
all_values[29]	auto[1]	auto[0]	auto[1]	32412	1			T30	2		T1	7		T19	1
all_values[29]	auto[1]	auto[1]	auto[1]	31752	1			T30	4		T1	15		T103	8
all_values[30]	auto[0]	auto[0]	auto[0]	2387251	1			T25	20		T26	103		T27	259
all_values[30]	auto[0]	auto[0]	auto[1]	2048471	1			T28	91		T30	16		T33	354
all_values[30]	auto[0]	auto[1]	auto[0]	232149	1			T30	17		T33	77		T1	16
all_values[30]	auto[0]	auto[1]	auto[1]	2047497	1			T28	44		T30	18		T33	834
all_values[30]	auto[1]	auto[0]	auto[1]	32384	1			T30	3		T1	6		T34	1
all_values[30]	auto[1]	auto[1]	auto[1]	31805	1			T30	4		T1	15		T104	1
all_values[31]	auto[0]	auto[0]	auto[0]	2387947	1			T25	20		T26	103		T27	259
all_values[31]	auto[0]	auto[0]	auto[1]	2043993	1			T28	94		T30	44		T33	919
all_values[31]	auto[0]	auto[1]	auto[0]	233440	1			T28	9		T30	5		T33	32
all_values[31]	auto[0]	auto[1]	auto[1]	2050041	1			T28	32		T30	3		T33	337
all_values[31]	auto[1]	auto[0]	auto[1]	32146	1			T30	4		T1	6		T104	1
all_values[31]	auto[1]	auto[1]	auto[1]	31990	1			T1	9		T34	1		T103	8

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal