Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
data_oe	2	0	2	100.00	100	1	1	2
data_out	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_all	192	0	192	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	11217492	1			T41	379		T42	524		T43	103
bins_for_gpio_bits[1]	11217492	1			T41	379		T42	524		T43	103
bins_for_gpio_bits[2]	11217492	1			T41	379		T42	524		T43	103
bins_for_gpio_bits[3]	11217492	1			T41	379		T42	524		T43	103
bins_for_gpio_bits[4]	11217492	1			T41	379		T42	524		T43	103
bins_for_gpio_bits[5]	11217492	1			T41	379		T42	524		T43	103
bins_for_gpio_bits[6]	11217492	1			T41	379		T42	524		T43	103
bins_for_gpio_bits[7]	11217492	1			T41	379		T42	524		T43	103
bins_for_gpio_bits[8]	11217492	1			T41	379		T42	524		T43	103
bins_for_gpio_bits[9]	11217492	1			T41	379		T42	524		T43	103
bins_for_gpio_bits[10]	11217492	1			T41	379		T42	524		T43	103
bins_for_gpio_bits[11]	11217492	1			T41	379		T42	524		T43	103
bins_for_gpio_bits[12]	11217492	1			T41	379		T42	524		T43	103
bins_for_gpio_bits[13]	11217492	1			T41	379		T42	524		T43	103
bins_for_gpio_bits[14]	11217492	1			T41	379		T42	524		T43	103
bins_for_gpio_bits[15]	11217492	1			T41	379		T42	524		T43	103
bins_for_gpio_bits[16]	11217492	1			T41	379		T42	524		T43	103
bins_for_gpio_bits[17]	11217492	1			T41	379		T42	524		T43	103
bins_for_gpio_bits[18]	11217492	1			T41	379		T42	524		T43	103
bins_for_gpio_bits[19]	11217492	1			T41	379		T42	524		T43	103
bins_for_gpio_bits[20]	11217492	1			T41	379		T42	524		T43	103
bins_for_gpio_bits[21]	11217492	1			T41	379		T42	524		T43	103
bins_for_gpio_bits[22]	11217492	1			T41	379		T42	524		T43	103
bins_for_gpio_bits[23]	11217492	1			T41	379		T42	524		T43	103
bins_for_gpio_bits[24]	11217492	1			T41	379		T42	524		T43	103
bins_for_gpio_bits[25]	11217492	1			T41	379		T42	524		T43	103
bins_for_gpio_bits[26]	11217492	1			T41	379		T42	524		T43	103
bins_for_gpio_bits[27]	11217492	1			T41	379		T42	524		T43	103
bins_for_gpio_bits[28]	11217492	1			T41	379		T42	524		T43	103
bins_for_gpio_bits[29]	11217492	1			T41	379		T42	524		T43	103
bins_for_gpio_bits[30]	11217492	1			T41	379		T42	524		T43	103
bins_for_gpio_bits[31]	11217492	1			T41	379		T42	524		T43	103

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

210860388

1

T41

8156

T42

4738

T43

2666

auto[1]

148099356

1

T41

3972

T42

12030

T43

630

---

Summary for Variable data_oe

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_oe

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

289210084

1

T41

8378

T42

9963

T43

2718

auto[1]

69749660

1

T41

3750

T42

6805

T43

578

---

Summary for Variable data_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

269254585

1

T41

8238

T42

9639

T43

1782

auto[1]

89705159

1

T41

3890

T42

7129

T43

1514

---

Summary for Cross cp_cross_all

Samples crossed: cp_pin data_out data_oe data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_all

Bins

cp_pin	data_out	data_oe	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[0]	4147490	1			T41	122		T42	54		T43	49
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[1]	3166886	1			T41	60		T42	141		T43	4
bins_for_gpio_bits[0]	auto[0]	auto[1]	auto[0]	1095982	1			T41	85		T42	106		T43	20
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[0]	1339238	1			T41	56		T43	19		T44	31
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[1]	379427	1			T42	117		T43	4		T44	4
bins_for_gpio_bits[0]	auto[1]	auto[1]	auto[1]	1088469	1			T41	56		T42	106		T43	7
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[0]	4146927	1			T41	168		T42	42		T43	48
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[1]	3166312	1			T41	60		T42	167		T43	8
bins_for_gpio_bits[1]	auto[0]	auto[1]	auto[0]	1094534	1			T41	35		T42	116		T43	16
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[0]	1341184	1			T41	66		T43	15		T44	45
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[1]	378567	1			T42	107		T43	2		T44	12
bins_for_gpio_bits[1]	auto[1]	auto[1]	auto[1]	1089968	1			T41	50		T42	92		T43	14
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[0]	4153936	1			T41	137		T42	40		T43	42
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[1]	3163680	1			T41	55		T42	153		T44	7
bins_for_gpio_bits[2]	auto[0]	auto[1]	auto[0]	1096642	1			T41	59		T42	115		T43	6
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[0]	1337470	1			T41	90		T43	39		T44	40
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[1]	377628	1			T42	122		T43	6		T44	4
bins_for_gpio_bits[2]	auto[1]	auto[1]	auto[1]	1088136	1			T41	38		T42	94		T43	10
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[0]	4148861	1			T41	121		T42	47		T43	43
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[1]	3166739	1			T41	67		T42	156		T43	6
bins_for_gpio_bits[3]	auto[0]	auto[1]	auto[0]	1100335	1			T41	60		T42	90		T43	25
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[0]	1335986	1			T41	70		T43	20		T44	21
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[1]	378436	1			T42	133		T43	5		T44	3
bins_for_gpio_bits[3]	auto[1]	auto[1]	auto[1]	1087135	1			T41	61		T42	98		T43	4
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[0]	4163502	1			T41	147		T42	42		T43	32
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[1]	3162255	1			T41	65		T42	177		T43	3
bins_for_gpio_bits[4]	auto[0]	auto[1]	auto[0]	1095470	1			T41	83		T42	98		T43	2
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[0]	1334503	1			T41	38		T43	48		T44	25
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[1]	375217	1			T42	113		T43	7		T44	2
bins_for_gpio_bits[4]	auto[1]	auto[1]	auto[1]	1086545	1			T41	46		T42	94		T43	11
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[0]	4150780	1			T41	156		T42	40		T43	34
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[1]	3164918	1			T41	60		T42	143		T43	4
bins_for_gpio_bits[5]	auto[0]	auto[1]	auto[0]	1096359	1			T41	39		T42	94		T43	2
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[0]	1342225	1			T41	82		T43	43		T44	43
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[1]	376641	1			T42	116		T43	5		T44	19
bins_for_gpio_bits[5]	auto[1]	auto[1]	auto[1]	1086569	1			T41	42		T42	131		T43	15
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[0]	4143969	1			T41	118		T42	41		T43	12
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[1]	3172168	1			T41	62		T42	124		T43	1
bins_for_gpio_bits[6]	auto[0]	auto[1]	auto[0]	1096762	1			T41	56		T42	132		T44	8
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[0]	1341783	1			T41	62		T43	58		T44	30
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[1]	378056	1			T42	123		T43	12		T44	17
bins_for_gpio_bits[6]	auto[1]	auto[1]	auto[1]	1084754	1			T41	81		T42	104		T43	20
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[0]	4155560	1			T41	166		T42	43		T43	37
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[1]	3166476	1			T41	60		T42	176		T43	5
bins_for_gpio_bits[7]	auto[0]	auto[1]	auto[0]	1098189	1			T41	70		T42	86		T43	8
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[0]	1333163	1			T41	41		T43	39		T44	65
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[1]	377923	1			T42	112		T43	6		T44	13
bins_for_gpio_bits[7]	auto[1]	auto[1]	auto[1]	1086181	1			T41	42		T42	107		T43	8
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[0]	4150642	1			T41	136		T42	36		T43	36
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[1]	3171202	1			T41	55		T42	153		T43	4
bins_for_gpio_bits[8]	auto[0]	auto[1]	auto[0]	1098267	1			T41	44		T42	136		T43	8
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[0]	1336842	1			T41	64		T43	27		T44	12
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[1]	377258	1			T42	98		T43	5		T44	1
bins_for_gpio_bits[8]	auto[1]	auto[1]	auto[1]	1083281	1			T41	80		T42	101		T43	23
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[0]	4157722	1			T41	107		T42	40		T43	46
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[1]	3159510	1			T41	69		T42	133		T43	3
bins_for_gpio_bits[9]	auto[0]	auto[1]	auto[0]	1098955	1			T41	76		T42	76		T44	4
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[0]	1337203	1			T41	51		T43	42		T44	31
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[1]	376940	1			T42	159		T43	8		T44	9
bins_for_gpio_bits[9]	auto[1]	auto[1]	auto[1]	1087162	1			T41	76		T42	116		T43	4
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[0]	4160396	1			T41	121		T42	49		T43	52
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[1]	3162098	1			T41	69		T42	139		T43	10
bins_for_gpio_bits[10]	auto[0]	auto[1]	auto[0]	1096878	1			T41	53		T42	140		T43	8
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[0]	1335189	1			T41	60		T43	12		T44	49
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[1]	376161	1			T42	92		T43	4		T44	6
bins_for_gpio_bits[10]	auto[1]	auto[1]	auto[1]	1086770	1			T41	76		T42	104		T43	17
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[0]	4148612	1			T41	130		T42	45		T43	77
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[1]	3166829	1			T41	70		T42	130		T43	4
bins_for_gpio_bits[11]	auto[0]	auto[1]	auto[0]	1095343	1			T41	52		T42	102		T43	2
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[0]	1340283	1			T41	66		T43	18		T44	51
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[1]	375496	1			T42	141		T43	2		T44	18
bins_for_gpio_bits[11]	auto[1]	auto[1]	auto[1]	1090929	1			T41	61		T42	106		T44	4
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[0]	4153196	1			T41	123		T42	44		T43	38
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[1]	3162682	1			T41	71		T42	153		T43	9
bins_for_gpio_bits[12]	auto[0]	auto[1]	auto[0]	1097045	1			T41	58		T42	108		T43	8
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[0]	1340246	1			T41	68		T43	36		T44	40
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[1]	377930	1			T42	126		T43	6		T44	4
bins_for_gpio_bits[12]	auto[1]	auto[1]	auto[1]	1086393	1			T41	59		T42	93		T43	6
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[0]	4157438	1			T41	114		T42	46		T43	18
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[1]	3163747	1			T41	68		T42	181		T43	4
bins_for_gpio_bits[13]	auto[0]	auto[1]	auto[0]	1098087	1			T41	65		T42	98		T43	21
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[0]	1336439	1			T41	72		T43	41		T44	14
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[1]	376357	1			T42	129		T43	7		T45	13
bins_for_gpio_bits[13]	auto[1]	auto[1]	auto[1]	1085424	1			T41	60		T42	70		T43	12
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[0]	4148084	1			T41	151		T42	43		T43	56
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[1]	3168357	1			T41	55		T42	162		T43	4
bins_for_gpio_bits[14]	auto[0]	auto[1]	auto[0]	1101701	1			T41	49		T42	104		T43	2
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[0]	1331329	1			T41	76		T43	38		T44	62
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[1]	378212	1			T42	99		T43	3		T44	16
bins_for_gpio_bits[14]	auto[1]	auto[1]	auto[1]	1089809	1			T41	48		T42	116		T44	22
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[0]	4144690	1			T41	157		T42	39		T43	31
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[1]	3172804	1			T41	65		T42	128		T43	7
bins_for_gpio_bits[15]	auto[0]	auto[1]	auto[0]	1093582	1			T41	57		T42	106		T43	15
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[0]	1337662	1			T41	52		T43	30		T44	27
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[1]	378260	1			T42	105		T43	6		T44	8
bins_for_gpio_bits[15]	auto[1]	auto[1]	auto[1]	1090494	1			T41	48		T42	146		T43	14
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[0]	4164638	1			T41	112		T42	41		T43	38
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[1]	3161793	1			T41	70		T42	141		T43	5
bins_for_gpio_bits[16]	auto[0]	auto[1]	auto[0]	1089304	1			T41	74		T42	70		T43	8
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[0]	1343785	1			T41	61		T43	45		T44	1
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[1]	379609	1			T42	146		T43	3		T44	1
bins_for_gpio_bits[16]	auto[1]	auto[1]	auto[1]	1078363	1			T41	62		T42	126		T43	4
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[0]	4152315	1			T41	109		T42	41		T43	59
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[1]	3164547	1			T41	76		T42	166		T43	13
bins_for_gpio_bits[17]	auto[0]	auto[1]	auto[0]	1089107	1			T41	70		T42	90		T43	31
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[0]	1344153	1			T41	50		T44	32		T45	95
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[1]	382490	1			T42	129		T44	10		T45	7
bins_for_gpio_bits[17]	auto[1]	auto[1]	auto[1]	1084880	1			T41	74		T42	98		T44	15
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[0]	4172266	1			T41	139		T42	39		T43	31
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[1]	3151765	1			T41	65		T42	162		T43	5
bins_for_gpio_bits[18]	auto[0]	auto[1]	auto[0]	1089154	1			T41	64		T42	80		T43	4
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[0]	1341229	1			T41	63		T43	49		T44	19
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[1]	377990	1			T42	114		T43	4		T44	9
bins_for_gpio_bits[18]	auto[1]	auto[1]	auto[1]	1085088	1			T41	48		T42	129		T43	10
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[0]	4161626	1			T41	144		T42	45		T43	27
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[1]	3158378	1			T41	70		T42	146		T43	10
bins_for_gpio_bits[19]	auto[0]	auto[1]	auto[0]	1094197	1			T41	61		T42	85		T43	6
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[0]	1340876	1			T41	52		T43	29		T44	46
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[1]	379468	1			T42	128		T43	5		T44	9
bins_for_gpio_bits[19]	auto[1]	auto[1]	auto[1]	1082947	1			T41	52		T42	120		T43	26
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[0]	4175835	1			T41	132		T42	33		T43	42
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[1]	3156090	1			T41	68		T42	179		T43	4
bins_for_gpio_bits[20]	auto[0]	auto[1]	auto[0]	1094289	1			T41	39		T42	120		T44	11
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[0]	1334588	1			T41	86		T43	43		T44	28
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[1]	380601	1			T42	80		T43	12		T44	13
bins_for_gpio_bits[20]	auto[1]	auto[1]	auto[1]	1076089	1			T41	54		T42	112		T43	2
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[0]	4145502	1			T41	162		T42	37		T43	41
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[1]	3172297	1			T41	70		T42	165		T43	3
bins_for_gpio_bits[21]	auto[0]	auto[1]	auto[0]	1091887	1			T41	56		T42	122		T44	7
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[0]	1343839	1			T41	54		T43	52		T44	32
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[1]	381087	1			T42	122		T43	7		T44	12
bins_for_gpio_bits[21]	auto[1]	auto[1]	auto[1]	1082880	1			T41	37		T42	78		T44	9
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[0]	4154190	1			T41	137		T42	46		T43	47
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[1]	3163211	1			T41	67		T42	155		T43	8
bins_for_gpio_bits[22]	auto[0]	auto[1]	auto[0]	1090473	1			T41	79		T42	127		T43	12
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[0]	1345922	1			T41	38		T43	20		T44	61
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[1]	378153	1			T42	106		T43	3		T44	18
bins_for_gpio_bits[22]	auto[1]	auto[1]	auto[1]	1085543	1			T41	58		T42	90		T43	13
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[0]	4149351	1			T41	118		T42	39		T43	25
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[1]	3170399	1			T41	68		T42	154		T43	1
bins_for_gpio_bits[23]	auto[0]	auto[1]	auto[0]	1098175	1			T41	42		T42	136		T43	6
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[0]	1339706	1			T41	84		T43	55		T44	61
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[1]	377350	1			T42	98		T43	10		T44	17
bins_for_gpio_bits[23]	auto[1]	auto[1]	auto[1]	1082511	1			T41	67		T42	97		T43	6
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[0]	4154547	1			T41	126		T42	44		T43	24
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[1]	3168652	1			T41	66		T42	141		T43	7
bins_for_gpio_bits[24]	auto[0]	auto[1]	auto[0]	1089263	1			T41	40		T42	88		T43	13
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[0]	1344997	1			T41	70		T43	49		T44	68
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[1]	379363	1			T42	123		T43	4		T44	19
bins_for_gpio_bits[24]	auto[1]	auto[1]	auto[1]	1080670	1			T41	77		T42	128		T43	6
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[0]	4159567	1			T41	117		T42	42		T43	32
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[1]	3167410	1			T41	67		T42	128		T43	5
bins_for_gpio_bits[25]	auto[0]	auto[1]	auto[0]	1090961	1			T41	67		T42	94		T43	18
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[0]	1344998	1			T41	74		T43	29		T44	58
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[1]	378686	1			T42	126		T43	8		T44	14
bins_for_gpio_bits[25]	auto[1]	auto[1]	auto[1]	1075870	1			T41	54		T42	134		T43	11
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[0]	4150749	1			T41	130		T42	49		T43	47
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[1]	3163885	1			T41	73		T42	164		T43	9
bins_for_gpio_bits[26]	auto[0]	auto[1]	auto[0]	1090838	1			T41	56		T42	123		T43	18
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[0]	1347804	1			T41	52		T43	23		T44	45
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[1]	377257	1			T42	86		T43	6		T44	6
bins_for_gpio_bits[26]	auto[1]	auto[1]	auto[1]	1086959	1			T41	68		T42	102		T44	4
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[0]	4153759	1			T41	148		T42	53		T43	44
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[1]	3164383	1			T41	62		T42	140		T43	10
bins_for_gpio_bits[27]	auto[0]	auto[1]	auto[0]	1094456	1			T41	46		T42	96		T43	12
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[0]	1340975	1			T41	81		T43	22		T44	21
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[1]	378257	1			T42	106		T43	7		T44	7
bins_for_gpio_bits[27]	auto[1]	auto[1]	auto[1]	1085662	1			T41	42		T42	129		T43	8
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[0]	4158178	1			T41	136		T42	42		T43	56
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[1]	3165101	1			T41	58		T42	171		T43	7
bins_for_gpio_bits[28]	auto[0]	auto[1]	auto[0]	1091080	1			T41	89		T42	88		T43	12
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[0]	1336969	1			T41	44		T43	20		T44	62
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[1]	378402	1			T42	94		T43	4		T44	23
bins_for_gpio_bits[28]	auto[1]	auto[1]	auto[1]	1087762	1			T41	52		T42	129		T43	4
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[0]	4156949	1			T41	123		T42	44		T43	62
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[1]	3157946	1			T41	69		T42	161		T43	5
bins_for_gpio_bits[29]	auto[0]	auto[1]	auto[0]	1095035	1			T41	44		T42	112		T43	5
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[0]	1344547	1			T41	67		T43	19		T44	42
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[1]	378657	1			T42	95		T43	6		T44	9
bins_for_gpio_bits[29]	auto[1]	auto[1]	auto[1]	1084358	1			T41	76		T42	112		T43	6
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[0]	4160851	1			T41	119		T42	38		T43	64
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[1]	3164462	1			T41	67		T42	163		T43	7
bins_for_gpio_bits[30]	auto[0]	auto[1]	auto[0]	1092738	1			T41	57		T42	96		T43	6
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[0]	1338831	1			T41	80		T43	14		T44	55
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[1]	379731	1			T42	134		T44	10		T45	5
bins_for_gpio_bits[30]	auto[1]	auto[1]	auto[1]	1080879	1			T41	56		T42	93		T43	12
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[0]	4151795	1			T41	128		T42	52		T43	16
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[1]	3164244	1			T41	76		T42	149		T43	3
bins_for_gpio_bits[31]	auto[0]	auto[1]	auto[0]	1094348	1			T41	56		T42	128		T43	4
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[0]	1343065	1			T41	51		T43	68		T44	38
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[1]	382296	1			T42	107		T43	5		T44	7
bins_for_gpio_bits[31]	auto[1]	auto[1]	auto[1]	1081744	1			T41	68		T42	88		T43	7

User Defined Cross Bins for cp_cross_all

Excluded/Illegal bins

NAME	COUNT	STATUS
data_oe_1_data_out_0_data_in_1	0	Illegal
data_oe_1_data_out_1_data_in_0	0	Illegal