Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/gpio-sim-vcs/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
data_oe	2	0	2	100.00	100	1	1	2
data_out	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_all	192	0	192	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	6723450	1			T25	44		T26	201		T27	345
bins_for_gpio_bits[1]	6723450	1			T25	44		T26	201		T27	345
bins_for_gpio_bits[2]	6723450	1			T25	44		T26	201		T27	345
bins_for_gpio_bits[3]	6723450	1			T25	44		T26	201		T27	345
bins_for_gpio_bits[4]	6723450	1			T25	44		T26	201		T27	345
bins_for_gpio_bits[5]	6723450	1			T25	44		T26	201		T27	345
bins_for_gpio_bits[6]	6723450	1			T25	44		T26	201		T27	345
bins_for_gpio_bits[7]	6723450	1			T25	44		T26	201		T27	345
bins_for_gpio_bits[8]	6723450	1			T25	44		T26	201		T27	345
bins_for_gpio_bits[9]	6723450	1			T25	44		T26	201		T27	345
bins_for_gpio_bits[10]	6723450	1			T25	44		T26	201		T27	345
bins_for_gpio_bits[11]	6723450	1			T25	44		T26	201		T27	345
bins_for_gpio_bits[12]	6723450	1			T25	44		T26	201		T27	345
bins_for_gpio_bits[13]	6723450	1			T25	44		T26	201		T27	345
bins_for_gpio_bits[14]	6723450	1			T25	44		T26	201		T27	345
bins_for_gpio_bits[15]	6723450	1			T25	44		T26	201		T27	345
bins_for_gpio_bits[16]	6723450	1			T25	44		T26	201		T27	345
bins_for_gpio_bits[17]	6723450	1			T25	44		T26	201		T27	345
bins_for_gpio_bits[18]	6723450	1			T25	44		T26	201		T27	345
bins_for_gpio_bits[19]	6723450	1			T25	44		T26	201		T27	345
bins_for_gpio_bits[20]	6723450	1			T25	44		T26	201		T27	345
bins_for_gpio_bits[21]	6723450	1			T25	44		T26	201		T27	345
bins_for_gpio_bits[22]	6723450	1			T25	44		T26	201		T27	345
bins_for_gpio_bits[23]	6723450	1			T25	44		T26	201		T27	345
bins_for_gpio_bits[24]	6723450	1			T25	44		T26	201		T27	345
bins_for_gpio_bits[25]	6723450	1			T25	44		T26	201		T27	345
bins_for_gpio_bits[26]	6723450	1			T25	44		T26	201		T27	345
bins_for_gpio_bits[27]	6723450	1			T25	44		T26	201		T27	345
bins_for_gpio_bits[28]	6723450	1			T25	44		T26	201		T27	345
bins_for_gpio_bits[29]	6723450	1			T25	44		T26	201		T27	345
bins_for_gpio_bits[30]	6723450	1			T25	44		T26	201		T27	345
bins_for_gpio_bits[31]	6723450	1			T25	44		T26	201		T27	345

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

111516648

1

T25

247

T26

5191

T27

6942

auto[1]

103633752

1

T25

1161

T26

1241

T27

4098

---

Summary for Variable data_oe

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_oe

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

178366620

1

T25

1176

T26

4804

T27

8267

auto[1]

36783780

1

T25

232

T26

1628

T27

2773

---

Summary for Variable data_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

167570164

1

T25

738

T26

3108

T27

8266

auto[1]

47580236

1

T25

670

T26

3324

T27

2774

---

Summary for Cross cp_cross_all

Samples crossed: cp_pin data_out data_oe data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_all

Bins

cp_pin	data_out	data_oe	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[0]	2385990	1			T26	96		T27	134		T28	35
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[1]	2272455	1			T25	8		T26	6		T27	80
bins_for_gpio_bits[0]	auto[0]	auto[1]	auto[0]	573685	1			T25	4		T26	32		T27	44
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[0]	521318	1			T25	1		T26	39		T27	55
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[1]	396633	1			T25	25		T26	4		T29	250
bins_for_gpio_bits[0]	auto[1]	auto[1]	auto[1]	573369	1			T25	6		T26	24		T27	32
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[0]	2384078	1			T25	1		T26	95		T27	124
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[1]	2274674	1			T25	20		T26	7		T27	90
bins_for_gpio_bits[1]	auto[0]	auto[1]	auto[0]	580527	1			T25	11		T26	19		T27	44
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[0]	514705	1			T26	61		T27	47		T29	25
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[1]	397722	1			T25	8		T26	1		T29	180
bins_for_gpio_bits[1]	auto[1]	auto[1]	auto[1]	571744	1			T25	4		T26	18		T27	40
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[0]	2391174	1			T25	2		T26	50		T27	119
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[1]	2269049	1			T25	25		T26	4		T27	91
bins_for_gpio_bits[2]	auto[0]	auto[1]	auto[0]	580550	1			T26	15		T27	48		T29	58
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[0]	513557	1			T26	85		T27	38		T29	34
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[1]	398021	1			T25	17		T26	6		T29	278
bins_for_gpio_bits[2]	auto[1]	auto[1]	auto[1]	571099	1			T26	41		T27	49		T29	87
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[0]	2392445	1			T25	1		T26	53		T27	120
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[1]	2263582	1			T25	7		T26	2		T27	80
bins_for_gpio_bits[3]	auto[0]	auto[1]	auto[0]	579242	1			T25	2		T26	20		T27	45
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[0]	518918	1			T25	2		T26	88		T27	48
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[1]	398106	1			T25	30		T26	5		T29	229
bins_for_gpio_bits[3]	auto[1]	auto[1]	auto[1]	571157	1			T25	2		T26	33		T27	52
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[0]	2391349	1			T26	97		T27	145		T28	45
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[1]	2267418	1			T25	18		T26	12		T27	69
bins_for_gpio_bits[4]	auto[0]	auto[1]	auto[0]	576511	1			T25	4		T26	18		T27	44
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[0]	516280	1			T25	7		T26	48		T27	46
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[1]	397322	1			T25	13		T26	2		T29	267
bins_for_gpio_bits[4]	auto[1]	auto[1]	auto[1]	574570	1			T25	2		T26	24		T27	41
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[0]	2384571	1			T26	69		T27	139		T28	32
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[1]	2271884	1			T25	12		T26	5		T27	93
bins_for_gpio_bits[5]	auto[0]	auto[1]	auto[0]	579310	1			T26	34		T27	26		T29	90
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[0]	515158	1			T25	3		T26	60		T27	48
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[1]	397107	1			T25	25		T26	4		T29	264
bins_for_gpio_bits[5]	auto[1]	auto[1]	auto[1]	575420	1			T25	4		T26	29		T27	39
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[0]	2386502	1			T25	1		T26	109		T27	126
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[1]	2266620	1			T25	6		T26	11		T27	84
bins_for_gpio_bits[6]	auto[0]	auto[1]	auto[0]	575735	1			T26	12		T27	40		T29	121
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[0]	519778	1			T25	4		T26	62		T27	54
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[1]	400113	1			T25	29		T26	1		T29	199
bins_for_gpio_bits[6]	auto[1]	auto[1]	auto[1]	574702	1			T25	4		T26	6		T27	41
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[0]	2390752	1			T25	1		T26	73		T27	114
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[1]	2270166	1			T25	25		T26	8		T27	88
bins_for_gpio_bits[7]	auto[0]	auto[1]	auto[0]	579354	1			T26	31		T27	48		T29	78
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[0]	511576	1			T25	4		T26	53		T27	38
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[1]	395520	1			T25	14		T26	5		T29	266
bins_for_gpio_bits[7]	auto[1]	auto[1]	auto[1]	576082	1			T26	31		T27	57		T29	104
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[0]	2392406	1			T25	4		T26	74		T27	105
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[1]	2259273	1			T25	21		T26	7		T27	107
bins_for_gpio_bits[8]	auto[0]	auto[1]	auto[0]	580497	1			T26	29		T27	49		T29	107
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[0]	515172	1			T25	1		T26	80		T27	48
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[1]	400891	1			T25	18		T26	3		T29	171
bins_for_gpio_bits[8]	auto[1]	auto[1]	auto[1]	575211	1			T26	8		T27	36		T29	90
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[0]	2385720	1			T26	23		T27	120		T28	46
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[1]	2273954	1			T25	22		T27	96		T28	43
bins_for_gpio_bits[9]	auto[0]	auto[1]	auto[0]	578349	1			T26	16		T27	46		T29	98
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[0]	515407	1			T25	2		T26	98		T27	53
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[1]	397139	1			T25	20		T26	9		T29	251
bins_for_gpio_bits[9]	auto[1]	auto[1]	auto[1]	572881	1			T26	55		T27	30		T29	73
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[0]	2403634	1			T26	61		T27	123		T28	38
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[1]	2254154	1			T25	15		T26	5		T27	87
bins_for_gpio_bits[10]	auto[0]	auto[1]	auto[0]	580714	1			T25	7		T26	24		T27	51
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[0]	517643	1			T25	4		T26	81		T27	38
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[1]	396000	1			T25	12		T26	6		T29	306
bins_for_gpio_bits[10]	auto[1]	auto[1]	auto[1]	571305	1			T25	6		T26	24		T27	46
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[0]	2391005	1			T25	1		T26	97		T27	124
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[1]	2268167	1			T25	19		T26	8		T27	86
bins_for_gpio_bits[11]	auto[0]	auto[1]	auto[0]	579202	1			T25	13		T26	37		T27	44
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[0]	515668	1			T25	1		T26	41		T27	43
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[1]	397550	1			T25	4		T26	2		T29	267
bins_for_gpio_bits[11]	auto[1]	auto[1]	auto[1]	571858	1			T25	6		T26	16		T27	48
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[0]	2387336	1			T25	5		T26	56		T27	119
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[1]	2270423	1			T25	19		T26	5		T27	91
bins_for_gpio_bits[12]	auto[0]	auto[1]	auto[0]	576878	1			T25	13		T26	16		T27	59
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[0]	516758	1			T26	82		T27	34		T29	18
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[1]	398644	1			T25	1		T26	4		T29	177
bins_for_gpio_bits[12]	auto[1]	auto[1]	auto[1]	573411	1			T25	6		T26	38		T27	42
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[0]	2393154	1			T25	4		T26	81		T27	121
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[1]	2264563	1			T25	16		T26	7		T27	79
bins_for_gpio_bits[13]	auto[0]	auto[1]	auto[0]	577656	1			T25	9		T26	27		T27	37
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[0]	515428	1			T26	72		T27	36		T29	21
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[1]	400224	1			T25	15		T26	4		T29	140
bins_for_gpio_bits[13]	auto[1]	auto[1]	auto[1]	572425	1			T26	10		T27	72		T29	91
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[0]	2389273	1			T25	7		T26	87		T27	143
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[1]	2269821	1			T25	30		T26	10		T27	86
bins_for_gpio_bits[14]	auto[0]	auto[1]	auto[0]	576614	1			T25	2		T26	37		T27	52
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[0]	517157	1			T26	50		T27	32		T29	19
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[1]	396927	1			T25	3		T26	1		T29	189
bins_for_gpio_bits[14]	auto[1]	auto[1]	auto[1]	573658	1			T25	2		T26	16		T27	32
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[0]	2383261	1			T25	4		T26	79		T27	114
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[1]	2276439	1			T25	7		T26	3		T27	86
bins_for_gpio_bits[15]	auto[0]	auto[1]	auto[0]	580779	1			T25	4		T26	28		T27	70
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[0]	516468	1			T25	3		T26	72		T27	36
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[1]	395617	1			T25	15		T26	7		T29	278
bins_for_gpio_bits[15]	auto[1]	auto[1]	auto[1]	570886	1			T25	11		T26	12		T27	39
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[0]	2386068	1			T26	83		T27	134		T28	54
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[1]	2270293	1			T25	5		T26	3		T27	78
bins_for_gpio_bits[16]	auto[0]	auto[1]	auto[0]	574611	1			T25	2		T26	21		T27	45
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[0]	519467	1			T25	4		T26	63		T27	36
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[1]	400667	1			T25	13		T26	3		T29	214
bins_for_gpio_bits[16]	auto[1]	auto[1]	auto[1]	572344	1			T25	20		T26	28		T27	52
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[0]	2403888	1			T26	64		T27	137		T28	39
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[1]	2260612	1			T25	15		T26	4		T27	87
bins_for_gpio_bits[17]	auto[0]	auto[1]	auto[0]	578608	1			T25	2		T26	31		T27	33
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[0]	513256	1			T25	2		T26	77		T27	52
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[1]	395068	1			T25	20		T26	10		T29	224
bins_for_gpio_bits[17]	auto[1]	auto[1]	auto[1]	572018	1			T25	5		T26	15		T27	36
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[0]	2381584	1			T26	113		T27	156		T28	54
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[1]	2274410	1			T25	21		T26	7		T27	76
bins_for_gpio_bits[18]	auto[0]	auto[1]	auto[0]	577378	1			T25	6		T26	26		T27	46
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[0]	517738	1			T25	6		T26	37		T27	33
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[1]	397939	1			T25	9		T26	3		T29	229
bins_for_gpio_bits[18]	auto[1]	auto[1]	auto[1]	574401	1			T25	2		T26	15		T27	34
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[0]	2398663	1			T26	85		T27	138		T28	47
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[1]	2263005	1			T25	11		T26	8		T27	91
bins_for_gpio_bits[19]	auto[0]	auto[1]	auto[0]	577290	1			T26	26		T27	40		T29	103
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[0]	516524	1			T25	3		T26	48		T27	32
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[1]	396597	1			T25	30		T26	5		T29	214
bins_for_gpio_bits[19]	auto[1]	auto[1]	auto[1]	571371	1			T26	29		T27	44		T29	82
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[0]	2382385	1			T25	4		T26	57		T27	127
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[1]	2279378	1			T25	23		T26	5		T27	88
bins_for_gpio_bits[20]	auto[0]	auto[1]	auto[0]	577180	1			T26	36		T27	50		T29	115
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[0]	515036	1			T25	1		T26	62		T27	46
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[1]	398102	1			T25	12		T26	5		T29	263
bins_for_gpio_bits[20]	auto[1]	auto[1]	auto[1]	571369	1			T25	4		T26	36		T27	34
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[0]	2396256	1			T26	32		T27	130		T28	31
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[1]	2267777	1			T25	11		T26	2		T27	86
bins_for_gpio_bits[21]	auto[0]	auto[1]	auto[0]	574999	1			T25	4		T26	6		T27	54
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[0]	518709	1			T25	4		T26	91		T27	36
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[1]	396154	1			T25	14		T26	7		T29	194
bins_for_gpio_bits[21]	auto[1]	auto[1]	auto[1]	569555	1			T25	11		T26	63		T27	39
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[0]	2384298	1			T25	3		T26	25		T27	124
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[1]	2274639	1			T25	21		T26	3		T27	76
bins_for_gpio_bits[22]	auto[0]	auto[1]	auto[0]	577225	1			T25	4		T26	22		T27	66
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[0]	518373	1			T25	1		T26	96		T27	41
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[1]	398425	1			T25	15		T26	8		T29	186
bins_for_gpio_bits[22]	auto[1]	auto[1]	auto[1]	570490	1			T26	47		T27	38		T29	133
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[0]	2402516	1			T26	79		T27	142		T28	42
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[1]	2263113	1			T25	28		T26	6		T27	73
bins_for_gpio_bits[23]	auto[0]	auto[1]	auto[0]	574678	1			T25	4		T26	44		T27	26
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[0]	515936	1			T25	4		T26	46		T27	58
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[1]	397517	1			T25	8		T26	4		T29	270
bins_for_gpio_bits[23]	auto[1]	auto[1]	auto[1]	569690	1			T26	22		T27	46		T29	106
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[0]	2400290	1			T25	5		T26	79		T27	113
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[1]	2258817	1			T25	14		T26	4		T27	85
bins_for_gpio_bits[24]	auto[0]	auto[1]	auto[0]	574741	1			T25	11		T26	20		T27	36
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[0]	517960	1			T26	57		T27	79		T29	26
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[1]	398377	1			T25	14		T26	9		T29	224
bins_for_gpio_bits[24]	auto[1]	auto[1]	auto[1]	573265	1			T26	32		T27	32		T29	63
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[0]	2399928	1			T25	4		T26	88		T27	136
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[1]	2264669	1			T25	13		T26	8		T27	85
bins_for_gpio_bits[25]	auto[0]	auto[1]	auto[0]	576541	1			T25	6		T26	10		T27	32
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[0]	514347	1			T26	51		T27	44		T29	18
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[1]	397090	1			T25	12		T26	5		T29	245
bins_for_gpio_bits[25]	auto[1]	auto[1]	auto[1]	570875	1			T25	9		T26	39		T27	48
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[0]	2388939	1			T25	1		T26	36		T27	134
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[1]	2268276	1			T25	19		T26	4		T27	92
bins_for_gpio_bits[26]	auto[0]	auto[1]	auto[0]	574478	1			T26	2		T27	48		T29	66
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[0]	519113	1			T25	1		T26	104		T27	39
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[1]	398990	1			T25	23		T26	9		T29	256
bins_for_gpio_bits[26]	auto[1]	auto[1]	auto[1]	573654	1			T26	46		T27	32		T29	110
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[0]	2386420	1			T25	1		T26	76		T27	98
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[1]	2278540	1			T25	17		T26	3		T27	92
bins_for_gpio_bits[27]	auto[0]	auto[1]	auto[0]	573583	1			T26	12		T27	44		T29	95
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[0]	515885	1			T25	3		T26	80		T27	46
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[1]	397726	1			T25	19		T26	2		T29	233
bins_for_gpio_bits[27]	auto[1]	auto[1]	auto[1]	571296	1			T25	4		T26	28		T27	65
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[0]	2397910	1			T26	49		T27	118		T28	41
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[1]	2264277	1			T25	22		T26	5		T27	90
bins_for_gpio_bits[28]	auto[0]	auto[1]	auto[0]	574916	1			T26	4		T27	34		T29	79
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[0]	516366	1			T25	4		T26	97		T27	40
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[1]	399674	1			T25	18		T26	5		T29	285
bins_for_gpio_bits[28]	auto[1]	auto[1]	auto[1]	570307	1			T26	41		T27	63		T29	108
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[0]	2388183	1			T26	46		T27	162		T28	51
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[1]	2272203	1			T25	27		T26	2		T27	78
bins_for_gpio_bits[29]	auto[0]	auto[1]	auto[0]	571263	1			T26	21		T27	33		T29	87
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[0]	522050	1			T25	4		T26	82		T27	52
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[1]	396892	1			T25	9		T26	12		T29	237
bins_for_gpio_bits[29]	auto[1]	auto[1]	auto[1]	572859	1			T25	4		T26	38		T27	20
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[0]	2386234	1			T26	49		T27	122		T28	51
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[1]	2270111	1			T25	28		T26	5		T27	93
bins_for_gpio_bits[30]	auto[0]	auto[1]	auto[0]	578188	1			T25	4		T26	15		T27	34
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[0]	517004	1			T25	5		T26	112		T27	50
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[1]	398828	1			T25	7		T26	2		T29	274
bins_for_gpio_bits[30]	auto[1]	auto[1]	auto[1]	573085	1			T26	18		T27	46		T29	90
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[0]	2399437	1			T26	58		T27	140		T28	44
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[1]	2264587	1			T25	24		T26	5		T27	82
bins_for_gpio_bits[31]	auto[0]	auto[1]	auto[0]	575884	1			T25	8		T26	24		T27	52
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[0]	515078	1			T25	4		T26	82		T27	43
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[1]	398207	1			T25	8		T26	1		T29	218
bins_for_gpio_bits[31]	auto[1]	auto[1]	auto[1]	570257	1			T26	31		T27	28		T29	44

User Defined Cross Bins for cp_cross_all

Excluded/Illegal bins

NAME	COUNT	STATUS
data_oe_1_data_out_0_data_in_1	0	Illegal
data_oe_1_data_out_1_data_in_0	0	Illegal