Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
gpio_value	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_pins_data_in	128	0	128	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	15572965	1			T23	38182		T24	2322		T25	1259
bins_for_gpio_bits[1]	15572965	1			T23	38182		T24	2322		T25	1259
bins_for_gpio_bits[2]	15572965	1			T23	38182		T24	2322		T25	1259
bins_for_gpio_bits[3]	15572965	1			T23	38182		T24	2322		T25	1259
bins_for_gpio_bits[4]	15572965	1			T23	38182		T24	2322		T25	1259
bins_for_gpio_bits[5]	15572965	1			T23	38182		T24	2322		T25	1259
bins_for_gpio_bits[6]	15572965	1			T23	38182		T24	2322		T25	1259
bins_for_gpio_bits[7]	15572965	1			T23	38182		T24	2322		T25	1259
bins_for_gpio_bits[8]	15572965	1			T23	38182		T24	2322		T25	1259
bins_for_gpio_bits[9]	15572965	1			T23	38182		T24	2322		T25	1259
bins_for_gpio_bits[10]	15572965	1			T23	38182		T24	2322		T25	1259
bins_for_gpio_bits[11]	15572965	1			T23	38182		T24	2322		T25	1259
bins_for_gpio_bits[12]	15572965	1			T23	38182		T24	2322		T25	1259
bins_for_gpio_bits[13]	15572965	1			T23	38182		T24	2322		T25	1259
bins_for_gpio_bits[14]	15572965	1			T23	38182		T24	2322		T25	1259
bins_for_gpio_bits[15]	15572965	1			T23	38182		T24	2322		T25	1259
bins_for_gpio_bits[16]	15572965	1			T23	38182		T24	2322		T25	1259
bins_for_gpio_bits[17]	15572965	1			T23	38182		T24	2322		T25	1259
bins_for_gpio_bits[18]	15572965	1			T23	38182		T24	2322		T25	1259
bins_for_gpio_bits[19]	15572965	1			T23	38182		T24	2322		T25	1259
bins_for_gpio_bits[20]	15572965	1			T23	38182		T24	2322		T25	1259
bins_for_gpio_bits[21]	15572965	1			T23	38182		T24	2322		T25	1259
bins_for_gpio_bits[22]	15572965	1			T23	38182		T24	2322		T25	1259
bins_for_gpio_bits[23]	15572965	1			T23	38182		T24	2322		T25	1259
bins_for_gpio_bits[24]	15572965	1			T23	38182		T24	2322		T25	1259
bins_for_gpio_bits[25]	15572965	1			T23	38182		T24	2322		T25	1259
bins_for_gpio_bits[26]	15572965	1			T23	38182		T24	2322		T25	1259
bins_for_gpio_bits[27]	15572965	1			T23	38182		T24	2322		T25	1259
bins_for_gpio_bits[28]	15572965	1			T23	38182		T24	2322		T25	1259
bins_for_gpio_bits[29]	15572965	1			T23	38182		T24	2322		T25	1259
bins_for_gpio_bits[30]	15572965	1			T23	38182		T24	2322		T25	1259
bins_for_gpio_bits[31]	15572965	1			T23	38182		T24	2322		T25	1259

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

299803664

1

T23

613362

T24

37067

T25

20023

auto[1]

198531216

1

T23

608462

T24

37237

T25

20265

---

Summary for Variable gpio_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for gpio_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

299795660

1

T23

613362

T24

37067

T25

20023

auto[1]

198539220

1

T23

608462

T24

37237

T25

20265

---

Summary for Cross cp_cross_pins_data_in

Samples crossed: cp_pin gpio_value data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_cross_pins_data_in

Bins

cp_pin	gpio_value	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	9082766	1			T23	19410		T24	1227		T25	584
bins_for_gpio_bits[0]	auto[0]	auto[1]	272894	1			T27	46		T28	22		T29	1
bins_for_gpio_bits[0]	auto[1]	auto[0]	273159	1			T27	46		T28	22		T31	2
bins_for_gpio_bits[0]	auto[1]	auto[1]	5944146	1			T23	18772		T24	1095		T25	675
bins_for_gpio_bits[1]	auto[0]	auto[0]	9092337	1			T23	17966		T24	1156		T25	622
bins_for_gpio_bits[1]	auto[0]	auto[1]	271877	1			T27	46		T28	21		T31	4
bins_for_gpio_bits[1]	auto[1]	auto[0]	272110	1			T27	46		T28	21		T31	4
bins_for_gpio_bits[1]	auto[1]	auto[1]	5936641	1			T23	20216		T24	1166		T25	637
bins_for_gpio_bits[2]	auto[0]	auto[0]	9094479	1			T23	17915		T24	1170		T25	657
bins_for_gpio_bits[2]	auto[0]	auto[1]	271486	1			T27	37		T28	19		T29	1
bins_for_gpio_bits[2]	auto[1]	auto[0]	271734	1			T27	37		T28	19		T29	1
bins_for_gpio_bits[2]	auto[1]	auto[1]	5935266	1			T23	20267		T24	1152		T25	602
bins_for_gpio_bits[3]	auto[0]	auto[0]	9107781	1			T23	21018		T24	1122		T25	687
bins_for_gpio_bits[3]	auto[0]	auto[1]	271357	1			T27	47		T28	25		T29	2
bins_for_gpio_bits[3]	auto[1]	auto[0]	271621	1			T27	47		T28	25		T29	2
bins_for_gpio_bits[3]	auto[1]	auto[1]	5922206	1			T23	17164		T24	1200		T25	572
bins_for_gpio_bits[4]	auto[0]	auto[0]	9101284	1			T23	19212		T24	1152		T25	611
bins_for_gpio_bits[4]	auto[0]	auto[1]	271571	1			T27	51		T28	21		T29	2
bins_for_gpio_bits[4]	auto[1]	auto[0]	271824	1			T27	52		T28	21		T29	2
bins_for_gpio_bits[4]	auto[1]	auto[1]	5928286	1			T23	18970		T24	1170		T25	648
bins_for_gpio_bits[5]	auto[0]	auto[0]	9101683	1			T23	20562		T24	1149		T25	597
bins_for_gpio_bits[5]	auto[0]	auto[1]	271827	1			T27	49		T28	15		T29	2
bins_for_gpio_bits[5]	auto[1]	auto[0]	272053	1			T27	49		T28	15		T29	2
bins_for_gpio_bits[5]	auto[1]	auto[1]	5927402	1			T23	17620		T24	1173		T25	662
bins_for_gpio_bits[6]	auto[0]	auto[0]	9086742	1			T23	19036		T24	1169		T25	687
bins_for_gpio_bits[6]	auto[0]	auto[1]	272127	1			T27	43		T28	24		T29	2
bins_for_gpio_bits[6]	auto[1]	auto[0]	272366	1			T27	44		T28	24		T29	2
bins_for_gpio_bits[6]	auto[1]	auto[1]	5941730	1			T23	19146		T24	1153		T25	572
bins_for_gpio_bits[7]	auto[0]	auto[0]	9093219	1			T23	17827		T24	1157		T25	626
bins_for_gpio_bits[7]	auto[0]	auto[1]	271803	1			T27	43		T28	14		T29	2
bins_for_gpio_bits[7]	auto[1]	auto[0]	272061	1			T27	43		T28	14		T29	2
bins_for_gpio_bits[7]	auto[1]	auto[1]	5935882	1			T23	20355		T24	1165		T25	633
bins_for_gpio_bits[8]	auto[0]	auto[0]	9102170	1			T23	20266		T24	1147		T25	513
bins_for_gpio_bits[8]	auto[0]	auto[1]	272317	1			T27	48		T28	12		T29	2
bins_for_gpio_bits[8]	auto[1]	auto[0]	272543	1			T27	48		T28	12		T29	2
bins_for_gpio_bits[8]	auto[1]	auto[1]	5925935	1			T23	17916		T24	1175		T25	746
bins_for_gpio_bits[9]	auto[0]	auto[0]	9089550	1			T23	19735		T24	1152		T25	669
bins_for_gpio_bits[9]	auto[0]	auto[1]	271536	1			T27	45		T28	19		T29	2
bins_for_gpio_bits[9]	auto[1]	auto[0]	271738	1			T27	45		T28	19		T29	2
bins_for_gpio_bits[9]	auto[1]	auto[1]	5940141	1			T23	18447		T24	1170		T25	590
bins_for_gpio_bits[10]	auto[0]	auto[0]	9094296	1			T23	18358		T24	1149		T25	643
bins_for_gpio_bits[10]	auto[0]	auto[1]	271735	1			T27	44		T28	17		T29	3
bins_for_gpio_bits[10]	auto[1]	auto[0]	272002	1			T27	44		T28	17		T29	3
bins_for_gpio_bits[10]	auto[1]	auto[1]	5934932	1			T23	19824		T24	1173		T25	616
bins_for_gpio_bits[11]	auto[0]	auto[0]	9104104	1			T23	19267		T24	1134		T25	700
bins_for_gpio_bits[11]	auto[0]	auto[1]	271575	1			T27	49		T28	21		T29	1
bins_for_gpio_bits[11]	auto[1]	auto[0]	271828	1			T27	49		T28	21		T29	1
bins_for_gpio_bits[11]	auto[1]	auto[1]	5925458	1			T23	18915		T24	1188		T25	559
bins_for_gpio_bits[12]	auto[0]	auto[0]	9098702	1			T23	18390		T24	1161		T25	700
bins_for_gpio_bits[12]	auto[0]	auto[1]	271410	1			T27	39		T28	15		T29	3
bins_for_gpio_bits[12]	auto[1]	auto[0]	271684	1			T27	40		T28	15		T29	3
bins_for_gpio_bits[12]	auto[1]	auto[1]	5931169	1			T23	19792		T24	1161		T25	559
bins_for_gpio_bits[13]	auto[0]	auto[0]	9096636	1			T23	20221		T24	1151		T25	547
bins_for_gpio_bits[13]	auto[0]	auto[1]	271666	1			T27	49		T28	18		T29	2
bins_for_gpio_bits[13]	auto[1]	auto[0]	271909	1			T27	49		T28	18		T29	2
bins_for_gpio_bits[13]	auto[1]	auto[1]	5932754	1			T23	17961		T24	1171		T25	712
bins_for_gpio_bits[14]	auto[0]	auto[0]	9102081	1			T23	19823		T24	1181		T25	576
bins_for_gpio_bits[14]	auto[0]	auto[1]	272098	1			T27	50		T28	22		T29	4
bins_for_gpio_bits[14]	auto[1]	auto[0]	272357	1			T27	50		T28	22		T29	4
bins_for_gpio_bits[14]	auto[1]	auto[1]	5926429	1			T23	18359		T24	1141		T25	683
bins_for_gpio_bits[15]	auto[0]	auto[0]	9103412	1			T23	19359		T24	1158		T25	615
bins_for_gpio_bits[15]	auto[0]	auto[1]	272027	1			T27	46		T28	19		T29	4
bins_for_gpio_bits[15]	auto[1]	auto[0]	272269	1			T27	46		T28	19		T29	4
bins_for_gpio_bits[15]	auto[1]	auto[1]	5925257	1			T23	18823		T24	1164		T25	644
bins_for_gpio_bits[16]	auto[0]	auto[0]	9099090	1			T23	19477		T24	1199		T25	606
bins_for_gpio_bits[16]	auto[0]	auto[1]	271718	1			T27	52		T28	12		T29	7
bins_for_gpio_bits[16]	auto[1]	auto[0]	271981	1			T27	52		T28	12		T29	7
bins_for_gpio_bits[16]	auto[1]	auto[1]	5930176	1			T23	18705		T24	1123		T25	653
bins_for_gpio_bits[17]	auto[0]	auto[0]	9083636	1			T23	18084		T24	1135		T25	530
bins_for_gpio_bits[17]	auto[0]	auto[1]	272607	1			T27	46		T28	13		T29	5
bins_for_gpio_bits[17]	auto[1]	auto[0]	272834	1			T27	47		T28	13		T29	5
bins_for_gpio_bits[17]	auto[1]	auto[1]	5943888	1			T23	20098		T24	1187		T25	729
bins_for_gpio_bits[18]	auto[0]	auto[0]	9094811	1			T23	19692		T24	1149		T25	614
bins_for_gpio_bits[18]	auto[0]	auto[1]	271747	1			T27	47		T28	18		T29	1
bins_for_gpio_bits[18]	auto[1]	auto[0]	272024	1			T27	47		T28	18		T29	1
bins_for_gpio_bits[18]	auto[1]	auto[1]	5934383	1			T23	18490		T24	1173		T25	645
bins_for_gpio_bits[19]	auto[0]	auto[0]	9092195	1			T23	18926		T24	1153		T25	664
bins_for_gpio_bits[19]	auto[0]	auto[1]	272358	1			T27	45		T28	25		T29	3
bins_for_gpio_bits[19]	auto[1]	auto[0]	272611	1			T27	45		T28	25		T29	3
bins_for_gpio_bits[19]	auto[1]	auto[1]	5935801	1			T23	19256		T24	1169		T25	595
bins_for_gpio_bits[20]	auto[0]	auto[0]	9099910	1			T23	19516		T24	1180		T25	639
bins_for_gpio_bits[20]	auto[0]	auto[1]	272393	1			T27	41		T28	19		T29	1
bins_for_gpio_bits[20]	auto[1]	auto[0]	272632	1			T27	41		T28	19		T29	1
bins_for_gpio_bits[20]	auto[1]	auto[1]	5928030	1			T23	18666		T24	1142		T25	620
bins_for_gpio_bits[21]	auto[0]	auto[0]	9092376	1			T23	18088		T24	1170		T25	654
bins_for_gpio_bits[21]	auto[0]	auto[1]	272827	1			T27	40		T28	22		T29	2
bins_for_gpio_bits[21]	auto[1]	auto[0]	273090	1			T27	40		T28	22		T29	1
bins_for_gpio_bits[21]	auto[1]	auto[1]	5934672	1			T23	20094		T24	1152		T25	605
bins_for_gpio_bits[22]	auto[0]	auto[0]	9095226	1			T23	19324		T24	1166		T25	643
bins_for_gpio_bits[22]	auto[0]	auto[1]	271913	1			T27	46		T28	16		T29	2
bins_for_gpio_bits[22]	auto[1]	auto[0]	272173	1			T27	46		T28	16		T29	2
bins_for_gpio_bits[22]	auto[1]	auto[1]	5933653	1			T23	18858		T24	1156		T25	616
bins_for_gpio_bits[23]	auto[0]	auto[0]	9091597	1			T23	18567		T24	1136		T25	626
bins_for_gpio_bits[23]	auto[0]	auto[1]	271749	1			T27	45		T28	16		T29	2
bins_for_gpio_bits[23]	auto[1]	auto[0]	272021	1			T27	45		T28	16		T29	2
bins_for_gpio_bits[23]	auto[1]	auto[1]	5937598	1			T23	19615		T24	1186		T25	633
bins_for_gpio_bits[24]	auto[0]	auto[0]	9090903	1			T23	20143		T24	1121		T25	622
bins_for_gpio_bits[24]	auto[0]	auto[1]	271898	1			T27	46		T28	16		T29	2
bins_for_gpio_bits[24]	auto[1]	auto[0]	272139	1			T27	46		T28	16		T29	2
bins_for_gpio_bits[24]	auto[1]	auto[1]	5938025	1			T23	18039		T24	1201		T25	637
bins_for_gpio_bits[25]	auto[0]	auto[0]	9104769	1			T23	18653		T24	1154		T25	606
bins_for_gpio_bits[25]	auto[0]	auto[1]	272072	1			T27	46		T28	18		T29	2
bins_for_gpio_bits[25]	auto[1]	auto[0]	272313	1			T27	46		T28	18		T29	2
bins_for_gpio_bits[25]	auto[1]	auto[1]	5923811	1			T23	19529		T24	1168		T25	653
bins_for_gpio_bits[26]	auto[0]	auto[0]	9108919	1			T23	18289		T24	1178		T25	664
bins_for_gpio_bits[26]	auto[0]	auto[1]	271968	1			T27	47		T28	23		T29	2
bins_for_gpio_bits[26]	auto[1]	auto[0]	272241	1			T27	47		T28	23		T29	2
bins_for_gpio_bits[26]	auto[1]	auto[1]	5919837	1			T23	19893		T24	1144		T25	595
bins_for_gpio_bits[27]	auto[0]	auto[0]	9096818	1			T23	17878		T24	1160		T25	548
bins_for_gpio_bits[27]	auto[0]	auto[1]	271955	1			T27	46		T28	22		T31	1
bins_for_gpio_bits[27]	auto[1]	auto[0]	272206	1			T27	46		T28	22		T31	1
bins_for_gpio_bits[27]	auto[1]	auto[1]	5931986	1			T23	20304		T24	1162		T25	711
bins_for_gpio_bits[28]	auto[0]	auto[0]	9099411	1			T23	20180		T24	1165		T25	652
bins_for_gpio_bits[28]	auto[0]	auto[1]	272203	1			T27	49		T28	20		T29	1
bins_for_gpio_bits[28]	auto[1]	auto[0]	272426	1			T27	50		T28	20		T29	1
bins_for_gpio_bits[28]	auto[1]	auto[1]	5928925	1			T23	18002		T24	1157		T25	607
bins_for_gpio_bits[29]	auto[0]	auto[0]	9098656	1			T23	19142		T24	1211		T25	605
bins_for_gpio_bits[29]	auto[0]	auto[1]	271870	1			T27	42		T28	12		T29	2
bins_for_gpio_bits[29]	auto[1]	auto[0]	272108	1			T27	43		T28	12		T29	2
bins_for_gpio_bits[29]	auto[1]	auto[1]	5930331	1			T23	19040		T24	1111		T25	654
bins_for_gpio_bits[30]	auto[0]	auto[0]	9095201	1			T23	18919		T24	1155		T25	641
bins_for_gpio_bits[30]	auto[0]	auto[1]	272070	1			T27	53		T28	16		T29	5
bins_for_gpio_bits[30]	auto[1]	auto[0]	272334	1			T27	53		T28	16		T29	5
bins_for_gpio_bits[30]	auto[1]	auto[1]	5933360	1			T23	19263		T24	1167		T25	618
bins_for_gpio_bits[31]	auto[0]	auto[0]	9098927	1			T23	20119		T24	1100		T25	675
bins_for_gpio_bits[31]	auto[0]	auto[1]	271319	1			T27	46		T28	14		T29	3
bins_for_gpio_bits[31]	auto[1]	auto[0]	271586	1			T27	46		T28	14		T29	3
bins_for_gpio_bits[31]	auto[1]	auto[1]	5931133	1			T23	18063		T24	1222		T25	584