Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
gpio_value	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_pins_data_in	128	0	128	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	11217492	1			T41	379		T42	524		T43	103
bins_for_gpio_bits[1]	11217492	1			T41	379		T42	524		T43	103
bins_for_gpio_bits[2]	11217492	1			T41	379		T42	524		T43	103
bins_for_gpio_bits[3]	11217492	1			T41	379		T42	524		T43	103
bins_for_gpio_bits[4]	11217492	1			T41	379		T42	524		T43	103
bins_for_gpio_bits[5]	11217492	1			T41	379		T42	524		T43	103
bins_for_gpio_bits[6]	11217492	1			T41	379		T42	524		T43	103
bins_for_gpio_bits[7]	11217492	1			T41	379		T42	524		T43	103
bins_for_gpio_bits[8]	11217492	1			T41	379		T42	524		T43	103
bins_for_gpio_bits[9]	11217492	1			T41	379		T42	524		T43	103
bins_for_gpio_bits[10]	11217492	1			T41	379		T42	524		T43	103
bins_for_gpio_bits[11]	11217492	1			T41	379		T42	524		T43	103
bins_for_gpio_bits[12]	11217492	1			T41	379		T42	524		T43	103
bins_for_gpio_bits[13]	11217492	1			T41	379		T42	524		T43	103
bins_for_gpio_bits[14]	11217492	1			T41	379		T42	524		T43	103
bins_for_gpio_bits[15]	11217492	1			T41	379		T42	524		T43	103
bins_for_gpio_bits[16]	11217492	1			T41	379		T42	524		T43	103
bins_for_gpio_bits[17]	11217492	1			T41	379		T42	524		T43	103
bins_for_gpio_bits[18]	11217492	1			T41	379		T42	524		T43	103
bins_for_gpio_bits[19]	11217492	1			T41	379		T42	524		T43	103
bins_for_gpio_bits[20]	11217492	1			T41	379		T42	524		T43	103
bins_for_gpio_bits[21]	11217492	1			T41	379		T42	524		T43	103
bins_for_gpio_bits[22]	11217492	1			T41	379		T42	524		T43	103
bins_for_gpio_bits[23]	11217492	1			T41	379		T42	524		T43	103
bins_for_gpio_bits[24]	11217492	1			T41	379		T42	524		T43	103
bins_for_gpio_bits[25]	11217492	1			T41	379		T42	524		T43	103
bins_for_gpio_bits[26]	11217492	1			T41	379		T42	524		T43	103
bins_for_gpio_bits[27]	11217492	1			T41	379		T42	524		T43	103
bins_for_gpio_bits[28]	11217492	1			T41	379		T42	524		T43	103
bins_for_gpio_bits[29]	11217492	1			T41	379		T42	524		T43	103
bins_for_gpio_bits[30]	11217492	1			T41	379		T42	524		T43	103
bins_for_gpio_bits[31]	11217492	1			T41	379		T42	524		T43	103

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

210860388

1

T41

8156

T42

4738

T43

2666

auto[1]

148099356

1

T41

3972

T42

12030

T43

630

---

Summary for Variable gpio_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for gpio_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

210852421

1

T41

8149

T42

4742

T43

2666

auto[1]

148107323

1

T41

3979

T42

12026

T43

630

---

Summary for Cross cp_cross_pins_data_in

Samples crossed: cp_pin gpio_value data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_cross_pins_data_in

Bins

cp_pin	gpio_value	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	6387949	1			T41	247		T42	132		T43	87
bins_for_gpio_bits[0]	auto[0]	auto[1]	194527	1			T41	16		T42	28		T43	1
bins_for_gpio_bits[0]	auto[1]	auto[0]	194761	1			T41	16		T42	28		T43	1
bins_for_gpio_bits[0]	auto[1]	auto[1]	4440255	1			T41	100		T42	336		T43	14
bins_for_gpio_bits[1]	auto[0]	auto[0]	6387633	1			T41	257		T42	130		T43	77
bins_for_gpio_bits[1]	auto[0]	auto[1]	194788	1			T41	12		T42	28		T43	2
bins_for_gpio_bits[1]	auto[1]	auto[0]	195012	1			T41	12		T42	28		T43	2
bins_for_gpio_bits[1]	auto[1]	auto[1]	4440059	1			T41	98		T42	338		T43	22
bins_for_gpio_bits[2]	auto[0]	auto[0]	6392905	1			T41	274		T42	128		T43	84
bins_for_gpio_bits[2]	auto[0]	auto[1]	194913	1			T41	12		T42	28		T43	3
bins_for_gpio_bits[2]	auto[1]	auto[0]	195143	1			T41	12		T42	27		T43	3
bins_for_gpio_bits[2]	auto[1]	auto[1]	4434531	1			T41	81		T42	341		T43	13
bins_for_gpio_bits[3]	auto[0]	auto[0]	6390069	1			T41	233		T42	109		T43	87
bins_for_gpio_bits[3]	auto[0]	auto[1]	194861	1			T41	17		T42	28		T43	1
bins_for_gpio_bits[3]	auto[1]	auto[0]	195113	1			T41	18		T42	28		T43	1
bins_for_gpio_bits[3]	auto[1]	auto[1]	4437449	1			T41	111		T42	359		T43	14
bins_for_gpio_bits[4]	auto[0]	auto[0]	6398834	1			T41	258		T42	113		T43	79
bins_for_gpio_bits[4]	auto[0]	auto[1]	194384	1			T41	10		T42	27		T43	3
bins_for_gpio_bits[4]	auto[1]	auto[0]	194641	1			T41	10		T42	27		T43	3
bins_for_gpio_bits[4]	auto[1]	auto[1]	4429633	1			T41	101		T42	357		T43	18
bins_for_gpio_bits[5]	auto[0]	auto[0]	6394391	1			T41	265		T42	107		T43	76
bins_for_gpio_bits[5]	auto[0]	auto[1]	194686	1			T41	12		T42	27		T43	3
bins_for_gpio_bits[5]	auto[1]	auto[0]	194973	1			T41	12		T42	27		T43	3
bins_for_gpio_bits[5]	auto[1]	auto[1]	4433442	1			T41	90		T42	363		T43	21
bins_for_gpio_bits[6]	auto[0]	auto[0]	6387689	1			T41	217		T42	146		T43	67
bins_for_gpio_bits[6]	auto[0]	auto[1]	194584	1			T41	18		T42	27		T43	3
bins_for_gpio_bits[6]	auto[1]	auto[0]	194825	1			T41	19		T42	27		T43	3
bins_for_gpio_bits[6]	auto[1]	auto[1]	4440394	1			T41	125		T42	324		T43	30
bins_for_gpio_bits[7]	auto[0]	auto[0]	6391946	1			T41	263		T42	104		T43	83
bins_for_gpio_bits[7]	auto[0]	auto[1]	194722	1			T41	14		T42	25		T43	1
bins_for_gpio_bits[7]	auto[1]	auto[0]	194966	1			T41	14		T42	25		T43	1
bins_for_gpio_bits[7]	auto[1]	auto[1]	4435858	1			T41	88		T42	370		T43	18
bins_for_gpio_bits[8]	auto[0]	auto[0]	6391594	1			T41	226		T42	143		T43	68
bins_for_gpio_bits[8]	auto[0]	auto[1]	193932	1			T41	18		T42	29		T43	3
bins_for_gpio_bits[8]	auto[1]	auto[0]	194157	1			T41	18		T42	29		T43	3
bins_for_gpio_bits[8]	auto[1]	auto[1]	4437809	1			T41	117		T42	323		T43	29
bins_for_gpio_bits[9]	auto[0]	auto[0]	6398674	1			T41	217		T42	94		T43	87
bins_for_gpio_bits[9]	auto[0]	auto[1]	194926	1			T41	17		T42	22		T43	1
bins_for_gpio_bits[9]	auto[1]	auto[0]	195206	1			T41	17		T42	22		T43	1
bins_for_gpio_bits[9]	auto[1]	auto[1]	4428686	1			T41	128		T42	386		T43	14
bins_for_gpio_bits[10]	auto[0]	auto[0]	6397734	1			T41	216		T42	158		T43	70
bins_for_gpio_bits[10]	auto[0]	auto[1]	194453	1			T41	18		T42	31		T43	2
bins_for_gpio_bits[10]	auto[1]	auto[0]	194729	1			T41	18		T42	31		T43	2
bins_for_gpio_bits[10]	auto[1]	auto[1]	4430576	1			T41	127		T42	304		T43	29
bins_for_gpio_bits[11]	auto[0]	auto[0]	6388790	1			T41	236		T42	119		T43	97
bins_for_gpio_bits[11]	auto[0]	auto[1]	195173	1			T41	11		T42	28		T44	2
bins_for_gpio_bits[11]	auto[1]	auto[0]	195448	1			T41	12		T42	28		T44	2
bins_for_gpio_bits[11]	auto[1]	auto[1]	4438081	1			T41	120		T42	349		T43	6
bins_for_gpio_bits[12]	auto[0]	auto[0]	6396060	1			T41	232		T42	125		T43	80
bins_for_gpio_bits[12]	auto[0]	auto[1]	194160	1			T41	16		T42	27		T43	2
bins_for_gpio_bits[12]	auto[1]	auto[0]	194427	1			T41	17		T42	27		T43	2
bins_for_gpio_bits[12]	auto[1]	auto[1]	4432845	1			T41	114		T42	345		T43	19
bins_for_gpio_bits[13]	auto[0]	auto[0]	6397479	1			T41	237		T42	121		T43	76
bins_for_gpio_bits[13]	auto[0]	auto[1]	194253	1			T41	14		T42	23		T43	4
bins_for_gpio_bits[13]	auto[1]	auto[0]	194485	1			T41	14		T42	23		T43	4
bins_for_gpio_bits[13]	auto[1]	auto[1]	4431275	1			T41	114		T42	357		T43	19
bins_for_gpio_bits[14]	auto[0]	auto[0]	6385985	1			T41	265		T42	121		T43	96
bins_for_gpio_bits[14]	auto[0]	auto[1]	194886	1			T41	11		T42	26		T44	4
bins_for_gpio_bits[14]	auto[1]	auto[0]	195129	1			T41	11		T42	26		T44	4
bins_for_gpio_bits[14]	auto[1]	auto[1]	4441492	1			T41	92		T42	351		T43	7
bins_for_gpio_bits[15]	auto[0]	auto[0]	6381275	1			T41	254		T42	115		T43	74
bins_for_gpio_bits[15]	auto[0]	auto[1]	194428	1			T41	12		T42	30		T43	2
bins_for_gpio_bits[15]	auto[1]	auto[0]	194659	1			T41	12		T42	30		T43	2
bins_for_gpio_bits[15]	auto[1]	auto[1]	4447130	1			T41	101		T42	349		T43	25
bins_for_gpio_bits[16]	auto[0]	auto[0]	6403061	1			T41	226		T42	89		T43	90
bins_for_gpio_bits[16]	auto[0]	auto[1]	194399	1			T41	21		T42	22		T43	1
bins_for_gpio_bits[16]	auto[1]	auto[0]	194666	1			T41	21		T42	22		T43	1
bins_for_gpio_bits[16]	auto[1]	auto[1]	4425366	1			T41	111		T42	391		T43	11
bins_for_gpio_bits[17]	auto[0]	auto[0]	6390979	1			T41	210		T42	104		T43	90
bins_for_gpio_bits[17]	auto[0]	auto[1]	194339	1			T41	19		T42	27		T44	3
bins_for_gpio_bits[17]	auto[1]	auto[0]	194596	1			T41	19		T42	27		T44	3
bins_for_gpio_bits[17]	auto[1]	auto[1]	4437578	1			T41	131		T42	366		T43	13
bins_for_gpio_bits[18]	auto[0]	auto[0]	6407692	1			T41	252		T42	95		T43	82
bins_for_gpio_bits[18]	auto[0]	auto[1]	194686	1			T41	14		T42	24		T43	2
bins_for_gpio_bits[18]	auto[1]	auto[0]	194957	1			T41	14		T42	24		T43	2
bins_for_gpio_bits[18]	auto[1]	auto[1]	4420157	1			T41	99		T42	381		T43	17
bins_for_gpio_bits[19]	auto[0]	auto[0]	6401923	1			T41	242		T42	103		T43	58
bins_for_gpio_bits[19]	auto[0]	auto[1]	194547	1			T41	15		T42	28		T43	4
bins_for_gpio_bits[19]	auto[1]	auto[0]	194776	1			T41	15		T42	27		T43	4
bins_for_gpio_bits[19]	auto[1]	auto[1]	4426246	1			T41	107		T42	366		T43	37
bins_for_gpio_bits[20]	auto[0]	auto[0]	6410559	1			T41	242		T42	123		T43	84
bins_for_gpio_bits[20]	auto[0]	auto[1]	193900	1			T41	15		T42	30		T43	1
bins_for_gpio_bits[20]	auto[1]	auto[0]	194153	1			T41	15		T42	30		T43	1
bins_for_gpio_bits[20]	auto[1]	auto[1]	4418880	1			T41	107		T42	341		T43	17
bins_for_gpio_bits[21]	auto[0]	auto[0]	6386221	1			T41	263		T42	132		T43	93
bins_for_gpio_bits[21]	auto[0]	auto[1]	194737	1			T41	8		T42	27		T44	3
bins_for_gpio_bits[21]	auto[1]	auto[0]	195007	1			T41	9		T42	27		T44	3
bins_for_gpio_bits[21]	auto[1]	auto[1]	4441527	1			T41	99		T42	338		T43	10
bins_for_gpio_bits[22]	auto[0]	auto[0]	6395629	1			T41	237		T42	146		T43	77
bins_for_gpio_bits[22]	auto[0]	auto[1]	194729	1			T41	17		T42	28		T43	2
bins_for_gpio_bits[22]	auto[1]	auto[0]	194956	1			T41	17		T42	27		T43	2
bins_for_gpio_bits[22]	auto[1]	auto[1]	4432178	1			T41	108		T42	323		T43	22
bins_for_gpio_bits[23]	auto[0]	auto[0]	6392208	1			T41	227		T42	147		T43	85
bins_for_gpio_bits[23]	auto[0]	auto[1]	194814	1			T41	16		T42	28		T43	1
bins_for_gpio_bits[23]	auto[1]	auto[0]	195024	1			T41	17		T42	28		T43	1
bins_for_gpio_bits[23]	auto[1]	auto[1]	4435446	1			T41	119		T42	321		T43	16
bins_for_gpio_bits[24]	auto[0]	auto[0]	6394307	1			T41	219		T42	106		T43	84
bins_for_gpio_bits[24]	auto[0]	auto[1]	194271	1			T41	16		T42	26		T43	2
bins_for_gpio_bits[24]	auto[1]	auto[0]	194500	1			T41	17		T42	26		T43	2
bins_for_gpio_bits[24]	auto[1]	auto[1]	4434414	1			T41	127		T42	366		T43	15
bins_for_gpio_bits[25]	auto[0]	auto[0]	6401382	1			T41	242		T42	112		T43	78
bins_for_gpio_bits[25]	auto[0]	auto[1]	193929	1			T41	16		T42	24		T43	1
bins_for_gpio_bits[25]	auto[1]	auto[0]	194144	1			T41	16		T42	24		T43	1
bins_for_gpio_bits[25]	auto[1]	auto[1]	4428037	1			T41	105		T42	364		T43	23
bins_for_gpio_bits[26]	auto[0]	auto[0]	6394091	1			T41	222		T42	144		T43	88
bins_for_gpio_bits[26]	auto[0]	auto[1]	195055	1			T41	16		T42	29		T44	2
bins_for_gpio_bits[26]	auto[1]	auto[0]	195300	1			T41	16		T42	28		T44	2
bins_for_gpio_bits[26]	auto[1]	auto[1]	4433046	1			T41	125		T42	323		T43	15
bins_for_gpio_bits[27]	auto[0]	auto[0]	6394263	1			T41	264		T42	120		T43	75
bins_for_gpio_bits[27]	auto[0]	auto[1]	194679	1			T41	11		T42	29		T43	3
bins_for_gpio_bits[27]	auto[1]	auto[0]	194927	1			T41	11		T42	29		T43	3
bins_for_gpio_bits[27]	auto[1]	auto[1]	4433623	1			T41	93		T42	346		T43	22
bins_for_gpio_bits[28]	auto[0]	auto[0]	6391376	1			T41	253		T42	101		T43	86
bins_for_gpio_bits[28]	auto[0]	auto[1]	194591	1			T41	16		T42	29		T43	2
bins_for_gpio_bits[28]	auto[1]	auto[0]	194851	1			T41	16		T42	29		T43	2
bins_for_gpio_bits[28]	auto[1]	auto[1]	4436674	1			T41	94		T42	365		T43	13
bins_for_gpio_bits[29]	auto[0]	auto[0]	6401486	1			T41	218		T42	128		T43	85
bins_for_gpio_bits[29]	auto[0]	auto[1]	194791	1			T41	16		T42	28		T43	1
bins_for_gpio_bits[29]	auto[1]	auto[0]	195045	1			T41	16		T42	28		T43	1
bins_for_gpio_bits[29]	auto[1]	auto[1]	4426170	1			T41	129		T42	340		T43	16
bins_for_gpio_bits[30]	auto[0]	auto[0]	6397837	1			T41	241		T42	107		T43	82
bins_for_gpio_bits[30]	auto[0]	auto[1]	194326	1			T41	15		T42	27		T43	2
bins_for_gpio_bits[30]	auto[1]	auto[0]	194583	1			T41	15		T42	27		T43	2
bins_for_gpio_bits[30]	auto[1]	auto[1]	4430746	1			T41	108		T42	363		T43	17
bins_for_gpio_bits[31]	auto[0]	auto[0]	6394893	1			T41	215		T42	150		T43	86
bins_for_gpio_bits[31]	auto[0]	auto[1]	194038	1			T41	20		T42	30		T43	2
bins_for_gpio_bits[31]	auto[1]	auto[0]	194315	1			T41	20		T42	30		T43	2
bins_for_gpio_bits[31]	auto[1]	auto[1]	4434246	1			T41	124		T42	314		T43	13