Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/gpio-sim-vcs/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
gpio_value	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_pins_data_in	128	0	128	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	6723450	1			T25	44		T26	201		T27	345
bins_for_gpio_bits[1]	6723450	1			T25	44		T26	201		T27	345
bins_for_gpio_bits[2]	6723450	1			T25	44		T26	201		T27	345
bins_for_gpio_bits[3]	6723450	1			T25	44		T26	201		T27	345
bins_for_gpio_bits[4]	6723450	1			T25	44		T26	201		T27	345
bins_for_gpio_bits[5]	6723450	1			T25	44		T26	201		T27	345
bins_for_gpio_bits[6]	6723450	1			T25	44		T26	201		T27	345
bins_for_gpio_bits[7]	6723450	1			T25	44		T26	201		T27	345
bins_for_gpio_bits[8]	6723450	1			T25	44		T26	201		T27	345
bins_for_gpio_bits[9]	6723450	1			T25	44		T26	201		T27	345
bins_for_gpio_bits[10]	6723450	1			T25	44		T26	201		T27	345
bins_for_gpio_bits[11]	6723450	1			T25	44		T26	201		T27	345
bins_for_gpio_bits[12]	6723450	1			T25	44		T26	201		T27	345
bins_for_gpio_bits[13]	6723450	1			T25	44		T26	201		T27	345
bins_for_gpio_bits[14]	6723450	1			T25	44		T26	201		T27	345
bins_for_gpio_bits[15]	6723450	1			T25	44		T26	201		T27	345
bins_for_gpio_bits[16]	6723450	1			T25	44		T26	201		T27	345
bins_for_gpio_bits[17]	6723450	1			T25	44		T26	201		T27	345
bins_for_gpio_bits[18]	6723450	1			T25	44		T26	201		T27	345
bins_for_gpio_bits[19]	6723450	1			T25	44		T26	201		T27	345
bins_for_gpio_bits[20]	6723450	1			T25	44		T26	201		T27	345
bins_for_gpio_bits[21]	6723450	1			T25	44		T26	201		T27	345
bins_for_gpio_bits[22]	6723450	1			T25	44		T26	201		T27	345
bins_for_gpio_bits[23]	6723450	1			T25	44		T26	201		T27	345
bins_for_gpio_bits[24]	6723450	1			T25	44		T26	201		T27	345
bins_for_gpio_bits[25]	6723450	1			T25	44		T26	201		T27	345
bins_for_gpio_bits[26]	6723450	1			T25	44		T26	201		T27	345
bins_for_gpio_bits[27]	6723450	1			T25	44		T26	201		T27	345
bins_for_gpio_bits[28]	6723450	1			T25	44		T26	201		T27	345
bins_for_gpio_bits[29]	6723450	1			T25	44		T26	201		T27	345
bins_for_gpio_bits[30]	6723450	1			T25	44		T26	201		T27	345
bins_for_gpio_bits[31]	6723450	1			T25	44		T26	201		T27	345

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

111516648

1

T25

247

T26

5191

T27

6942

auto[1]

103633752

1

T25

1161

T26

1241

T27

4098

---

Summary for Variable gpio_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for gpio_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

111509978

1

T25

247

T26

5180

T27

6933

auto[1]

103640422

1

T25

1161

T26

1252

T27

4107

---

Summary for Cross cp_cross_pins_data_in

Samples crossed: cp_pin gpio_value data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_cross_pins_data_in

Bins

cp_pin	gpio_value	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	3377426	1			T25	3		T26	163		T27	221
bins_for_gpio_bits[0]	auto[0]	auto[1]	103349	1			T25	2		T26	4		T27	12
bins_for_gpio_bits[0]	auto[1]	auto[0]	103567	1			T25	2		T26	4		T27	12
bins_for_gpio_bits[0]	auto[1]	auto[1]	3139108	1			T25	37		T26	30		T27	100
bins_for_gpio_bits[1]	auto[0]	auto[0]	3375637	1			T25	10		T26	171		T27	205
bins_for_gpio_bits[1]	auto[0]	auto[1]	103450	1			T25	2		T26	4		T27	10
bins_for_gpio_bits[1]	auto[1]	auto[0]	103673	1			T25	2		T26	4		T27	10
bins_for_gpio_bits[1]	auto[1]	auto[1]	3140690	1			T25	30		T26	22		T27	120
bins_for_gpio_bits[2]	auto[0]	auto[0]	3381275	1			T25	2		T26	143		T27	194
bins_for_gpio_bits[2]	auto[0]	auto[1]	103778	1			T26	6		T27	10		T29	11
bins_for_gpio_bits[2]	auto[1]	auto[0]	104006	1			T26	7		T27	11		T29	11
bins_for_gpio_bits[2]	auto[1]	auto[1]	3134391	1			T25	42		T26	45		T27	130
bins_for_gpio_bits[3]	auto[0]	auto[0]	3386727	1			T25	4		T26	154		T27	199
bins_for_gpio_bits[3]	auto[0]	auto[1]	103706	1			T25	1		T26	6		T27	14
bins_for_gpio_bits[3]	auto[1]	auto[0]	103878	1			T25	1		T26	7		T27	14
bins_for_gpio_bits[3]	auto[1]	auto[1]	3129139	1			T25	38		T26	34		T27	118
bins_for_gpio_bits[4]	auto[0]	auto[0]	3380634	1			T25	10		T26	158		T27	222
bins_for_gpio_bits[4]	auto[0]	auto[1]	103304	1			T25	1		T26	4		T27	12
bins_for_gpio_bits[4]	auto[1]	auto[0]	103506	1			T25	1		T26	5		T27	13
bins_for_gpio_bits[4]	auto[1]	auto[1]	3136006	1			T25	32		T26	34		T27	98
bins_for_gpio_bits[5]	auto[0]	auto[0]	3375014	1			T25	3		T26	159		T27	204
bins_for_gpio_bits[5]	auto[0]	auto[1]	103828	1			T26	3		T27	8		T29	15
bins_for_gpio_bits[5]	auto[1]	auto[0]	104025	1			T26	4		T27	9		T29	15
bins_for_gpio_bits[5]	auto[1]	auto[1]	3140583	1			T25	41		T26	35		T27	124
bins_for_gpio_bits[6]	auto[0]	auto[0]	3378817	1			T25	5		T26	182		T27	208
bins_for_gpio_bits[6]	auto[0]	auto[1]	102976	1			T26	1		T27	11		T29	21
bins_for_gpio_bits[6]	auto[1]	auto[0]	103198	1			T26	1		T27	12		T29	21
bins_for_gpio_bits[6]	auto[1]	auto[1]	3138459	1			T25	39		T26	17		T27	114
bins_for_gpio_bits[7]	auto[0]	auto[0]	3378023	1			T25	5		T26	152		T27	189
bins_for_gpio_bits[7]	auto[0]	auto[1]	103441	1			T26	5		T27	10		T29	17
bins_for_gpio_bits[7]	auto[1]	auto[0]	103659	1			T26	5		T27	11		T29	16
bins_for_gpio_bits[7]	auto[1]	auto[1]	3138327	1			T25	39		T26	39		T27	135
bins_for_gpio_bits[8]	auto[0]	auto[0]	3384178	1			T25	5		T26	181		T27	189
bins_for_gpio_bits[8]	auto[0]	auto[1]	103681	1			T26	2		T27	13		T29	19
bins_for_gpio_bits[8]	auto[1]	auto[0]	103897	1			T26	2		T27	13		T29	19
bins_for_gpio_bits[8]	auto[1]	auto[1]	3131694	1			T25	39		T26	16		T27	130
bins_for_gpio_bits[9]	auto[0]	auto[0]	3375825	1			T25	2		T26	129		T27	210
bins_for_gpio_bits[9]	auto[0]	auto[1]	103464	1			T26	8		T27	9		T29	16
bins_for_gpio_bits[9]	auto[1]	auto[0]	103651	1			T26	8		T27	9		T29	15
bins_for_gpio_bits[9]	auto[1]	auto[1]	3140510	1			T25	42		T26	56		T27	117
bins_for_gpio_bits[10]	auto[0]	auto[0]	3398099	1			T25	10		T26	162		T27	201
bins_for_gpio_bits[10]	auto[0]	auto[1]	103683	1			T25	1		T26	4		T27	11
bins_for_gpio_bits[10]	auto[1]	auto[0]	103892	1			T25	1		T26	4		T27	11
bins_for_gpio_bits[10]	auto[1]	auto[1]	3117776	1			T25	32		T26	31		T27	122
bins_for_gpio_bits[11]	auto[0]	auto[0]	3382386	1			T25	13		T26	170		T27	200
bins_for_gpio_bits[11]	auto[0]	auto[1]	103259	1			T25	2		T26	5		T27	11
bins_for_gpio_bits[11]	auto[1]	auto[0]	103489	1			T25	2		T26	5		T27	11
bins_for_gpio_bits[11]	auto[1]	auto[1]	3134316	1			T25	27		T26	21		T27	123
bins_for_gpio_bits[12]	auto[0]	auto[0]	3377783	1			T25	15		T26	146		T27	205
bins_for_gpio_bits[12]	auto[0]	auto[1]	103029	1			T25	3		T26	7		T27	7
bins_for_gpio_bits[12]	auto[1]	auto[0]	103189	1			T25	3		T26	8		T27	7
bins_for_gpio_bits[12]	auto[1]	auto[1]	3139449	1			T25	23		T26	40		T27	126
bins_for_gpio_bits[13]	auto[0]	auto[0]	3383031	1			T25	12		T26	177		T27	184
bins_for_gpio_bits[13]	auto[0]	auto[1]	102979	1			T25	1		T26	3		T27	10
bins_for_gpio_bits[13]	auto[1]	auto[0]	103207	1			T25	1		T26	3		T27	10
bins_for_gpio_bits[13]	auto[1]	auto[1]	3134233	1			T25	30		T26	18		T27	141
bins_for_gpio_bits[14]	auto[0]	auto[0]	3379454	1			T25	8		T26	170		T27	219
bins_for_gpio_bits[14]	auto[0]	auto[1]	103418	1			T25	1		T26	4		T27	8
bins_for_gpio_bits[14]	auto[1]	auto[0]	103590	1			T25	1		T26	4		T27	8
bins_for_gpio_bits[14]	auto[1]	auto[1]	3136988	1			T25	34		T26	23		T27	110
bins_for_gpio_bits[15]	auto[0]	auto[0]	3376769	1			T25	9		T26	175		T27	209
bins_for_gpio_bits[15]	auto[0]	auto[1]	103525	1			T25	2		T26	4		T27	10
bins_for_gpio_bits[15]	auto[1]	auto[0]	103739	1			T25	2		T26	4		T27	11
bins_for_gpio_bits[15]	auto[1]	auto[1]	3139417	1			T25	31		T26	18		T27	115
bins_for_gpio_bits[16]	auto[0]	auto[0]	3376698	1			T25	5		T26	162		T27	202
bins_for_gpio_bits[16]	auto[0]	auto[1]	103211	1			T25	1		T26	5		T27	13
bins_for_gpio_bits[16]	auto[1]	auto[0]	103448	1			T25	1		T26	5		T27	13
bins_for_gpio_bits[16]	auto[1]	auto[1]	3140093	1			T25	37		T26	29		T27	117
bins_for_gpio_bits[17]	auto[0]	auto[0]	3392111	1			T25	3		T26	166		T27	213
bins_for_gpio_bits[17]	auto[0]	auto[1]	103435	1			T25	1		T26	5		T27	9
bins_for_gpio_bits[17]	auto[1]	auto[0]	103641	1			T25	1		T26	6		T27	9
bins_for_gpio_bits[17]	auto[1]	auto[1]	3124263	1			T25	39		T26	24		T27	114
bins_for_gpio_bits[18]	auto[0]	auto[0]	3372847	1			T25	10		T26	172		T27	224
bins_for_gpio_bits[18]	auto[0]	auto[1]	103645	1			T25	2		T26	3		T27	11
bins_for_gpio_bits[18]	auto[1]	auto[0]	103853	1			T25	2		T26	4		T27	11
bins_for_gpio_bits[18]	auto[1]	auto[1]	3143105	1			T25	30		T26	22		T27	99
bins_for_gpio_bits[19]	auto[0]	auto[0]	3388608	1			T25	3		T26	155		T27	198
bins_for_gpio_bits[19]	auto[0]	auto[1]	103646	1			T26	4		T27	12		T29	23
bins_for_gpio_bits[19]	auto[1]	auto[0]	103869	1			T26	4		T27	12		T29	22
bins_for_gpio_bits[19]	auto[1]	auto[1]	3127327	1			T25	41		T26	38		T27	123
bins_for_gpio_bits[20]	auto[0]	auto[0]	3371021	1			T25	5		T26	151		T27	211
bins_for_gpio_bits[20]	auto[0]	auto[1]	103353	1			T26	4		T27	12		T29	18
bins_for_gpio_bits[20]	auto[1]	auto[0]	103580	1			T26	4		T27	12		T29	18
bins_for_gpio_bits[20]	auto[1]	auto[1]	3145496	1			T25	39		T26	42		T27	110
bins_for_gpio_bits[21]	auto[0]	auto[0]	3386155	1			T25	6		T26	120		T27	206
bins_for_gpio_bits[21]	auto[0]	auto[1]	103626	1			T25	2		T26	8		T27	13
bins_for_gpio_bits[21]	auto[1]	auto[0]	103809	1			T25	2		T26	9		T27	14
bins_for_gpio_bits[21]	auto[1]	auto[1]	3129860	1			T25	34		T26	64		T27	112
bins_for_gpio_bits[22]	auto[0]	auto[0]	3376120	1			T25	7		T26	135		T27	222
bins_for_gpio_bits[22]	auto[0]	auto[1]	103596	1			T25	1		T26	8		T27	9
bins_for_gpio_bits[22]	auto[1]	auto[0]	103776	1			T25	1		T26	8		T27	9
bins_for_gpio_bits[22]	auto[1]	auto[1]	3139958	1			T25	35		T26	50		T27	105
bins_for_gpio_bits[23]	auto[0]	auto[0]	3389466	1			T25	7		T26	165		T27	215
bins_for_gpio_bits[23]	auto[0]	auto[1]	103449	1			T25	1		T26	4		T27	11
bins_for_gpio_bits[23]	auto[1]	auto[0]	103664	1			T25	1		T26	4		T27	11
bins_for_gpio_bits[23]	auto[1]	auto[1]	3126871	1			T25	35		T26	28		T27	108
bins_for_gpio_bits[24]	auto[0]	auto[0]	3389419	1			T25	15		T26	151		T27	218
bins_for_gpio_bits[24]	auto[0]	auto[1]	103370	1			T25	1		T26	5		T27	10
bins_for_gpio_bits[24]	auto[1]	auto[0]	103572	1			T25	1		T26	5		T27	10
bins_for_gpio_bits[24]	auto[1]	auto[1]	3127089	1			T25	27		T26	40		T27	107
bins_for_gpio_bits[25]	auto[0]	auto[0]	3387231	1			T25	9		T26	144		T27	200
bins_for_gpio_bits[25]	auto[0]	auto[1]	103371	1			T25	1		T26	5		T27	12
bins_for_gpio_bits[25]	auto[1]	auto[0]	103585	1			T25	1		T26	5		T27	12
bins_for_gpio_bits[25]	auto[1]	auto[1]	3129263	1			T25	33		T26	47		T27	121
bins_for_gpio_bits[26]	auto[0]	auto[0]	3378868	1			T25	2		T26	134		T27	210
bins_for_gpio_bits[26]	auto[0]	auto[1]	103423	1			T26	7		T27	11		T29	14
bins_for_gpio_bits[26]	auto[1]	auto[0]	103662	1			T26	8		T27	11		T29	14
bins_for_gpio_bits[26]	auto[1]	auto[1]	3137497	1			T25	42		T26	52		T27	113
bins_for_gpio_bits[27]	auto[0]	auto[0]	3372010	1			T25	4		T26	165		T27	175
bins_for_gpio_bits[27]	auto[0]	auto[1]	103676	1			T26	3		T27	12		T29	17
bins_for_gpio_bits[27]	auto[1]	auto[0]	103878	1			T26	3		T27	13		T29	16
bins_for_gpio_bits[27]	auto[1]	auto[1]	3143886	1			T25	40		T26	30		T27	145
bins_for_gpio_bits[28]	auto[0]	auto[0]	3385481	1			T25	4		T26	147		T27	180
bins_for_gpio_bits[28]	auto[0]	auto[1]	103517	1			T26	2		T27	11		T29	15
bins_for_gpio_bits[28]	auto[1]	auto[0]	103711	1			T26	3		T27	12		T29	15
bins_for_gpio_bits[28]	auto[1]	auto[1]	3130741	1			T25	40		T26	49		T27	142
bins_for_gpio_bits[29]	auto[0]	auto[0]	3377907	1			T25	4		T26	141		T27	240
bins_for_gpio_bits[29]	auto[0]	auto[1]	103367	1			T26	8		T27	7		T29	18
bins_for_gpio_bits[29]	auto[1]	auto[0]	103589	1			T26	8		T27	7		T29	18
bins_for_gpio_bits[29]	auto[1]	auto[1]	3138587	1			T25	40		T26	44		T27	91
bins_for_gpio_bits[30]	auto[0]	auto[0]	3377555	1			T25	8		T26	172		T27	192
bins_for_gpio_bits[30]	auto[0]	auto[1]	103654	1			T25	1		T26	4		T27	14
bins_for_gpio_bits[30]	auto[1]	auto[0]	103871	1			T25	1		T26	4		T27	14
bins_for_gpio_bits[30]	auto[1]	auto[1]	3138370	1			T25	34		T26	21		T27	125
bins_for_gpio_bits[31]	auto[0]	auto[0]	3387035	1			T25	11		T26	159		T27	226
bins_for_gpio_bits[31]	auto[0]	auto[1]	103159	1			T25	1		T26	4		T27	9
bins_for_gpio_bits[31]	auto[1]	auto[0]	103364	1			T25	1		T26	5		T27	9
bins_for_gpio_bits[31]	auto[1]	auto[1]	3129892	1			T25	31		T26	33		T27	101