Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4464086 |
1 |
|
|
T25 |
20 |
|
T26 |
103 |
|
T27 |
259 |
| auto[1] |
2315471 |
1 |
|
|
T28 |
41 |
|
T30 |
8 |
|
T33 |
369 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6487975 |
1 |
|
|
T25 |
20 |
|
T26 |
103 |
|
T27 |
259 |
| auto[1] |
291582 |
1 |
|
|
T28 |
8 |
|
T33 |
148 |
|
T1 |
8 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4479597 |
1 |
|
|
T25 |
20 |
|
T26 |
103 |
|
T27 |
259 |
| auto[1] |
2299960 |
1 |
|
|
T28 |
121 |
|
T30 |
33 |
|
T33 |
707 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1000450 |
1 |
|
|
T28 |
86 |
|
T30 |
28 |
|
T33 |
393 |
| auto[1] |
auto[0] |
auto[1] |
145321 |
1 |
|
|
T28 |
7 |
|
T33 |
109 |
|
T1 |
3 |
| auto[1] |
auto[1] |
auto[0] |
1007928 |
1 |
|
|
T28 |
27 |
|
T30 |
5 |
|
T33 |
166 |
| auto[1] |
auto[1] |
auto[1] |
146261 |
1 |
|
|
T28 |
1 |
|
T33 |
39 |
|
T1 |
5 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |