Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6760369 |
1 |
|
|
T41 |
259 |
|
T42 |
306 |
|
T43 |
55 |
| auto[1] |
4647528 |
1 |
|
|
T46 |
49 |
|
T47 |
98 |
|
T51 |
1183 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9453521 |
1 |
|
|
T41 |
259 |
|
T42 |
306 |
|
T43 |
55 |
| auto[1] |
1954376 |
1 |
|
|
T46 |
4 |
|
T47 |
36 |
|
T51 |
692 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6738260 |
1 |
|
|
T41 |
259 |
|
T42 |
306 |
|
T43 |
55 |
| auto[1] |
4669637 |
1 |
|
|
T46 |
16 |
|
T47 |
71 |
|
T51 |
1353 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1370104 |
1 |
|
|
T46 |
7 |
|
T47 |
6 |
|
T51 |
399 |
| auto[1] |
auto[0] |
auto[1] |
988034 |
1 |
|
|
T46 |
4 |
|
T47 |
22 |
|
T51 |
388 |
| auto[1] |
auto[1] |
auto[0] |
1345157 |
1 |
|
|
T46 |
5 |
|
T47 |
29 |
|
T51 |
262 |
| auto[1] |
auto[1] |
auto[1] |
966342 |
1 |
|
|
T47 |
14 |
|
T51 |
304 |
|
T64 |
9 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |