Summary for Variable type_ctrl_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for type_ctrl_en

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 6727642 1 T41 259 T42 306 T43 55
auto[1] 4680255 1 T46 26 T47 38 T51 1493


Summary for Cross cp_cross_type_en_state

Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY   EXPECTED   UNCOVERED   COVERED   PERCENT   MISSING   
TOTAL 4 0 4 100.00
Automatically Generated Cross Bins 4 0 4 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cp_cross_type_en_state

Bins
type_ctrl_en   intr_en   intr_state   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[1] auto[0] auto[0] 2041629 1 T46 17 T47 16 T51 390
auto[1] auto[0] auto[1] 297870 1 T46 1 T51 97 T64 2
auto[1] auto[1] auto[0] 2042369 1 T46 8 T47 21 T51 801
auto[1] auto[1] auto[1] 298387 1 T47 1 T51 205 T79 3


User Defined Cross Bins for cp_cross_type_en_state

Excluded/Illegal bins
NAMECOUNTSTATUS
intr_type_disabled 0 Excluded