Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6728993 |
1 |
|
|
T41 |
259 |
|
T42 |
306 |
|
T43 |
55 |
| auto[1] |
4678904 |
1 |
|
|
T46 |
29 |
|
T47 |
49 |
|
T51 |
1618 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9451804 |
1 |
|
|
T41 |
259 |
|
T42 |
306 |
|
T43 |
55 |
| auto[1] |
1956093 |
1 |
|
|
T46 |
9 |
|
T47 |
28 |
|
T51 |
387 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6741078 |
1 |
|
|
T41 |
259 |
|
T42 |
306 |
|
T43 |
55 |
| auto[1] |
4666819 |
1 |
|
|
T46 |
31 |
|
T47 |
50 |
|
T51 |
805 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1355731 |
1 |
|
|
T46 |
12 |
|
T47 |
17 |
|
T51 |
128 |
| auto[1] |
auto[0] |
auto[1] |
981994 |
1 |
|
|
T46 |
7 |
|
T47 |
19 |
|
T51 |
111 |
| auto[1] |
auto[1] |
auto[0] |
1354995 |
1 |
|
|
T46 |
10 |
|
T47 |
5 |
|
T51 |
290 |
| auto[1] |
auto[1] |
auto[1] |
974099 |
1 |
|
|
T46 |
2 |
|
T47 |
9 |
|
T51 |
276 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |