Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4477506 |
1 |
|
|
T25 |
20 |
|
T26 |
103 |
|
T27 |
259 |
| auto[1] |
2302051 |
1 |
|
|
T28 |
51 |
|
T30 |
27 |
|
T33 |
723 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
5674904 |
1 |
|
|
T25 |
20 |
|
T26 |
103 |
|
T27 |
259 |
| auto[1] |
1104653 |
1 |
|
|
T28 |
73 |
|
T30 |
16 |
|
T33 |
341 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4488918 |
1 |
|
|
T25 |
20 |
|
T26 |
103 |
|
T27 |
259 |
| auto[1] |
2290639 |
1 |
|
|
T28 |
111 |
|
T30 |
21 |
|
T33 |
713 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
592305 |
1 |
|
|
T28 |
31 |
|
T30 |
5 |
|
T33 |
179 |
| auto[1] |
auto[0] |
auto[1] |
550865 |
1 |
|
|
T28 |
41 |
|
T30 |
7 |
|
T33 |
149 |
| auto[1] |
auto[1] |
auto[0] |
593681 |
1 |
|
|
T28 |
7 |
|
T33 |
193 |
|
T1 |
24 |
| auto[1] |
auto[1] |
auto[1] |
553788 |
1 |
|
|
T28 |
32 |
|
T30 |
9 |
|
T33 |
192 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |