Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6756923 |
1 |
|
|
T41 |
259 |
|
T42 |
306 |
|
T43 |
55 |
| auto[1] |
4650974 |
1 |
|
|
T46 |
21 |
|
T47 |
60 |
|
T51 |
1161 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9444339 |
1 |
|
|
T41 |
259 |
|
T42 |
306 |
|
T43 |
55 |
| auto[1] |
1963558 |
1 |
|
|
T46 |
26 |
|
T47 |
27 |
|
T51 |
726 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6720983 |
1 |
|
|
T41 |
259 |
|
T42 |
306 |
|
T43 |
55 |
| auto[1] |
4686914 |
1 |
|
|
T46 |
44 |
|
T47 |
70 |
|
T51 |
1529 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1372626 |
1 |
|
|
T46 |
12 |
|
T47 |
33 |
|
T51 |
460 |
| auto[1] |
auto[0] |
auto[1] |
986998 |
1 |
|
|
T46 |
19 |
|
T47 |
11 |
|
T51 |
412 |
| auto[1] |
auto[1] |
auto[0] |
1350730 |
1 |
|
|
T46 |
6 |
|
T47 |
10 |
|
T51 |
343 |
| auto[1] |
auto[1] |
auto[1] |
976560 |
1 |
|
|
T46 |
7 |
|
T47 |
16 |
|
T51 |
314 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |