Summary for Variable intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for intr_en

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 6739123 1 T41 259 T42 306 T43 55
auto[1] 4668774 1 T46 19 T47 98 T51 1150


Summary for Variable intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for intr_state

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 9457799 1 T41 259 T42 306 T43 55
auto[1] 1950098 1 T46 8 T47 39 T51 668


Summary for Variable type_ctrl_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for type_ctrl_en

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 6752232 1 T41 259 T42 306 T43 55
auto[1] 4655665 1 T46 25 T47 97 T51 1221


Summary for Cross cp_cross_type_en_state

Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY   EXPECTED   UNCOVERED   COVERED   PERCENT   MISSING   
TOTAL 4 0 4 100.00
Automatically Generated Cross Bins 4 0 4 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cp_cross_type_en_state

Bins
type_ctrl_en   intr_en   intr_state   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[1] auto[0] auto[0] 1352792 1 T46 14 T47 28 T51 324
auto[1] auto[0] auto[1] 976935 1 T46 6 T47 9 T51 379
auto[1] auto[1] auto[0] 1352775 1 T46 3 T47 30 T51 229
auto[1] auto[1] auto[1] 973163 1 T46 2 T47 30 T51 289


User Defined Cross Bins for cp_cross_type_en_state

Excluded/Illegal bins
NAMECOUNTSTATUS
intr_type_disabled 0 Excluded