Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4468214 |
1 |
|
|
T25 |
20 |
|
T26 |
103 |
|
T27 |
259 |
| auto[1] |
2311343 |
1 |
|
|
T28 |
43 |
|
T30 |
15 |
|
T33 |
398 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
5662663 |
1 |
|
|
T25 |
20 |
|
T26 |
103 |
|
T27 |
259 |
| auto[1] |
1116894 |
1 |
|
|
T28 |
28 |
|
T30 |
12 |
|
T33 |
278 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4468093 |
1 |
|
|
T25 |
20 |
|
T26 |
103 |
|
T27 |
259 |
| auto[1] |
2311464 |
1 |
|
|
T28 |
54 |
|
T30 |
26 |
|
T33 |
511 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
596530 |
1 |
|
|
T28 |
21 |
|
T30 |
14 |
|
T33 |
158 |
| auto[1] |
auto[0] |
auto[1] |
562199 |
1 |
|
|
T28 |
13 |
|
T30 |
12 |
|
T33 |
180 |
| auto[1] |
auto[1] |
auto[0] |
598040 |
1 |
|
|
T28 |
5 |
|
T33 |
75 |
|
T1 |
13 |
| auto[1] |
auto[1] |
auto[1] |
554695 |
1 |
|
|
T28 |
15 |
|
T33 |
98 |
|
T1 |
42 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |