Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4485568 |
1 |
|
|
T25 |
20 |
|
T26 |
103 |
|
T27 |
259 |
| auto[1] |
2293989 |
1 |
|
|
T28 |
48 |
|
T30 |
30 |
|
T33 |
505 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
5670879 |
1 |
|
|
T25 |
20 |
|
T26 |
103 |
|
T27 |
259 |
| auto[1] |
1108678 |
1 |
|
|
T28 |
50 |
|
T30 |
32 |
|
T33 |
242 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4488022 |
1 |
|
|
T25 |
20 |
|
T26 |
103 |
|
T27 |
259 |
| auto[1] |
2291535 |
1 |
|
|
T28 |
95 |
|
T30 |
42 |
|
T33 |
472 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
596169 |
1 |
|
|
T28 |
35 |
|
T30 |
10 |
|
T33 |
154 |
| auto[1] |
auto[0] |
auto[1] |
560452 |
1 |
|
|
T28 |
36 |
|
T30 |
13 |
|
T33 |
166 |
| auto[1] |
auto[1] |
auto[0] |
586688 |
1 |
|
|
T28 |
10 |
|
T33 |
76 |
|
T1 |
22 |
| auto[1] |
auto[1] |
auto[1] |
548226 |
1 |
|
|
T28 |
14 |
|
T30 |
19 |
|
T33 |
76 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |