Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6768772 |
1 |
|
|
T41 |
259 |
|
T42 |
306 |
|
T43 |
55 |
| auto[1] |
4639125 |
1 |
|
|
T46 |
25 |
|
T47 |
115 |
|
T51 |
1363 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10815410 |
1 |
|
|
T41 |
259 |
|
T42 |
306 |
|
T43 |
55 |
| auto[1] |
592487 |
1 |
|
|
T46 |
1 |
|
T47 |
6 |
|
T51 |
217 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6745490 |
1 |
|
|
T41 |
259 |
|
T42 |
306 |
|
T43 |
55 |
| auto[1] |
4662407 |
1 |
|
|
T46 |
53 |
|
T47 |
54 |
|
T51 |
1064 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2053902 |
1 |
|
|
T46 |
37 |
|
T47 |
9 |
|
T51 |
448 |
| auto[1] |
auto[0] |
auto[1] |
299024 |
1 |
|
|
T46 |
1 |
|
T47 |
1 |
|
T51 |
116 |
| auto[1] |
auto[1] |
auto[0] |
2016018 |
1 |
|
|
T46 |
15 |
|
T47 |
39 |
|
T51 |
399 |
| auto[1] |
auto[1] |
auto[1] |
293463 |
1 |
|
|
T47 |
5 |
|
T51 |
101 |
|
T79 |
4 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |