Summary for Variable intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for intr_en

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 6714630 1 T41 259 T42 306 T43 55
auto[1] 4693267 1 T46 42 T47 18 T51 1436


Summary for Variable intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for intr_state

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 10812135 1 T41 259 T42 306 T43 55
auto[1] 595762 1 T46 1 T47 5 T51 200


Summary for Variable type_ctrl_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for type_ctrl_en

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 6714693 1 T41 259 T42 306 T43 55
auto[1] 4693204 1 T46 31 T47 37 T51 1054


Summary for Cross cp_cross_type_en_state

Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY   EXPECTED   UNCOVERED   COVERED   PERCENT   MISSING   
TOTAL 4 0 4 100.00
Automatically Generated Cross Bins 4 0 4 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cp_cross_type_en_state

Bins
type_ctrl_en   intr_en   intr_state   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[1] auto[0] auto[0] 2049273 1 T46 21 T47 25 T51 434
auto[1] auto[0] auto[1] 297497 1 T46 1 T47 4 T51 101
auto[1] auto[1] auto[0] 2048169 1 T46 9 T47 7 T51 420
auto[1] auto[1] auto[1] 298265 1 T47 1 T51 99 T79 2


User Defined Cross Bins for cp_cross_type_en_state

Excluded/Illegal bins
NAMECOUNTSTATUS
intr_type_disabled 0 Excluded