Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4469872 |
1 |
|
|
T25 |
20 |
|
T26 |
103 |
|
T27 |
259 |
| auto[1] |
2309685 |
1 |
|
|
T28 |
86 |
|
T30 |
48 |
|
T33 |
797 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6486229 |
1 |
|
|
T25 |
20 |
|
T26 |
103 |
|
T27 |
259 |
| auto[1] |
293328 |
1 |
|
|
T28 |
8 |
|
T30 |
1 |
|
T33 |
93 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4471226 |
1 |
|
|
T25 |
20 |
|
T26 |
103 |
|
T27 |
259 |
| auto[1] |
2308331 |
1 |
|
|
T28 |
86 |
|
T30 |
27 |
|
T33 |
481 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1006539 |
1 |
|
|
T28 |
34 |
|
T30 |
7 |
|
T33 |
260 |
| auto[1] |
auto[0] |
auto[1] |
146853 |
1 |
|
|
T28 |
5 |
|
T33 |
57 |
|
T15 |
2 |
| auto[1] |
auto[1] |
auto[0] |
1008464 |
1 |
|
|
T28 |
44 |
|
T30 |
19 |
|
T33 |
128 |
| auto[1] |
auto[1] |
auto[1] |
146475 |
1 |
|
|
T28 |
3 |
|
T30 |
1 |
|
T33 |
36 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |