Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
4461941 |
1 |
|
|
T25 |
20 |
|
T26 |
103 |
|
T27 |
259 |
auto[1] |
2317616 |
1 |
|
|
T28 |
76 |
|
T30 |
24 |
|
T33 |
554 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
5674383 |
1 |
|
|
T25 |
20 |
|
T26 |
103 |
|
T27 |
259 |
auto[1] |
1105174 |
1 |
|
|
T28 |
67 |
|
T30 |
18 |
|
T33 |
353 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
4494570 |
1 |
|
|
T25 |
20 |
|
T26 |
103 |
|
T27 |
259 |
auto[1] |
2284987 |
1 |
|
|
T28 |
104 |
|
T30 |
25 |
|
T33 |
743 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
586007 |
1 |
|
|
T28 |
10 |
|
T30 |
7 |
|
T33 |
201 |
auto[1] |
auto[0] |
auto[1] |
551687 |
1 |
|
|
T28 |
32 |
|
T30 |
7 |
|
T33 |
195 |
auto[1] |
auto[1] |
auto[0] |
593806 |
1 |
|
|
T28 |
27 |
|
T33 |
189 |
|
T1 |
8 |
auto[1] |
auto[1] |
auto[1] |
553487 |
1 |
|
|
T28 |
35 |
|
T30 |
11 |
|
T33 |
158 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
4456688 |
1 |
|
|
T25 |
20 |
|
T26 |
103 |
|
T27 |
259 |
auto[1] |
2322869 |
1 |
|
|
T28 |
44 |
|
T30 |
17 |
|
T33 |
663 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
5661816 |
1 |
|
|
T25 |
20 |
|
T26 |
103 |
|
T27 |
259 |
auto[1] |
1117741 |
1 |
|
|
T28 |
23 |
|
T30 |
7 |
|
T33 |
355 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
4467334 |
1 |
|
|
T25 |
20 |
|
T26 |
103 |
|
T27 |
259 |
auto[1] |
2312223 |
1 |
|
|
T28 |
82 |
|
T30 |
23 |
|
T33 |
714 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
593389 |
1 |
|
|
T28 |
43 |
|
T30 |
16 |
|
T33 |
174 |
auto[1] |
auto[0] |
auto[1] |
558937 |
1 |
|
|
T28 |
18 |
|
T30 |
2 |
|
T33 |
199 |
auto[1] |
auto[1] |
auto[0] |
601093 |
1 |
|
|
T28 |
16 |
|
T33 |
185 |
|
T1 |
19 |
auto[1] |
auto[1] |
auto[1] |
558804 |
1 |
|
|
T28 |
5 |
|
T30 |
5 |
|
T33 |
156 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
4476604 |
1 |
|
|
T25 |
20 |
|
T26 |
103 |
|
T27 |
259 |
auto[1] |
2302953 |
1 |
|
|
T28 |
104 |
|
T30 |
32 |
|
T33 |
686 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
5671821 |
1 |
|
|
T25 |
20 |
|
T26 |
103 |
|
T27 |
259 |
auto[1] |
1107736 |
1 |
|
|
T28 |
56 |
|
T30 |
3 |
|
T33 |
250 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
4486369 |
1 |
|
|
T25 |
20 |
|
T26 |
103 |
|
T27 |
259 |
auto[1] |
2293188 |
1 |
|
|
T28 |
85 |
|
T30 |
25 |
|
T33 |
474 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
598346 |
1 |
|
|
T28 |
12 |
|
T30 |
9 |
|
T33 |
83 |
auto[1] |
auto[0] |
auto[1] |
558198 |
1 |
|
|
T28 |
35 |
|
T30 |
3 |
|
T33 |
95 |
auto[1] |
auto[1] |
auto[0] |
587106 |
1 |
|
|
T28 |
17 |
|
T30 |
13 |
|
T33 |
141 |
auto[1] |
auto[1] |
auto[1] |
549538 |
1 |
|
|
T28 |
21 |
|
T33 |
155 |
|
T1 |
121 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
4476811 |
1 |
|
|
T25 |
20 |
|
T26 |
103 |
|
T27 |
259 |
auto[1] |
2302746 |
1 |
|
|
T28 |
66 |
|
T30 |
11 |
|
T33 |
640 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
5666781 |
1 |
|
|
T25 |
20 |
|
T26 |
103 |
|
T27 |
259 |
auto[1] |
1112776 |
1 |
|
|
T28 |
31 |
|
T30 |
26 |
|
T33 |
287 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
4474107 |
1 |
|
|
T25 |
20 |
|
T26 |
103 |
|
T27 |
259 |
auto[1] |
2305450 |
1 |
|
|
T28 |
88 |
|
T30 |
43 |
|
T33 |
552 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
603222 |
1 |
|
|
T28 |
32 |
|
T30 |
16 |
|
T33 |
168 |
auto[1] |
auto[0] |
auto[1] |
561582 |
1 |
|
|
T28 |
23 |
|
T30 |
19 |
|
T33 |
190 |
auto[1] |
auto[1] |
auto[0] |
589452 |
1 |
|
|
T28 |
25 |
|
T30 |
1 |
|
T33 |
97 |
auto[1] |
auto[1] |
auto[1] |
551194 |
1 |
|
|
T28 |
8 |
|
T30 |
7 |
|
T33 |
97 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
4469872 |
1 |
|
|
T25 |
20 |
|
T26 |
103 |
|
T27 |
259 |
auto[1] |
2309685 |
1 |
|
|
T28 |
86 |
|
T30 |
48 |
|
T33 |
797 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
5665898 |
1 |
|
|
T25 |
20 |
|
T26 |
103 |
|
T27 |
259 |
auto[1] |
1113659 |
1 |
|
|
T28 |
32 |
|
T30 |
29 |
|
T33 |
375 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
4479269 |
1 |
|
|
T25 |
20 |
|
T26 |
103 |
|
T27 |
259 |
auto[1] |
2300288 |
1 |
|
|
T28 |
100 |
|
T30 |
39 |
|
T33 |
739 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
590832 |
1 |
|
|
T28 |
33 |
|
T30 |
9 |
|
T33 |
130 |
auto[1] |
auto[0] |
auto[1] |
557619 |
1 |
|
|
T28 |
18 |
|
T30 |
6 |
|
T33 |
155 |
auto[1] |
auto[1] |
auto[0] |
595797 |
1 |
|
|
T28 |
35 |
|
T30 |
1 |
|
T33 |
234 |
auto[1] |
auto[1] |
auto[1] |
556040 |
1 |
|
|
T28 |
14 |
|
T30 |
23 |
|
T33 |
220 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
4473852 |
1 |
|
|
T25 |
20 |
|
T26 |
103 |
|
T27 |
259 |
auto[1] |
2305705 |
1 |
|
|
T28 |
85 |
|
T30 |
47 |
|
T33 |
396 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
5663495 |
1 |
|
|
T25 |
20 |
|
T26 |
103 |
|
T27 |
259 |
auto[1] |
1116062 |
1 |
|
|
T28 |
51 |
|
T30 |
8 |
|
T33 |
301 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
4466127 |
1 |
|
|
T25 |
20 |
|
T26 |
103 |
|
T27 |
259 |
auto[1] |
2313430 |
1 |
|
|
T28 |
81 |
|
T30 |
41 |
|
T33 |
614 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
600103 |
1 |
|
|
T28 |
13 |
|
T30 |
11 |
|
T33 |
222 |
auto[1] |
auto[0] |
auto[1] |
560976 |
1 |
|
|
T28 |
31 |
|
T30 |
5 |
|
T33 |
212 |
auto[1] |
auto[1] |
auto[0] |
597265 |
1 |
|
|
T28 |
17 |
|
T30 |
22 |
|
T33 |
91 |
auto[1] |
auto[1] |
auto[1] |
555086 |
1 |
|
|
T28 |
20 |
|
T30 |
3 |
|
T33 |
89 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
4468106 |
1 |
|
|
T25 |
20 |
|
T26 |
103 |
|
T27 |
259 |
auto[1] |
2311451 |
1 |
|
|
T28 |
44 |
|
T30 |
39 |
|
T33 |
911 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
5672206 |
1 |
|
|
T25 |
20 |
|
T26 |
103 |
|
T27 |
259 |
auto[1] |
1107351 |
1 |
|
|
T28 |
53 |
|
T30 |
21 |
|
T33 |
175 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
4486046 |
1 |
|
|
T25 |
20 |
|
T26 |
103 |
|
T27 |
259 |
auto[1] |
2293511 |
1 |
|
|
T28 |
111 |
|
T30 |
33 |
|
T33 |
339 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
592729 |
1 |
|
|
T28 |
42 |
|
T30 |
8 |
|
T33 |
84 |
auto[1] |
auto[0] |
auto[1] |
552729 |
1 |
|
|
T28 |
28 |
|
T30 |
5 |
|
T33 |
90 |
auto[1] |
auto[1] |
auto[0] |
593431 |
1 |
|
|
T28 |
16 |
|
T30 |
4 |
|
T33 |
80 |
auto[1] |
auto[1] |
auto[1] |
554622 |
1 |
|
|
T28 |
25 |
|
T30 |
16 |
|
T33 |
85 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
4464086 |
1 |
|
|
T25 |
20 |
|
T26 |
103 |
|
T27 |
259 |
auto[1] |
2315471 |
1 |
|
|
T28 |
41 |
|
T30 |
8 |
|
T33 |
369 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
5674026 |
1 |
|
|
T25 |
20 |
|
T26 |
103 |
|
T27 |
259 |
auto[1] |
1105531 |
1 |
|
|
T28 |
36 |
|
T30 |
11 |
|
T33 |
380 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
4491248 |
1 |
|
|
T25 |
20 |
|
T26 |
103 |
|
T27 |
259 |
auto[1] |
2288309 |
1 |
|
|
T28 |
76 |
|
T30 |
25 |
|
T33 |
686 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
594768 |
1 |
|
|
T28 |
33 |
|
T30 |
11 |
|
T33 |
224 |
auto[1] |
auto[0] |
auto[1] |
554859 |
1 |
|
|
T28 |
25 |
|
T30 |
11 |
|
T33 |
285 |
auto[1] |
auto[1] |
auto[0] |
588010 |
1 |
|
|
T28 |
7 |
|
T30 |
3 |
|
T33 |
82 |
auto[1] |
auto[1] |
auto[1] |
550672 |
1 |
|
|
T28 |
11 |
|
T33 |
95 |
|
T1 |
108 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
4478193 |
1 |
|
|
T25 |
20 |
|
T26 |
103 |
|
T27 |
259 |
auto[1] |
2301364 |
1 |
|
|
T28 |
40 |
|
T30 |
49 |
|
T33 |
693 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
5670629 |
1 |
|
|
T25 |
20 |
|
T26 |
103 |
|
T27 |
259 |
auto[1] |
1108928 |
1 |
|
|
T28 |
33 |
|
T30 |
38 |
|
T33 |
383 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
4486390 |
1 |
|
|
T25 |
20 |
|
T26 |
103 |
|
T27 |
259 |
auto[1] |
2293167 |
1 |
|
|
T28 |
81 |
|
T30 |
39 |
|
T33 |
747 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
597121 |
1 |
|
|
T28 |
32 |
|
T30 |
1 |
|
T33 |
206 |
auto[1] |
auto[0] |
auto[1] |
558346 |
1 |
|
|
T28 |
33 |
|
T30 |
16 |
|
T33 |
234 |
auto[1] |
auto[1] |
auto[0] |
587118 |
1 |
|
|
T28 |
16 |
|
T33 |
158 |
|
T1 |
21 |
auto[1] |
auto[1] |
auto[1] |
550582 |
1 |
|
|
T30 |
22 |
|
T33 |
149 |
|
T1 |
114 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
4460073 |
1 |
|
|
T25 |
20 |
|
T26 |
103 |
|
T27 |
259 |
auto[1] |
2319484 |
1 |
|
|
T28 |
90 |
|
T30 |
50 |
|
T33 |
708 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
5664729 |
1 |
|
|
T25 |
20 |
|
T26 |
103 |
|
T27 |
259 |
auto[1] |
1114828 |
1 |
|
|
T28 |
20 |
|
T30 |
21 |
|
T33 |
260 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
4476368 |
1 |
|
|
T25 |
20 |
|
T26 |
103 |
|
T27 |
259 |
auto[1] |
2303189 |
1 |
|
|
T28 |
42 |
|
T30 |
25 |
|
T33 |
569 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
595147 |
1 |
|
|
T28 |
3 |
|
T30 |
3 |
|
T33 |
143 |
auto[1] |
auto[0] |
auto[1] |
555010 |
1 |
|
|
T28 |
19 |
|
T30 |
11 |
|
T33 |
125 |
auto[1] |
auto[1] |
auto[0] |
593214 |
1 |
|
|
T28 |
19 |
|
T30 |
1 |
|
T33 |
166 |
auto[1] |
auto[1] |
auto[1] |
559818 |
1 |
|
|
T28 |
1 |
|
T30 |
10 |
|
T33 |
135 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
4477436 |
1 |
|
|
T25 |
20 |
|
T26 |
103 |
|
T27 |
259 |
auto[1] |
2302121 |
1 |
|
|
T28 |
81 |
|
T30 |
16 |
|
T33 |
634 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
5675612 |
1 |
|
|
T25 |
20 |
|
T26 |
103 |
|
T27 |
259 |
auto[1] |
1103945 |
1 |
|
|
T28 |
86 |
|
T30 |
15 |
|
T33 |
302 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
4499547 |
1 |
|
|
T25 |
20 |
|
T26 |
103 |
|
T27 |
259 |
auto[1] |
2280010 |
1 |
|
|
T28 |
130 |
|
T30 |
48 |
|
T33 |
634 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
591034 |
1 |
|
|
T28 |
17 |
|
T30 |
23 |
|
T33 |
216 |
auto[1] |
auto[0] |
auto[1] |
553769 |
1 |
|
|
T28 |
37 |
|
T30 |
12 |
|
T33 |
175 |
auto[1] |
auto[1] |
auto[0] |
585031 |
1 |
|
|
T28 |
27 |
|
T30 |
10 |
|
T33 |
116 |
auto[1] |
auto[1] |
auto[1] |
550176 |
1 |
|
|
T28 |
49 |
|
T30 |
3 |
|
T33 |
127 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
4462025 |
1 |
|
|
T25 |
20 |
|
T26 |
103 |
|
T27 |
259 |
auto[1] |
2317532 |
1 |
|
|
T28 |
38 |
|
T30 |
42 |
|
T33 |
837 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
5669779 |
1 |
|
|
T25 |
20 |
|
T26 |
103 |
|
T27 |
259 |
auto[1] |
1109778 |
1 |
|
|
T28 |
56 |
|
T33 |
240 |
|
T1 |
134 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
4486988 |
1 |
|
|
T25 |
20 |
|
T26 |
103 |
|
T27 |
259 |
auto[1] |
2292569 |
1 |
|
|
T28 |
95 |
|
T30 |
7 |
|
T33 |
462 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
587792 |
1 |
|
|
T28 |
32 |
|
T30 |
4 |
|
T33 |
59 |
auto[1] |
auto[0] |
auto[1] |
553140 |
1 |
|
|
T28 |
45 |
|
T33 |
86 |
|
T1 |
60 |
auto[1] |
auto[1] |
auto[0] |
594999 |
1 |
|
|
T28 |
7 |
|
T30 |
3 |
|
T33 |
163 |
auto[1] |
auto[1] |
auto[1] |
556638 |
1 |
|
|
T28 |
11 |
|
T33 |
154 |
|
T1 |
74 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
4481400 |
1 |
|
|
T25 |
20 |
|
T26 |
103 |
|
T27 |
259 |
auto[1] |
2298157 |
1 |
|
|
T28 |
87 |
|
T30 |
44 |
|
T33 |
278 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
5664378 |
1 |
|
|
T25 |
20 |
|
T26 |
103 |
|
T27 |
259 |
auto[1] |
1115179 |
1 |
|
|
T28 |
57 |
|
T30 |
7 |
|
T33 |
425 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
4471178 |
1 |
|
|
T25 |
20 |
|
T26 |
103 |
|
T27 |
259 |
auto[1] |
2308379 |
1 |
|
|
T28 |
77 |
|
T30 |
38 |
|
T33 |
832 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
597543 |
1 |
|
|
T28 |
12 |
|
T30 |
10 |
|
T33 |
327 |
auto[1] |
auto[0] |
auto[1] |
559034 |
1 |
|
|
T28 |
32 |
|
T30 |
5 |
|
T33 |
335 |
auto[1] |
auto[1] |
auto[0] |
595657 |
1 |
|
|
T28 |
8 |
|
T30 |
21 |
|
T33 |
80 |
auto[1] |
auto[1] |
auto[1] |
556145 |
1 |
|
|
T28 |
25 |
|
T30 |
2 |
|
T33 |
90 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |