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Group Instance : intr_event_lvllow_pin21
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance intr_event_lvllow_pin21

CATEGORY   EXPECTED   UNCOVERED   COVERED   PERCENT   
Variables 6 0 6 100.00
Crosses 4 0 4 100.00


Variables for Group Instance intr_event_lvllow_pin21
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
intr_en 2 0 2 100.00 100 1 1 2
intr_state 2 0 2 100.00 100 1 1 2
type_ctrl_en 2 0 2 100.00 100 1 1 2


Crosses for Group Instance intr_event_lvllow_pin21
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cp_cross_type_en_state 4 0 4 100.00 100 1 1 0


Group Instance : intr_event_lvllow_pin22
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance intr_event_lvllow_pin22

CATEGORY   EXPECTED   UNCOVERED   COVERED   PERCENT   
Variables 6 0 6 100.00
Crosses 4 0 4 100.00


Variables for Group Instance intr_event_lvllow_pin22
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
intr_en 2 0 2 100.00 100 1 1 2
intr_state 2 0 2 100.00 100 1 1 2
type_ctrl_en 2 0 2 100.00 100 1 1 2


Crosses for Group Instance intr_event_lvllow_pin22
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cp_cross_type_en_state 4 0 4 100.00 100 1 1 0


Group Instance : intr_event_lvllow_pin23
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance intr_event_lvllow_pin23

CATEGORY   EXPECTED   UNCOVERED   COVERED   PERCENT   
Variables 6 0 6 100.00
Crosses 4 0 4 100.00


Variables for Group Instance intr_event_lvllow_pin23
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
intr_en 2 0 2 100.00 100 1 1 2
intr_state 2 0 2 100.00 100 1 1 2
type_ctrl_en 2 0 2 100.00 100 1 1 2


Crosses for Group Instance intr_event_lvllow_pin23
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cp_cross_type_en_state 4 0 4 100.00 100 1 1 0


Group Instance : intr_event_lvllow_pin24
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance intr_event_lvllow_pin24

CATEGORY   EXPECTED   UNCOVERED   COVERED   PERCENT   
Variables 6 0 6 100.00
Crosses 4 0 4 100.00


Variables for Group Instance intr_event_lvllow_pin24
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
intr_en 2 0 2 100.00 100 1 1 2
intr_state 2 0 2 100.00 100 1 1 2
type_ctrl_en 2 0 2 100.00 100 1 1 2


Crosses for Group Instance intr_event_lvllow_pin24
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cp_cross_type_en_state 4 0 4 100.00 100 1 1 0


Group Instance : intr_event_lvllow_pin25
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance intr_event_lvllow_pin25

CATEGORY   EXPECTED   UNCOVERED   COVERED   PERCENT   
Variables 6 0 6 100.00
Crosses 4 0 4 100.00


Variables for Group Instance intr_event_lvllow_pin25
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
intr_en 2 0 2 100.00 100 1 1 2
intr_state 2 0 2 100.00 100 1 1 2
type_ctrl_en 2 0 2 100.00 100 1 1 2


Crosses for Group Instance intr_event_lvllow_pin25
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cp_cross_type_en_state 4 0 4 100.00 100 1 1 0


Group Instance : intr_event_lvllow_pin26
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance intr_event_lvllow_pin26

CATEGORY   EXPECTED   UNCOVERED   COVERED   PERCENT   
Variables 6 0 6 100.00
Crosses 4 0 4 100.00


Variables for Group Instance intr_event_lvllow_pin26
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
intr_en 2 0 2 100.00 100 1 1 2
intr_state 2 0 2 100.00 100 1 1 2
type_ctrl_en 2 0 2 100.00 100 1 1 2


Crosses for Group Instance intr_event_lvllow_pin26
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cp_cross_type_en_state 4 0 4 100.00 100 1 1 0


Group Instance : intr_event_lvllow_pin27
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance intr_event_lvllow_pin27

CATEGORY   EXPECTED   UNCOVERED   COVERED   PERCENT   
Variables 6 0 6 100.00
Crosses 4 0 4 100.00


Variables for Group Instance intr_event_lvllow_pin27
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
intr_en 2 0 2 100.00 100 1 1 2
intr_state 2 0 2 100.00 100 1 1 2
type_ctrl_en 2 0 2 100.00 100 1 1 2


Crosses for Group Instance intr_event_lvllow_pin27
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cp_cross_type_en_state 4 0 4 100.00 100 1 1 0


Group Instance : intr_event_lvllow_pin28
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance intr_event_lvllow_pin28

CATEGORY   EXPECTED   UNCOVERED   COVERED   PERCENT   
Variables 6 0 6 100.00
Crosses 4 0 4 100.00


Variables for Group Instance intr_event_lvllow_pin28
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
intr_en 2 0 2 100.00 100 1 1 2
intr_state 2 0 2 100.00 100 1 1 2
type_ctrl_en 2 0 2 100.00 100 1 1 2


Crosses for Group Instance intr_event_lvllow_pin28
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cp_cross_type_en_state 4 0 4 100.00 100 1 1 0


Group Instance : intr_event_lvllow_pin29
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance intr_event_lvllow_pin29

CATEGORY   EXPECTED   UNCOVERED   COVERED   PERCENT   
Variables 6 0 6 100.00
Crosses 4 0 4 100.00


Variables for Group Instance intr_event_lvllow_pin29
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
intr_en 2 0 2 100.00 100 1 1 2
intr_state 2 0 2 100.00 100 1 1 2
type_ctrl_en 2 0 2 100.00 100 1 1 2


Crosses for Group Instance intr_event_lvllow_pin29
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cp_cross_type_en_state 4 0 4 100.00 100 1 1 0


Group Instance : intr_event_lvllow_pin3
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance intr_event_lvllow_pin3

CATEGORY   EXPECTED   UNCOVERED   COVERED   PERCENT   
Variables 6 0 6 100.00
Crosses 4 0 4 100.00


Variables for Group Instance intr_event_lvllow_pin3
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
intr_en 2 0 2 100.00 100 1 1 2
intr_state 2 0 2 100.00 100 1 1 2
type_ctrl_en 2 0 2 100.00 100 1 1 2


Crosses for Group Instance intr_event_lvllow_pin3
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cp_cross_type_en_state 4 0 4 100.00 100 1 1 0


Group Instance : intr_event_lvllow_pin30
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance intr_event_lvllow_pin30

CATEGORY   EXPECTED   UNCOVERED   COVERED   PERCENT   
Variables 6 0 6 100.00
Crosses 4 0 4 100.00


Variables for Group Instance intr_event_lvllow_pin30
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
intr_en 2 0 2 100.00 100 1 1 2
intr_state 2 0 2 100.00 100 1 1 2
type_ctrl_en 2 0 2 100.00 100 1 1 2


Crosses for Group Instance intr_event_lvllow_pin30
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cp_cross_type_en_state 4 0 4 100.00 100 1 1 0


Group Instance : intr_event_lvllow_pin31
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance intr_event_lvllow_pin31

CATEGORY   EXPECTED   UNCOVERED   COVERED   PERCENT   
Variables 6 0 6 100.00
Crosses 4 0 4 100.00


Variables for Group Instance intr_event_lvllow_pin31
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
intr_en 2 0 2 100.00 100 1 1 2
intr_state 2 0 2 100.00 100 1 1 2
type_ctrl_en 2 0 2 100.00 100 1 1 2


Crosses for Group Instance intr_event_lvllow_pin31
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cp_cross_type_en_state 4 0 4 100.00 100 1 1 0


Group Instance : intr_event_lvllow_pin4
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance intr_event_lvllow_pin4

CATEGORY   EXPECTED   UNCOVERED   COVERED   PERCENT   
Variables 6 0 6 100.00
Crosses 4 0 4 100.00


Variables for Group Instance intr_event_lvllow_pin4
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
intr_en 2 0 2 100.00 100 1 1 2
intr_state 2 0 2 100.00 100 1 1 2
type_ctrl_en 2 0 2 100.00 100 1 1 2


Crosses for Group Instance intr_event_lvllow_pin4
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cp_cross_type_en_state 4 0 4 100.00 100 1 1 0


Group Instance : intr_event_lvllow_pin5
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance intr_event_lvllow_pin5

CATEGORY   EXPECTED   UNCOVERED   COVERED   PERCENT   
Variables 6 0 6 100.00
Crosses 4 0 4 100.00


Variables for Group Instance intr_event_lvllow_pin5
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
intr_en 2 0 2 100.00 100 1 1 2
intr_state 2 0 2 100.00 100 1 1 2
type_ctrl_en 2 0 2 100.00 100 1 1 2


Crosses for Group Instance intr_event_lvllow_pin5
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cp_cross_type_en_state 4 0 4 100.00 100 1 1 0

Go back
Group Instances:
intr_event_lvllow_pin21
intr_event_lvllow_pin22
intr_event_lvllow_pin23
intr_event_lvllow_pin24
intr_event_lvllow_pin25
intr_event_lvllow_pin26
intr_event_lvllow_pin27
intr_event_lvllow_pin28
intr_event_lvllow_pin29
intr_event_lvllow_pin3
intr_event_lvllow_pin30
intr_event_lvllow_pin31
intr_event_lvllow_pin4
intr_event_lvllow_pin5

Summary for Variable intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for intr_en

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 6717806 1 T41 259 T42 306 T43 55
auto[1] 4690091 1 T46 24 T47 19 T51 1089


Summary for Variable intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for intr_state

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 8704389 1 T41 259 T42 306 T43 55
auto[1] 2703508 1 T47 42 T51 526 T64 44


Summary for Variable type_ctrl_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for type_ctrl_en

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 6752637 1 T41 259 T42 306 T43 55
auto[1] 4655260 1 T46 3 T47 103 T51 1110


Summary for Cross cp_cross_type_en_state

Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY   EXPECTED   UNCOVERED   COVERED   PERCENT   MISSING   
TOTAL 4 0 4 100.00
Automatically Generated Cross Bins 4 0 4 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cp_cross_type_en_state

Bins
type_ctrl_en   intr_en   intr_state   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[1] auto[0] auto[0] 974789 1 T47 55 T51 314 T64 6
auto[1] auto[0] auto[1] 1353025 1 T47 37 T51 308 T64 17
auto[1] auto[1] auto[0] 976963 1 T46 3 T47 6 T51 270
auto[1] auto[1] auto[1] 1350483 1 T47 5 T51 218 T64 27


User Defined Cross Bins for cp_cross_type_en_state

Excluded/Illegal bins
NAMECOUNTSTATUS
intr_type_disabled 0 Excluded


Summary for Variable intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for intr_en

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 6737147 1 T41 259 T42 306 T43 55
auto[1] 4670750 1 T46 48 T47 101 T51 1294


Summary for Variable intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for intr_state

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 8690154 1 T41 259 T42 306 T43 55
auto[1] 2717743 1 T46 19 T47 17 T51 587


Summary for Variable type_ctrl_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for type_ctrl_en

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 6736464 1 T41 259 T42 306 T43 55
auto[1] 4671433 1 T46 27 T47 42 T51 1188


Summary for Cross cp_cross_type_en_state

Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY   EXPECTED   UNCOVERED   COVERED   PERCENT   MISSING   
TOTAL 4 0 4 100.00
Automatically Generated Cross Bins 4 0 4 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cp_cross_type_en_state

Bins
type_ctrl_en   intr_en   intr_state   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[1] auto[0] auto[0] 985450 1 T46 8 T47 13 T51 302
auto[1] auto[0] auto[1] 1368315 1 T46 7 T47 2 T51 288
auto[1] auto[1] auto[0] 968240 1 T47 12 T51 299 T64 11
auto[1] auto[1] auto[1] 1349428 1 T46 12 T47 15 T51 299


User Defined Cross Bins for cp_cross_type_en_state

Excluded/Illegal bins
NAMECOUNTSTATUS
intr_type_disabled 0 Excluded


Summary for Variable intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for intr_en

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 6739334 1 T41 259 T42 306 T43 55
auto[1] 4668563 1 T46 28 T47 99 T51 1173


Summary for Variable intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for intr_state

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 8683740 1 T41 259 T42 306 T43 55
auto[1] 2724157 1 T46 11 T47 14 T51 603


Summary for Variable type_ctrl_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for type_ctrl_en

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 6722639 1 T41 259 T42 306 T43 55
auto[1] 4685258 1 T46 25 T47 30 T51 1196


Summary for Cross cp_cross_type_en_state

Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY   EXPECTED   UNCOVERED   COVERED   PERCENT   MISSING   
TOTAL 4 0 4 100.00
Automatically Generated Cross Bins 4 0 4 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cp_cross_type_en_state

Bins
type_ctrl_en   intr_en   intr_state   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[1] auto[0] auto[0] 982221 1 T46 8 T47 4 T51 310
auto[1] auto[0] auto[1] 1366718 1 T46 5 T47 5 T51 310
auto[1] auto[1] auto[0] 978880 1 T46 6 T47 12 T51 283
auto[1] auto[1] auto[1] 1357439 1 T46 6 T47 9 T51 293


User Defined Cross Bins for cp_cross_type_en_state

Excluded/Illegal bins
NAMECOUNTSTATUS
intr_type_disabled 0 Excluded


Summary for Variable intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for intr_en

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 6717990 1 T41 259 T42 306 T43 55
auto[1] 4689907 1 T46 39 T47 93 T51 1417


Summary for Variable intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for intr_state

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 8699930 1 T41 259 T42 306 T43 55
auto[1] 2707967 1 T46 3 T47 67 T51 741


Summary for Variable type_ctrl_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for type_ctrl_en

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 6745565 1 T41 259 T42 306 T43 55
auto[1] 4662332 1 T46 8 T47 102 T51 1529


Summary for Cross cp_cross_type_en_state

Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY   EXPECTED   UNCOVERED   COVERED   PERCENT   MISSING   
TOTAL 4 0 4 100.00
Automatically Generated Cross Bins 4 0 4 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cp_cross_type_en_state

Bins
type_ctrl_en   intr_en   intr_state   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[1] auto[0] auto[0] 977174 1 T46 2 T47 1 T51 349
auto[1] auto[0] auto[1] 1351100 1 T47 27 T51 323 T64 26
auto[1] auto[1] auto[0] 977191 1 T46 3 T47 34 T51 439
auto[1] auto[1] auto[1] 1356867 1 T46 3 T47 40 T51 418


User Defined Cross Bins for cp_cross_type_en_state

Excluded/Illegal bins
NAMECOUNTSTATUS
intr_type_disabled 0 Excluded


Summary for Variable intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for intr_en

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 6716133 1 T41 259 T42 306 T43 55
auto[1] 4691764 1 T46 30 T47 49 T51 1367


Summary for Variable intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for intr_state

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 8686115 1 T41 259 T42 306 T43 55
auto[1] 2721782 1 T46 13 T47 26 T51 850


Summary for Variable type_ctrl_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for type_ctrl_en

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 6722651 1 T41 259 T42 306 T43 55
auto[1] 4685246 1 T46 30 T47 45 T51 1689


Summary for Cross cp_cross_type_en_state

Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY   EXPECTED   UNCOVERED   COVERED   PERCENT   MISSING   
TOTAL 4 0 4 100.00
Automatically Generated Cross Bins 4 0 4 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cp_cross_type_en_state

Bins
type_ctrl_en   intr_en   intr_state   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[1] auto[0] auto[0] 984485 1 T46 10 T47 12 T51 372
auto[1] auto[0] auto[1] 1361321 1 T46 4 T47 17 T51 416
auto[1] auto[1] auto[0] 978979 1 T46 7 T47 7 T51 467
auto[1] auto[1] auto[1] 1360461 1 T46 9 T47 9 T51 434


User Defined Cross Bins for cp_cross_type_en_state

Excluded/Illegal bins
NAMECOUNTSTATUS
intr_type_disabled 0 Excluded


Summary for Variable intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for intr_en

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 6750994 1 T41 259 T42 306 T43 55
auto[1] 4656903 1 T46 28 T47 82 T51 1170


Summary for Variable intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for intr_state

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 8703739 1 T41 259 T42 306 T43 55
auto[1] 2704158 1 T46 13 T47 44 T51 698


Summary for Variable type_ctrl_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for type_ctrl_en

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 6756076 1 T41 259 T42 306 T43 55
auto[1] 4651821 1 T46 30 T47 64 T51 1440


Summary for Cross cp_cross_type_en_state

Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY   EXPECTED   UNCOVERED   COVERED   PERCENT   MISSING   
TOTAL 4 0 4 100.00
Automatically Generated Cross Bins 4 0 4 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cp_cross_type_en_state

Bins
type_ctrl_en   intr_en   intr_state   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[1] auto[0] auto[0] 980265 1 T46 17 T47 9 T51 410
auto[1] auto[0] auto[1] 1363068 1 T46 10 T47 16 T51 356
auto[1] auto[1] auto[0] 967398 1 T47 11 T51 332 T64 8
auto[1] auto[1] auto[1] 1341090 1 T46 3 T47 28 T51 342


User Defined Cross Bins for cp_cross_type_en_state

Excluded/Illegal bins
NAMECOUNTSTATUS
intr_type_disabled 0 Excluded


Summary for Variable intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for intr_en

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 6768772 1 T41 259 T42 306 T43 55
auto[1] 4639125 1 T46 25 T47 115 T51 1363


Summary for Variable intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for intr_state

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 8701032 1 T41 259 T42 306 T43 55
auto[1] 2706865 1 T46 8 T47 42 T51 702


Summary for Variable type_ctrl_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for type_ctrl_en

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 6747657 1 T41 259 T42 306 T43 55
auto[1] 4660240 1 T46 18 T47 77 T51 1321


Summary for Cross cp_cross_type_en_state

Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY   EXPECTED   UNCOVERED   COVERED   PERCENT   MISSING   
TOTAL 4 0 4 100.00
Automatically Generated Cross Bins 4 0 4 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cp_cross_type_en_state

Bins
type_ctrl_en   intr_en   intr_state   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[1] auto[0] auto[0] 984707 1 T46 3 T47 6 T51 259
auto[1] auto[0] auto[1] 1368364 1 T46 8 T51 299 T64 9
auto[1] auto[1] auto[0] 968668 1 T46 7 T47 29 T51 360
auto[1] auto[1] auto[1] 1338501 1 T47 42 T51 403 T64 21


User Defined Cross Bins for cp_cross_type_en_state

Excluded/Illegal bins
NAMECOUNTSTATUS
intr_type_disabled 0 Excluded


Summary for Variable intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for intr_en

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 6714630 1 T41 259 T42 306 T43 55
auto[1] 4693267 1 T46 42 T47 18 T51 1436


Summary for Variable intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for intr_state

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 8681997 1 T41 259 T42 306 T43 55
auto[1] 2725900 1 T46 11 T47 28 T51 559


Summary for Variable type_ctrl_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for type_ctrl_en

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 6719821 1 T41 259 T42 306 T43 55
auto[1] 4688076 1 T46 17 T47 47 T51 1172


Summary for Cross cp_cross_type_en_state

Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY   EXPECTED   UNCOVERED   COVERED   PERCENT   MISSING   
TOTAL 4 0 4 100.00
Automatically Generated Cross Bins 4 0 4 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cp_cross_type_en_state

Bins
type_ctrl_en   intr_en   intr_state   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[1] auto[0] auto[0] 981447 1 T46 2 T47 18 T51 290
auto[1] auto[0] auto[1] 1366947 1 T47 28 T51 260 T64 16
auto[1] auto[1] auto[0] 980729 1 T46 4 T47 1 T51 323
auto[1] auto[1] auto[1] 1358953 1 T46 11 T51 299 T64 14


User Defined Cross Bins for cp_cross_type_en_state

Excluded/Illegal bins
NAMECOUNTSTATUS
intr_type_disabled 0 Excluded


Summary for Variable intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for intr_en

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 6746644 1 T41 259 T42 306 T43 55
auto[1] 4661253 1 T46 21 T47 111 T51 1199


Summary for Variable intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for intr_state

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 8692080 1 T41 259 T42 306 T43 55
auto[1] 2715817 1 T46 8 T47 30 T51 708


Summary for Variable type_ctrl_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for type_ctrl_en

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 6740280 1 T41 259 T42 306 T43 55
auto[1] 4667617 1 T46 17 T47 76 T51 1409


Summary for Cross cp_cross_type_en_state

Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY   EXPECTED   UNCOVERED   COVERED   PERCENT   MISSING   
TOTAL 4 0 4 100.00
Automatically Generated Cross Bins 4 0 4 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cp_cross_type_en_state

Bins
type_ctrl_en   intr_en   intr_state   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[1] auto[0] auto[0] 979899 1 T46 9 T47 15 T51 318
auto[1] auto[0] auto[1] 1367231 1 T46 8 T47 3 T51 354
auto[1] auto[1] auto[0] 971901 1 T47 31 T51 383 T64 8
auto[1] auto[1] auto[1] 1348586 1 T47 27 T51 354 T64 26


User Defined Cross Bins for cp_cross_type_en_state

Excluded/Illegal bins
NAMECOUNTSTATUS
intr_type_disabled 0 Excluded


Summary for Variable intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for intr_en

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 6713808 1 T41 259 T42 306 T43 55
auto[1] 4694089 1 T46 24 T47 65 T51 1281


Summary for Variable intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for intr_state

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 8684616 1 T41 259 T42 306 T43 55
auto[1] 2723281 1 T46 18 T47 19 T51 587


Summary for Variable type_ctrl_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for type_ctrl_en

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 6732073 1 T41 259 T42 306 T43 55
auto[1] 4675824 1 T46 30 T47 49 T51 1209


Summary for Cross cp_cross_type_en_state

Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY   EXPECTED   UNCOVERED   COVERED   PERCENT   MISSING   
TOTAL 4 0 4 100.00
Automatically Generated Cross Bins 4 0 4 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cp_cross_type_en_state

Bins
type_ctrl_en   intr_en   intr_state   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[1] auto[0] auto[0] 973916 1 T46 12 T47 27 T51 271
auto[1] auto[0] auto[1] 1350554 1 T46 11 T47 9 T51 259
auto[1] auto[1] auto[0] 978627 1 T47 3 T51 351 T64 1
auto[1] auto[1] auto[1] 1372727 1 T46 7 T47 10 T51 328


User Defined Cross Bins for cp_cross_type_en_state

Excluded/Illegal bins
NAMECOUNTSTATUS
intr_type_disabled 0 Excluded


Summary for Variable intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for intr_en

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 6722447 1 T41 259 T42 306 T43 55
auto[1] 4685450 1 T46 15 T47 41 T51 1036


Summary for Variable intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for intr_state

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 8696571 1 T41 259 T42 306 T43 55
auto[1] 2711326 1 T47 43 T51 593 T64 32


Summary for Variable type_ctrl_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for type_ctrl_en

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 6739977 1 T41 259 T42 306 T43 55
auto[1] 4667920 1 T47 59 T51 1197 T64 60


Summary for Cross cp_cross_type_en_state

Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY   EXPECTED   UNCOVERED   COVERED   PERCENT   MISSING   
TOTAL 4 0 4 100.00
Automatically Generated Cross Bins 4 0 4 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cp_cross_type_en_state

Bins
type_ctrl_en   intr_en   intr_state   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[1] auto[0] auto[0] 978389 1 T47 8 T51 364 T64 12
auto[1] auto[0] auto[1] 1357280 1 T47 28 T51 357 T64 15
auto[1] auto[1] auto[0] 978205 1 T47 8 T51 240 T64 16
auto[1] auto[1] auto[1] 1354046 1 T47 15 T51 236 T64 17


User Defined Cross Bins for cp_cross_type_en_state

Excluded/Illegal bins
NAMECOUNTSTATUS
intr_type_disabled 0 Excluded


Summary for Variable intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for intr_en

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 6738809 1 T41 259 T42 306 T43 55
auto[1] 4669088 1 T46 27 T47 74 T51 1166


Summary for Variable intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for intr_state

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 8679572 1 T41 259 T42 306 T43 55
auto[1] 2728325 1 T46 3 T47 41 T51 623


Summary for Variable type_ctrl_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for type_ctrl_en

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 6723826 1 T41 259 T42 306 T43 55
auto[1] 4684071 1 T46 3 T47 93 T51 1256


Summary for Cross cp_cross_type_en_state

Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY   EXPECTED   UNCOVERED   COVERED   PERCENT   MISSING   
TOTAL 4 0 4 100.00
Automatically Generated Cross Bins 4 0 4 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cp_cross_type_en_state

Bins
type_ctrl_en   intr_en   intr_state   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[1] auto[0] auto[0] 977218 1 T47 25 T51 377 T64 8
auto[1] auto[0] auto[1] 1365352 1 T46 3 T47 15 T51 358
auto[1] auto[1] auto[0] 978528 1 T47 27 T51 256 T64 25
auto[1] auto[1] auto[1] 1362973 1 T47 26 T51 265 T64 24


User Defined Cross Bins for cp_cross_type_en_state

Excluded/Illegal bins
NAMECOUNTSTATUS
intr_type_disabled 0 Excluded


Summary for Variable intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for intr_en

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 6727469 1 T41 259 T42 306 T43 55
auto[1] 4680428 1 T46 24 T47 64 T51 1233


Summary for Variable intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for intr_state

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 8704604 1 T41 259 T42 306 T43 55
auto[1] 2703293 1 T46 3 T47 32 T51 669


Summary for Variable type_ctrl_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for type_ctrl_en

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 6758233 1 T41 259 T42 306 T43 55
auto[1] 4649664 1 T46 6 T47 62 T51 1371


Summary for Cross cp_cross_type_en_state

Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY   EXPECTED   UNCOVERED   COVERED   PERCENT   MISSING   
TOTAL 4 0 4 100.00
Automatically Generated Cross Bins 4 0 4 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cp_cross_type_en_state

Bins
type_ctrl_en   intr_en   intr_state   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[1] auto[0] auto[0] 971266 1 T46 3 T47 14 T51 348
auto[1] auto[0] auto[1] 1345052 1 T47 9 T51 354 T64 15
auto[1] auto[1] auto[0] 975105 1 T47 16 T51 354 T64 3
auto[1] auto[1] auto[1] 1358241 1 T46 3 T47 23 T51 315


User Defined Cross Bins for cp_cross_type_en_state

Excluded/Illegal bins
NAMECOUNTSTATUS
intr_type_disabled 0 Excluded


Summary for Variable intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for intr_en

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 6737938 1 T41 259 T42 306 T43 55
auto[1] 4669959 1 T46 25 T47 39 T51 1135


Summary for Variable intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for intr_state

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 8691163 1 T41 259 T42 306 T43 55
auto[1] 2716734 1 T47 50 T51 693 T64 26


Summary for Variable type_ctrl_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for type_ctrl_en

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 6743716 1 T41 259 T42 306 T43 55
auto[1] 4664181 1 T46 3 T47 107 T51 1343


Summary for Cross cp_cross_type_en_state

Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY   EXPECTED   UNCOVERED   COVERED   PERCENT   MISSING   
TOTAL 4 0 4 100.00
Automatically Generated Cross Bins 4 0 4 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cp_cross_type_en_state

Bins
type_ctrl_en   intr_en   intr_state   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[1] auto[0] auto[0] 975812 1 T47 42 T51 385 T64 32
auto[1] auto[0] auto[1] 1366191 1 T47 44 T51 420 T64 12
auto[1] auto[1] auto[0] 971635 1 T46 3 T47 15 T51 265
auto[1] auto[1] auto[1] 1350543 1 T47 6 T51 273 T64 14


User Defined Cross Bins for cp_cross_type_en_state

Excluded/Illegal bins
NAMECOUNTSTATUS
intr_type_disabled 0 Excluded