HMAC Simulation Results

Thursday May 18 2023 07:04:58 UTC

GitHub Revision: `ac0bef2ce`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 2907120974

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	hmac_smoke	4.380s	1.654ms	50	50	100.00
V1	csr_hw_reset	hmac_csr_hw_reset	0.660s	66.895us	5	5	100.00
V1	csr_rw	hmac_csr_rw	0.750s	333.176us	20	20	100.00
V1	csr_bit_bash	hmac_csr_bit_bash	9.120s	862.700us	5	5	100.00
V1	csr_aliasing	hmac_csr_aliasing	2.590s	136.228us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	hmac_csr_mem_rw_with_rand_reset	24.911m	859.004ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	hmac_csr_rw	0.750s	333.176us	20	20	100.00
		hmac_csr_aliasing	2.590s	136.228us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	long_msg	hmac_long_msg	1.704m	23.294ms	50	50	100.00
V2	back_pressure	hmac_back_pressure	58.330s	4.378ms	50	50	100.00
V2	test_vectors	hmac_test_sha_vectors	7.986m	32.158ms	46	50	92.00
		hmac_test_hmac_vectors	1.200s	203.049us	50	50	100.00
V2	burst_wr	hmac_burst_wr	1.119m	5.887ms	50	50	100.00
V2	datapath_stress	hmac_datapath_stress	2.212m	5.303ms	50	50	100.00
V2	error	hmac_error	3.619m	39.784ms	48	50	96.00
V2	wipe_secret	hmac_wipe_secret	1.547m	15.973ms	50	50	100.00
V2	stress_all	hmac_stress_all	36.451m	947.318ms	50	50	100.00
V2	alert_test	hmac_alert_test	0.620s	45.553us	50	50	100.00
V2	intr_test	hmac_intr_test	0.630s	15.424us	50	50	100.00
V2	tl_d_oob_addr_access	hmac_tl_errors	4.230s	232.334us	20	20	100.00
V2	tl_d_illegal_access	hmac_tl_errors	4.230s	232.334us	20	20	100.00
V2	tl_d_outstanding_access	hmac_csr_hw_reset	0.660s	66.895us	5	5	100.00
		hmac_csr_rw	0.750s	333.176us	20	20	100.00
		hmac_csr_aliasing	2.590s	136.228us	5	5	100.00
		hmac_same_csr_outstanding	1.430s	69.744us	20	20	100.00
V2	tl_d_partial_access	hmac_csr_hw_reset	0.660s	66.895us	5	5	100.00
		hmac_csr_rw	0.750s	333.176us	20	20	100.00
		hmac_csr_aliasing	2.590s	136.228us	5	5	100.00
		hmac_same_csr_outstanding	1.430s	69.744us	20	20	100.00
V2		TOTAL			584	590	98.98
V2S	tl_intg_err	hmac_sec_cm	0.960s	111.656us	5	5	100.00
		hmac_tl_intg_err	2.510s	179.004us	20	20	100.00
V2S	sec_cm_bus_integrity	hmac_tl_intg_err	2.510s	179.004us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	write_config_and_secret_key_during_msg_wr	hmac_smoke	4.380s	1.654ms	50	50	100.00
V3	stress_all_with_rand_reset	hmac_stress_all_with_rand_reset	1.535h	144.233ms	189	200	94.50
V3		TOTAL			189	200	94.50
		TOTAL			903	920	98.15

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	13	13	11	84.62
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.57	99.54	98.47	100.00	100.00	99.76	99.49	99.72

Failure Buckets

UVM_ERROR (hmac_base_vseq.sv:37) [hmac_stress_all_vseq] Check failed cfg.hmac_vif.is_idle() == *'b* (* [*] vs * [*]) has 6 failures:

Test hmac_stress_all_with_rand_reset has 6 failures.

0.hmac_stress_all_with_rand_reset.2208847911
Line 257, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/0.hmac_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 3523775770 ps: (hmac_base_vseq.sv:37) [uvm_test_top.env.virtual_sequencer.hmac_stress_all_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 3523775770 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

90.hmac_stress_all_with_rand_reset.838573896
Line 374, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/90.hmac_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 38560745484 ps: (hmac_base_vseq.sv:37) [uvm_test_top.env.virtual_sequencer.hmac_stress_all_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 38560745484 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 6 failures:

Test hmac_test_sha_vectors has 4 failures.

1.hmac_test_sha_vectors.3892934996
Line 215, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/1.hmac_test_sha_vectors/latest/run.log

  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

5.hmac_test_sha_vectors.2183951772
Line 215, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/5.hmac_test_sha_vectors/latest/run.log

  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

Test hmac_error has 2 failures.

17.hmac_error.3816821037
Line 258, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/17.hmac_error/latest/run.log

  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

39.hmac_error.3802410647
Line 263, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/39.hmac_error/latest/run.log

  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (hmac_base_vseq.sv:37) [hmac_common_vseq] Check failed cfg.hmac_vif.is_idle() == *'b* (* [*] vs * [*]) has 2 failures:

Test hmac_stress_all_with_rand_reset has 2 failures.

1.hmac_stress_all_with_rand_reset.4111762251
Line 891, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/1.hmac_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 190257741799 ps: (hmac_base_vseq.sv:37) [uvm_test_top.env.virtual_sequencer.hmac_common_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 190257741799 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

145.hmac_stress_all_with_rand_reset.4266674434
Line 1599, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/145.hmac_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 45972564955 ps: (hmac_base_vseq.sv:37) [uvm_test_top.env.virtual_sequencer.hmac_common_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 45972564955 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (hmac_base_vseq.sv:37) [hmac_datapath_stress_vseq] Check failed cfg.hmac_vif.is_idle() == *'b* (* [*] vs * [*]) has 1 failures:
- Test hmac_stress_all_with_rand_reset has 1 failures.
  - 47.hmac_stress_all_with_rand_reset.3688531529
    Line 1163, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/47.hmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1392412822210 ps: (hmac_base_vseq.sv:37) [uvm_test_top.env.virtual_sequencer.hmac_datapath_stress_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 1392412822210 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (hmac_base_vseq.sv:37) [hmac_smoke_vseq] Check failed cfg.hmac_vif.is_idle() == *'b* (* [*] vs * [*]) has 1 failures:
- Test hmac_stress_all_with_rand_reset has 1 failures.
  - 146.hmac_stress_all_with_rand_reset.2738619240
    Line 732, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/146.hmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 147562105735 ps: (hmac_base_vseq.sv:37) [uvm_test_top.env.virtual_sequencer.hmac_smoke_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 147562105735 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (hmac_base_vseq.sv:37) [hmac_back_pressure_vseq] Check failed cfg.hmac_vif.is_idle() == *'b* (* [*] vs * [*]) has 1 failures:
- Test hmac_stress_all_with_rand_reset has 1 failures.
  - 168.hmac_stress_all_with_rand_reset.3508262657
    Line 1004, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/168.hmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 48442138254 ps: (hmac_base_vseq.sv:37) [uvm_test_top.env.virtual_sequencer.hmac_back_pressure_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 48442138254 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```