HMAC Simulation Results

Friday July 26 2024 23:02:17 UTC

GitHub Revision: 4877b481e8

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 32772136499307530671572864311472020383177374948143841887013058662761887638244

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke hmac_smoke 16.130s 5.661ms 50 50 100.00
V1 csr_hw_reset hmac_csr_hw_reset 1.040s 129.036us 5 5 100.00
V1 csr_rw hmac_csr_rw 0.970s 59.578us 20 20 100.00
V1 csr_bit_bash hmac_csr_bit_bash 15.830s 1.098ms 5 5 100.00
V1 csr_aliasing hmac_csr_aliasing 6.180s 1.243ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset hmac_csr_mem_rw_with_rand_reset 19.130m 78.816ms 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr hmac_csr_rw 0.970s 59.578us 20 20 100.00
hmac_csr_aliasing 6.180s 1.243ms 5 5 100.00
V1 TOTAL 105 105 100.00
V2 long_msg hmac_long_msg 3.207m 43.481ms 50 50 100.00
V2 back_pressure hmac_back_pressure 1.776m 1.835ms 50 50 100.00
V2 test_vectors hmac_test_sha256_vectors 11.143m 267.982ms 5 5 100.00
hmac_test_sha384_vectors 44.729m 835.225ms 5 5 100.00
hmac_test_sha512_vectors 38.979m 170.603ms 5 5 100.00
hmac_test_hmac256_vectors 1.448m 52.738ms 5 5 100.00
hmac_test_hmac384_vectors 1.912m 9.750ms 5 5 100.00
hmac_test_hmac512_vectors 2.058m 127.592ms 5 5 100.00
V2 burst_wr hmac_burst_wr 1.262m 20.233ms 50 50 100.00
V2 datapath_stress hmac_datapath_stress 26.811m 29.435ms 50 50 100.00
V2 error hmac_error 4.635m 18.278ms 50 50 100.00
V2 wipe_secret hmac_wipe_secret 2.451m 5.473ms 50 50 100.00
V2 save_and_restore hmac_smoke 16.130s 5.661ms 50 50 100.00
hmac_long_msg 3.207m 43.481ms 50 50 100.00
hmac_back_pressure 1.776m 1.835ms 50 50 100.00
hmac_datapath_stress 26.811m 29.435ms 50 50 100.00
hmac_burst_wr 1.262m 20.233ms 50 50 100.00
hmac_stress_all 1.472h 1.961s 50 50 100.00
V2 fifo_empty_status_interrupt hmac_smoke 16.130s 5.661ms 50 50 100.00
hmac_long_msg 3.207m 43.481ms 50 50 100.00
hmac_back_pressure 1.776m 1.835ms 50 50 100.00
hmac_datapath_stress 26.811m 29.435ms 50 50 100.00
hmac_wipe_secret 2.451m 5.473ms 50 50 100.00
hmac_test_sha256_vectors 11.143m 267.982ms 5 5 100.00
hmac_test_sha384_vectors 44.729m 835.225ms 5 5 100.00
hmac_test_sha512_vectors 38.979m 170.603ms 5 5 100.00
hmac_test_hmac256_vectors 1.448m 52.738ms 5 5 100.00
hmac_test_hmac384_vectors 1.912m 9.750ms 5 5 100.00
hmac_test_hmac512_vectors 2.058m 127.592ms 5 5 100.00
V2 wide_digest_configurable_key_length hmac_smoke 16.130s 5.661ms 50 50 100.00
hmac_long_msg 3.207m 43.481ms 50 50 100.00
hmac_back_pressure 1.776m 1.835ms 50 50 100.00
hmac_datapath_stress 26.811m 29.435ms 50 50 100.00
hmac_burst_wr 1.262m 20.233ms 50 50 100.00
hmac_error 4.635m 18.278ms 50 50 100.00
hmac_wipe_secret 2.451m 5.473ms 50 50 100.00
hmac_test_sha256_vectors 11.143m 267.982ms 5 5 100.00
hmac_test_sha384_vectors 44.729m 835.225ms 5 5 100.00
hmac_test_sha512_vectors 38.979m 170.603ms 5 5 100.00
hmac_test_hmac256_vectors 1.448m 52.738ms 5 5 100.00
hmac_test_hmac384_vectors 1.912m 9.750ms 5 5 100.00
hmac_test_hmac512_vectors 2.058m 127.592ms 5 5 100.00
hmac_stress_all 1.472h 1.961s 50 50 100.00
V2 stress_all hmac_stress_all 1.472h 1.961s 50 50 100.00
V2 alert_test hmac_alert_test 0.630s 15.207us 50 50 100.00
V2 intr_test hmac_intr_test 0.660s 19.452us 50 50 100.00
V2 tl_d_oob_addr_access hmac_tl_errors 4.360s 253.359us 20 20 100.00
V2 tl_d_illegal_access hmac_tl_errors 4.360s 253.359us 20 20 100.00
V2 tl_d_outstanding_access hmac_csr_hw_reset 1.040s 129.036us 5 5 100.00
hmac_csr_rw 0.970s 59.578us 20 20 100.00
hmac_csr_aliasing 6.180s 1.243ms 5 5 100.00
hmac_same_csr_outstanding 2.320s 119.515us 20 20 100.00
V2 tl_d_partial_access hmac_csr_hw_reset 1.040s 129.036us 5 5 100.00
hmac_csr_rw 0.970s 59.578us 20 20 100.00
hmac_csr_aliasing 6.180s 1.243ms 5 5 100.00
hmac_same_csr_outstanding 2.320s 119.515us 20 20 100.00
V2 TOTAL 520 520 100.00
V2S tl_intg_err hmac_sec_cm 1.190s 1.791ms 5 5 100.00
hmac_tl_intg_err 4.400s 2.410ms 20 20 100.00
V2S sec_cm_bus_integrity hmac_tl_intg_err 4.400s 2.410ms 20 20 100.00
V2S TOTAL 25 25 100.00
V3 write_config_and_secret_key_during_msg_wr hmac_smoke 16.130s 5.661ms 50 50 100.00
V3 stress_all_with_rand_reset hmac_stress_all_with_rand_reset 2.684h 1.141s 10 10 100.00
V3 TOTAL 10 10 100.00
TOTAL 660 660 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 17 17 17 100.00
V2S 2 2 2 100.00
V3 1 1 1 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.62 95.40 97.22 100.00 94.12 98.27 98.48 99.85

Past Results