HMAC Simulation Results

Saturday February 08 2025 05:05:54 UTC

GitHub Revision: 9f20940d49

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 88344288495849993302635329522992994622996067932062874150778031027723701018040

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	hmac_smoke	23.480s	2.633ms	50	50	100.00
V1	csr_hw_reset	hmac_csr_hw_reset	1.440s	332.939us	5	5	100.00
V1	csr_rw	hmac_csr_rw	1.460s	28.843us	20	20	100.00
V1	csr_bit_bash	hmac_csr_bit_bash	22.910s	2.203ms	5	5	100.00
V1	csr_aliasing	hmac_csr_aliasing	12.800s	470.061us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	hmac_csr_mem_rw_with_rand_reset	9.583m	101.732ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	hmac_csr_rw	1.460s	28.843us	20	20	100.00
		hmac_csr_aliasing	12.800s	470.061us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	long_msg	hmac_long_msg	4.375m	11.352ms	50	50	100.00
V2	back_pressure	hmac_back_pressure	2.249m	1.564ms	50	50	100.00
V2	test_vectors	hmac_test_sha256_vectors	12.512m	225.758ms	5	5	100.00
		hmac_test_sha384_vectors	46.183m	292.057ms	5	5	100.00
		hmac_test_sha512_vectors	50.183m	223.227ms	5	5	100.00
		hmac_test_hmac256_vectors	1.710m	7.135ms	5	5	100.00
		hmac_test_hmac384_vectors	2.211m	13.077ms	5	5	100.00
		hmac_test_hmac512_vectors	2.258m	9.833ms	5	5	100.00
V2	burst_wr	hmac_burst_wr	1.487m	1.928ms	50	50	100.00
V2	datapath_stress	hmac_datapath_stress	30.669m	8.492ms	50	50	100.00
V2	error	hmac_error	4.667m	71.665ms	50	50	100.00
V2	wipe_secret	hmac_wipe_secret	2.835m	51.183ms	50	50	100.00
V2	save_and_restore	hmac_smoke	23.480s	2.633ms	50	50	100.00
		hmac_long_msg	4.375m	11.352ms	50	50	100.00
		hmac_back_pressure	2.249m	1.564ms	50	50	100.00
		hmac_datapath_stress	30.669m	8.492ms	50	50	100.00
		hmac_burst_wr	1.487m	1.928ms	50	50	100.00
		hmac_stress_all	1.564h	115.597ms	50	50	100.00
V2	fifo_empty_status_interrupt	hmac_smoke	23.480s	2.633ms	50	50	100.00
		hmac_long_msg	4.375m	11.352ms	50	50	100.00
		hmac_back_pressure	2.249m	1.564ms	50	50	100.00
		hmac_datapath_stress	30.669m	8.492ms	50	50	100.00
		hmac_wipe_secret	2.835m	51.183ms	50	50	100.00
		hmac_test_sha256_vectors	12.512m	225.758ms	5	5	100.00
		hmac_test_sha384_vectors	46.183m	292.057ms	5	5	100.00
		hmac_test_sha512_vectors	50.183m	223.227ms	5	5	100.00
		hmac_test_hmac256_vectors	1.710m	7.135ms	5	5	100.00
		hmac_test_hmac384_vectors	2.211m	13.077ms	5	5	100.00
		hmac_test_hmac512_vectors	2.258m	9.833ms	5	5	100.00
V2	wide_digest_configurable_key_length	hmac_smoke	23.480s	2.633ms	50	50	100.00
		hmac_long_msg	4.375m	11.352ms	50	50	100.00
		hmac_back_pressure	2.249m	1.564ms	50	50	100.00
		hmac_datapath_stress	30.669m	8.492ms	50	50	100.00
		hmac_burst_wr	1.487m	1.928ms	50	50	100.00
		hmac_error	4.667m	71.665ms	50	50	100.00
		hmac_wipe_secret	2.835m	51.183ms	50	50	100.00
		hmac_test_sha256_vectors	12.512m	225.758ms	5	5	100.00
		hmac_test_sha384_vectors	46.183m	292.057ms	5	5	100.00
		hmac_test_sha512_vectors	50.183m	223.227ms	5	5	100.00
		hmac_test_hmac256_vectors	1.710m	7.135ms	5	5	100.00
		hmac_test_hmac384_vectors	2.211m	13.077ms	5	5	100.00
		hmac_test_hmac512_vectors	2.258m	9.833ms	5	5	100.00
		hmac_stress_all	1.564h	115.597ms	50	50	100.00
V2	stress_all	hmac_stress_all	1.564h	115.597ms	50	50	100.00
V2	alert_test	hmac_alert_test	0.940s	15.445us	50	50	100.00
V2	intr_test	hmac_intr_test	0.960s	60.304us	50	50	100.00
V2	tl_d_oob_addr_access	hmac_tl_errors	5.740s	161.956us	20	20	100.00
V2	tl_d_illegal_access	hmac_tl_errors	5.740s	161.956us	20	20	100.00
V2	tl_d_outstanding_access	hmac_csr_hw_reset	1.440s	332.939us	5	5	100.00
		hmac_csr_rw	1.460s	28.843us	20	20	100.00
		hmac_csr_aliasing	12.800s	470.061us	5	5	100.00
		hmac_same_csr_outstanding	3.570s	148.982us	20	20	100.00
V2	tl_d_partial_access	hmac_csr_hw_reset	1.440s	332.939us	5	5	100.00
		hmac_csr_rw	1.460s	28.843us	20	20	100.00
		hmac_csr_aliasing	12.800s	470.061us	5	5	100.00
		hmac_same_csr_outstanding	3.570s	148.982us	20	20	100.00
V2		TOTAL			520	520	100.00
V2S	tl_intg_err	hmac_sec_cm	1.630s	82.772us	5	5	100.00
		hmac_tl_intg_err	6.350s	920.817us	20	20	100.00
V2S	sec_cm_bus_integrity	hmac_tl_intg_err	6.350s	920.817us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	write_config_and_secret_key_during_msg_wr	hmac_smoke	23.480s	2.633ms	50	50	100.00
V3	stress_all_with_rand_reset	hmac_stress_all_with_rand_reset	2.364h	496.960ms	10	10	100.00
V3		TOTAL			10	10	100.00
		TOTAL			660	660	100.00

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	17	17	17	100.00
V2S	2	2	2	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.03	95.40	97.17	100.00	97.06	98.27	98.48	99.85

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