HMAC Simulation Results

Monday October 14 2024 17:26:15 UTC

GitHub Revision: `12e3b8572e`

Branch: os_regression_2024_10_14

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 85025606402499621082521464627961092918263397067038954055071960501195381950243

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	hmac_smoke	22.280s	1.225ms	50	50	100.00
V1	csr_hw_reset	hmac_csr_hw_reset	1.430s	33.814us	5	5	100.00
V1	csr_rw	hmac_csr_rw	1.380s	542.958us	20	20	100.00
V1	csr_bit_bash	hmac_csr_bit_bash	19.900s	1.282ms	5	5	100.00
V1	csr_aliasing	hmac_csr_aliasing	11.760s	580.610us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	hmac_csr_mem_rw_with_rand_reset	16.523m	64.439ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	hmac_csr_rw	1.380s	542.958us	20	20	100.00
		hmac_csr_aliasing	11.760s	580.610us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	long_msg	hmac_long_msg	4.692m	33.440ms	50	50	100.00
V2	back_pressure	hmac_back_pressure	2.066m	6.966ms	50	50	100.00
V2	test_vectors	hmac_test_sha256_vectors	11.279m	107.412ms	5	5	100.00
		hmac_test_sha384_vectors	49.374m	207.114ms	5	5	100.00
		hmac_test_sha512_vectors	40.433m	269.249ms	5	5	100.00
		hmac_test_hmac256_vectors	49.130s	3.102ms	5	5	100.00
		hmac_test_hmac384_vectors	2.161m	19.240ms	5	5	100.00
		hmac_test_hmac512_vectors	2.742m	21.799ms	5	5	100.00
V2	burst_wr	hmac_burst_wr	1.545m	3.852ms	49	50	98.00
V2	datapath_stress	hmac_datapath_stress	26.269m	7.695ms	50	50	100.00
V2	error	hmac_error	5.071m	37.064ms	50	50	100.00
V2	wipe_secret	hmac_wipe_secret	2.392m	7.596ms	50	50	100.00
V2	save_and_restore	hmac_smoke	22.280s	1.225ms	50	50	100.00
		hmac_long_msg	4.692m	33.440ms	50	50	100.00
		hmac_back_pressure	2.066m	6.966ms	50	50	100.00
		hmac_datapath_stress	26.269m	7.695ms	50	50	100.00
		hmac_burst_wr	1.545m	3.852ms	49	50	98.00
		hmac_stress_all	1.159h	118.914ms	49	50	98.00
V2	fifo_empty_status_interrupt	hmac_smoke	22.280s	1.225ms	50	50	100.00
		hmac_long_msg	4.692m	33.440ms	50	50	100.00
		hmac_back_pressure	2.066m	6.966ms	50	50	100.00
		hmac_datapath_stress	26.269m	7.695ms	50	50	100.00
		hmac_wipe_secret	2.392m	7.596ms	50	50	100.00
		hmac_test_sha256_vectors	11.279m	107.412ms	5	5	100.00
		hmac_test_sha384_vectors	49.374m	207.114ms	5	5	100.00
		hmac_test_sha512_vectors	40.433m	269.249ms	5	5	100.00
		hmac_test_hmac256_vectors	49.130s	3.102ms	5	5	100.00
		hmac_test_hmac384_vectors	2.161m	19.240ms	5	5	100.00
		hmac_test_hmac512_vectors	2.742m	21.799ms	5	5	100.00
V2	wide_digest_configurable_key_length	hmac_smoke	22.280s	1.225ms	50	50	100.00
		hmac_long_msg	4.692m	33.440ms	50	50	100.00
		hmac_back_pressure	2.066m	6.966ms	50	50	100.00
		hmac_datapath_stress	26.269m	7.695ms	50	50	100.00
		hmac_burst_wr	1.545m	3.852ms	49	50	98.00
		hmac_error	5.071m	37.064ms	50	50	100.00
		hmac_wipe_secret	2.392m	7.596ms	50	50	100.00
		hmac_test_sha256_vectors	11.279m	107.412ms	5	5	100.00
		hmac_test_sha384_vectors	49.374m	207.114ms	5	5	100.00
		hmac_test_sha512_vectors	40.433m	269.249ms	5	5	100.00
		hmac_test_hmac256_vectors	49.130s	3.102ms	5	5	100.00
		hmac_test_hmac384_vectors	2.161m	19.240ms	5	5	100.00
		hmac_test_hmac512_vectors	2.742m	21.799ms	5	5	100.00
		hmac_stress_all	1.159h	118.914ms	49	50	98.00
V2	stress_all	hmac_stress_all	1.159h	118.914ms	49	50	98.00
V2	alert_test	hmac_alert_test	0.940s	14.822us	50	50	100.00
V2	intr_test	hmac_intr_test	0.960s	18.775us	50	50	100.00
V2	tl_d_oob_addr_access	hmac_tl_errors	6.250s	200.600us	20	20	100.00
V2	tl_d_illegal_access	hmac_tl_errors	6.250s	200.600us	20	20	100.00
V2	tl_d_outstanding_access	hmac_csr_hw_reset	1.430s	33.814us	5	5	100.00
		hmac_csr_rw	1.380s	542.958us	20	20	100.00
		hmac_csr_aliasing	11.760s	580.610us	5	5	100.00
		hmac_same_csr_outstanding	3.420s	425.516us	20	20	100.00
V2	tl_d_partial_access	hmac_csr_hw_reset	1.430s	33.814us	5	5	100.00
		hmac_csr_rw	1.380s	542.958us	20	20	100.00
		hmac_csr_aliasing	11.760s	580.610us	5	5	100.00
		hmac_same_csr_outstanding	3.420s	425.516us	20	20	100.00
V2		TOTAL			518	520	99.62
V2S	tl_intg_err	hmac_sec_cm	1.580s	379.064us	5	5	100.00
		hmac_tl_intg_err	6.360s	4.858ms	20	20	100.00
V2S	sec_cm_bus_integrity	hmac_tl_intg_err	6.360s	4.858ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	write_config_and_secret_key_during_msg_wr	hmac_smoke	22.280s	1.225ms	50	50	100.00
V3	stress_all_with_rand_reset	hmac_stress_all_with_rand_reset	6.363m	5.062ms	7	10	70.00
V3		TOTAL			7	10	70.00
		TOTAL			655	660	99.24

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	17	17	15	88.24
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.62	95.37	97.22	100.00	94.12	98.25	98.52	99.85

Failure Buckets

UVM_ERROR (hmac_scoreboard.sv:481) [scoreboard] Check failed item.d_data ==gmv(csr) (* [] vs * []) intr_state` has 2 failures:
- Test hmac_burst_wr has 1 failures.
  - 21.hmac_burst_wr.74181940452590687761107329193257616404138257073437123391880456582507819169030
    Line 556, in log /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/21.hmac_burst_wr/latest/run.log
```
  UVM_ERROR @ 458974564 ps: (hmac_scoreboard.sv:481) [uvm_test_top.env.scoreboard] Check failed item.d_data == `gmv(csr) (0 [0x0] vs 2 [0x2]) intr_state
  UVM_INFO @ 458974564 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test hmac_stress_all has 1 failures.
  - 29.hmac_stress_all.71650165180114369993311676590466963693439746705566334515562625718917725662145
    Line 131503, in log /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/29.hmac_stress_all/latest/run.log
```
  UVM_ERROR @ 10812660535 ps: (hmac_scoreboard.sv:481) [uvm_test_top.env.scoreboard] Check failed item.d_data == `gmv(csr) (0 [0x0] vs 2 [0x2]) intr_state
  UVM_INFO @ 10812660535 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:771) [hmac_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
- Test hmac_stress_all_with_rand_reset has 1 failures.
  - 0.hmac_stress_all_with_rand_reset.97142783253625661138157852461724184095206685364572973693449786967779994310432
    Line 13510, in log /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/0.hmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 13968159984 ps: (cip_base_vseq.sv:771) [uvm_test_top.env.virtual_sequencer.hmac_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 13968159984 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (hmac_base_vseq.sv:80) [hmac_datapath_stress_vseq] Check failed cfg.hmac_vif.is_idle() == *'b* (* [*] vs * [*]) has 1 failures:
- Test hmac_stress_all_with_rand_reset has 1 failures.
  - 1.hmac_stress_all_with_rand_reset.77023439716608756689838038908056513199877050070249873706380632836095021628571
    Line 11219, in log /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/1.hmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 9270267507 ps: (hmac_base_vseq.sv:80) [uvm_test_top.env.virtual_sequencer.hmac_datapath_stress_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 9270267507 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (hmac_base_vseq.sv:80) [hmac_smoke_vseq] Check failed cfg.hmac_vif.is_idle() == *'b* (* [*] vs * [*]) has 1 failures:
- Test hmac_stress_all_with_rand_reset has 1 failures.
  - 6.hmac_stress_all_with_rand_reset.52385920544143835347106021153151588867311338471575518493672832601573078428547
    Line 69, in log /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/6.hmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @   7624845 ps: (hmac_base_vseq.sv:80) [uvm_test_top.env.virtual_sequencer.hmac_smoke_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @   7624845 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

HMAC Simulation Results

Monday October 14 2024 17:26:15 UTC

GitHub Revision: 12e3b8572e

Branch: os_regression_2024_10_14

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 85025606402499621082521464627961092918263397067038954055071960501195381950243

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `12e3b8572e`