b938dde05c| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | hmac_smoke | 7.380s | 2.432ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | hmac_csr_hw_reset | 1.020s | 41.879us | 5 | 5 | 100.00 |
| V1 | csr_rw | hmac_csr_rw | 1.110s | 34.672us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | hmac_csr_bit_bash | 18.240s | 1.100ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | hmac_csr_aliasing | 8.570s | 306.665us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | hmac_csr_mem_rw_with_rand_reset | 13.549m | 80.572ms | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | hmac_csr_rw | 1.110s | 34.672us | 20 | 20 | 100.00 |
| hmac_csr_aliasing | 8.570s | 306.665us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 105 | 105 | 100.00 | |||
| V2 | long_msg | hmac_long_msg | 2.466m | 10.365ms | 50 | 50 | 100.00 |
| V2 | back_pressure | hmac_back_pressure | 1.117m | 1.697ms | 50 | 50 | 100.00 |
| V2 | test_vectors | hmac_test_sha_vectors | 9.165m | 43.457ms | 50 | 50 | 100.00 |
| hmac_test_hmac_vectors | 1.420s | 109.058us | 50 | 50 | 100.00 | ||
| V2 | burst_wr | hmac_burst_wr | 1.010m | 7.495ms | 50 | 50 | 100.00 |
| V2 | datapath_stress | hmac_datapath_stress | 3.041m | 6.846ms | 50 | 50 | 100.00 |
| V2 | error | hmac_error | 3.669m | 100.812ms | 50 | 50 | 100.00 |
| V2 | wipe_secret | hmac_wipe_secret | 1.575m | 1.833ms | 50 | 50 | 100.00 |
| V2 | save_and_restore | save_and_restore | 0 | 0 | -- | ||
| V2 | fifo_empty_status_interrupt | fifo_empty_status_interrupt | 0 | 0 | -- | ||
| V2 | wide_digest_configurable_key_length | wide_digest_configurable_key_length | 0 | 0 | -- | ||
| V2 | stress_all | hmac_stress_all | 47.972m | 231.658ms | 50 | 50 | 100.00 |
| V2 | alert_test | hmac_alert_test | 0.680s | 36.659us | 50 | 50 | 100.00 |
| V2 | intr_test | hmac_intr_test | 0.790s | 39.438us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | hmac_tl_errors | 3.990s | 405.008us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | hmac_tl_errors | 3.990s | 405.008us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | hmac_csr_hw_reset | 1.020s | 41.879us | 5 | 5 | 100.00 |
| hmac_csr_rw | 1.110s | 34.672us | 20 | 20 | 100.00 | ||
| hmac_csr_aliasing | 8.570s | 306.665us | 5 | 5 | 100.00 | ||
| hmac_same_csr_outstanding | 2.660s | 119.941us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | hmac_csr_hw_reset | 1.020s | 41.879us | 5 | 5 | 100.00 |
| hmac_csr_rw | 1.110s | 34.672us | 20 | 20 | 100.00 | ||
| hmac_csr_aliasing | 8.570s | 306.665us | 5 | 5 | 100.00 | ||
| hmac_same_csr_outstanding | 2.660s | 119.941us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 590 | 590 | 100.00 | |||
| V2S | tl_intg_err | hmac_sec_cm | 0.940s | 193.372us | 5 | 5 | 100.00 |
| hmac_tl_intg_err | 4.380s | 1.274ms | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | hmac_tl_intg_err | 4.380s | 1.274ms | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | write_config_and_secret_key_during_msg_wr | hmac_smoke | 7.380s | 2.432ms | 50 | 50 | 100.00 |
| V3 | stress_all_with_rand_reset | hmac_stress_all_with_rand_reset | 1.576h | 118.786ms | 12 | 200 | 6.00 |
| V3 | TOTAL | 12 | 200 | 6.00 | |||
| TOTAL | 732 | 920 | 79.57 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 6 | 100.00 |
| V2 | 16 | 13 | 13 | 81.25 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 86.94 | 92.47 | 85.22 | 100.00 | 76.32 | 85.98 | 99.49 | 69.08 |
UVM_ERROR (cip_base_vseq.sv:829) [hmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 188 failures:
1.hmac_stress_all_with_rand_reset.50495052295564478260603450644306359100422740396727940992812457489958412624754
Line 44585, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/1.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 21314160439 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.hmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 21314160439 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.hmac_stress_all_with_rand_reset.30420862341774067344540403889639442388784746771408856271147540254235956322549
Line 50199, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/2.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 32264790892 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.hmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 32264790892 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 186 more failures.