HMAC Simulation Results

Tuesday May 30 2023 07:03:17 UTC

GitHub Revision: f8b3c19a2

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 1284268927

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke hmac_smoke 4.760s 729.248us 50 50 100.00
V1 csr_hw_reset hmac_csr_hw_reset 0.690s 37.853us 5 5 100.00
V1 csr_rw hmac_csr_rw 0.770s 80.555us 20 20 100.00
V1 csr_bit_bash hmac_csr_bit_bash 9.290s 2.016ms 5 5 100.00
V1 csr_aliasing hmac_csr_aliasing 2.410s 50.110us 5 5 100.00
V1 csr_mem_rw_with_rand_reset hmac_csr_mem_rw_with_rand_reset 11.525m 106.099ms 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr hmac_csr_rw 0.770s 80.555us 20 20 100.00
hmac_csr_aliasing 2.410s 50.110us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 long_msg hmac_long_msg 2.227m 10.699ms 50 50 100.00
V2 back_pressure hmac_back_pressure 54.840s 7.503ms 50 50 100.00
V2 test_vectors hmac_test_sha_vectors 8.600m 96.524ms 47 50 94.00
hmac_test_hmac_vectors 1.270s 286.027us 50 50 100.00
V2 burst_wr hmac_burst_wr 1.259m 1.725ms 50 50 100.00
V2 datapath_stress hmac_datapath_stress 2.691m 3.124ms 50 50 100.00
V2 error hmac_error 3.779m 34.675ms 50 50 100.00
V2 wipe_secret hmac_wipe_secret 1.446m 42.170ms 50 50 100.00
V2 stress_all hmac_stress_all 48.787m 1.319s 50 50 100.00
V2 alert_test hmac_alert_test 0.630s 42.974us 50 50 100.00
V2 intr_test hmac_intr_test 0.670s 16.645us 50 50 100.00
V2 tl_d_oob_addr_access hmac_tl_errors 3.330s 251.789us 20 20 100.00
V2 tl_d_illegal_access hmac_tl_errors 3.330s 251.789us 20 20 100.00
V2 tl_d_outstanding_access hmac_csr_hw_reset 0.690s 37.853us 5 5 100.00
hmac_csr_rw 0.770s 80.555us 20 20 100.00
hmac_csr_aliasing 2.410s 50.110us 5 5 100.00
hmac_same_csr_outstanding 1.480s 190.083us 20 20 100.00
V2 tl_d_partial_access hmac_csr_hw_reset 0.690s 37.853us 5 5 100.00
hmac_csr_rw 0.770s 80.555us 20 20 100.00
hmac_csr_aliasing 2.410s 50.110us 5 5 100.00
hmac_same_csr_outstanding 1.480s 190.083us 20 20 100.00
V2 TOTAL 587 590 99.49
V2S tl_intg_err hmac_sec_cm 0.950s 378.840us 5 5 100.00
hmac_tl_intg_err 2.460s 144.672us 20 20 100.00
V2S sec_cm_bus_integrity hmac_tl_intg_err 2.460s 144.672us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 write_config_and_secret_key_during_msg_wr hmac_smoke 4.760s 729.248us 50 50 100.00
V3 stress_all_with_rand_reset hmac_stress_all_with_rand_reset 1.792h 159.218ms 191 200 95.50
V3 TOTAL 191 200 95.50
TOTAL 908 920 98.70

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 13 13 12 92.31
V2S 2 2 2 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
99.67 99.54 98.91 100.00 100.00 99.76 99.49 100.00

Failure Buckets

Past Results