f8b3c19a2
Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
---|---|---|---|---|---|---|---|
V1 | smoke | hmac_smoke | 4.760s | 729.248us | 50 | 50 | 100.00 |
V1 | csr_hw_reset | hmac_csr_hw_reset | 0.690s | 37.853us | 5 | 5 | 100.00 |
V1 | csr_rw | hmac_csr_rw | 0.770s | 80.555us | 20 | 20 | 100.00 |
V1 | csr_bit_bash | hmac_csr_bit_bash | 9.290s | 2.016ms | 5 | 5 | 100.00 |
V1 | csr_aliasing | hmac_csr_aliasing | 2.410s | 50.110us | 5 | 5 | 100.00 |
V1 | csr_mem_rw_with_rand_reset | hmac_csr_mem_rw_with_rand_reset | 11.525m | 106.099ms | 20 | 20 | 100.00 |
V1 | regwen_csr_and_corresponding_lockable_csr | hmac_csr_rw | 0.770s | 80.555us | 20 | 20 | 100.00 |
hmac_csr_aliasing | 2.410s | 50.110us | 5 | 5 | 100.00 | ||
V1 | TOTAL | 105 | 105 | 100.00 | |||
V2 | long_msg | hmac_long_msg | 2.227m | 10.699ms | 50 | 50 | 100.00 |
V2 | back_pressure | hmac_back_pressure | 54.840s | 7.503ms | 50 | 50 | 100.00 |
V2 | test_vectors | hmac_test_sha_vectors | 8.600m | 96.524ms | 47 | 50 | 94.00 |
hmac_test_hmac_vectors | 1.270s | 286.027us | 50 | 50 | 100.00 | ||
V2 | burst_wr | hmac_burst_wr | 1.259m | 1.725ms | 50 | 50 | 100.00 |
V2 | datapath_stress | hmac_datapath_stress | 2.691m | 3.124ms | 50 | 50 | 100.00 |
V2 | error | hmac_error | 3.779m | 34.675ms | 50 | 50 | 100.00 |
V2 | wipe_secret | hmac_wipe_secret | 1.446m | 42.170ms | 50 | 50 | 100.00 |
V2 | stress_all | hmac_stress_all | 48.787m | 1.319s | 50 | 50 | 100.00 |
V2 | alert_test | hmac_alert_test | 0.630s | 42.974us | 50 | 50 | 100.00 |
V2 | intr_test | hmac_intr_test | 0.670s | 16.645us | 50 | 50 | 100.00 |
V2 | tl_d_oob_addr_access | hmac_tl_errors | 3.330s | 251.789us | 20 | 20 | 100.00 |
V2 | tl_d_illegal_access | hmac_tl_errors | 3.330s | 251.789us | 20 | 20 | 100.00 |
V2 | tl_d_outstanding_access | hmac_csr_hw_reset | 0.690s | 37.853us | 5 | 5 | 100.00 |
hmac_csr_rw | 0.770s | 80.555us | 20 | 20 | 100.00 | ||
hmac_csr_aliasing | 2.410s | 50.110us | 5 | 5 | 100.00 | ||
hmac_same_csr_outstanding | 1.480s | 190.083us | 20 | 20 | 100.00 | ||
V2 | tl_d_partial_access | hmac_csr_hw_reset | 0.690s | 37.853us | 5 | 5 | 100.00 |
hmac_csr_rw | 0.770s | 80.555us | 20 | 20 | 100.00 | ||
hmac_csr_aliasing | 2.410s | 50.110us | 5 | 5 | 100.00 | ||
hmac_same_csr_outstanding | 1.480s | 190.083us | 20 | 20 | 100.00 | ||
V2 | TOTAL | 587 | 590 | 99.49 | |||
V2S | tl_intg_err | hmac_sec_cm | 0.950s | 378.840us | 5 | 5 | 100.00 |
hmac_tl_intg_err | 2.460s | 144.672us | 20 | 20 | 100.00 | ||
V2S | sec_cm_bus_integrity | hmac_tl_intg_err | 2.460s | 144.672us | 20 | 20 | 100.00 |
V2S | TOTAL | 25 | 25 | 100.00 | |||
V3 | write_config_and_secret_key_during_msg_wr | hmac_smoke | 4.760s | 729.248us | 50 | 50 | 100.00 |
V3 | stress_all_with_rand_reset | hmac_stress_all_with_rand_reset | 1.792h | 159.218ms | 191 | 200 | 95.50 |
V3 | TOTAL | 191 | 200 | 95.50 | |||
TOTAL | 908 | 920 | 98.70 |
Items | Total | Written | Passing | Progress |
---|---|---|---|---|
V1 | 6 | 6 | 6 | 100.00 |
V2 | 13 | 13 | 12 | 92.31 |
V2S | 2 | 2 | 2 | 100.00 |
V3 | 1 | 1 | 0 | 0.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
---|---|---|---|---|---|---|---|
99.67 | 99.54 | 98.91 | 100.00 | 100.00 | 99.76 | 99.49 | 100.00 |
UVM_ERROR (hmac_base_vseq.sv:37) [hmac_stress_all_vseq] Check failed cfg.hmac_vif.is_idle() == *'b* (* [*] vs * [*])
has 7 failures:
25.hmac_stress_all_with_rand_reset.3189840419
Line 674, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/25.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 31167415031 ps: (hmac_base_vseq.sv:37) [uvm_test_top.env.virtual_sequencer.hmac_stress_all_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 31167415031 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
76.hmac_stress_all_with_rand_reset.2342648533
Line 1123, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/76.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 82338990180 ps: (hmac_base_vseq.sv:37) [uvm_test_top.env.virtual_sequencer.hmac_stress_all_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 82338990180 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 5 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
has 3 failures:
7.hmac_test_sha_vectors.60945588
Line 215, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/7.hmac_test_sha_vectors/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
18.hmac_test_sha_vectors.3227435559
Line 215, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/18.hmac_test_sha_vectors/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR (hmac_base_vseq.sv:37) [hmac_long_msg_vseq] Check failed cfg.hmac_vif.is_idle() == *'b* (* [*] vs * [*])
has 1 failures:
142.hmac_stress_all_with_rand_reset.2809038806
Line 754, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/142.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 21622599605 ps: (hmac_base_vseq.sv:37) [uvm_test_top.env.virtual_sequencer.hmac_long_msg_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 21622599605 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (hmac_base_vseq.sv:37) [hmac_error_vseq] Check failed cfg.hmac_vif.is_idle() == *'b* (* [*] vs * [*])
has 1 failures:
172.hmac_stress_all_with_rand_reset.2753323742
Line 408, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/172.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 57639706042 ps: (hmac_base_vseq.sv:37) [uvm_test_top.env.virtual_sequencer.hmac_error_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 57639706042 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---