Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	24921920	1			T15	8		T16	8		T18	1
all_values[1]	24921920	1			T15	8		T16	8		T18	1
all_values[2]	24921920	1			T15	8		T16	8		T18	1

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Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

143010

1

T15

9

T16

9

T18

3

auto[1]

74622750

1

T15

15

T16

15

T19

15

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

51092260

1

T15

9

T16

9

T18

3

auto[1]

23673500

1

T15

15

T16

15

T19

15

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	7870	1			T15	2		T16	2		T18	1
all_values[0]	auto[0]	auto[1]	550	1			T15	3		T16	3		T19	3
all_values[0]	auto[1]	auto[0]	24776750	1			T2	26131		T3	26131		T4	41806
all_values[0]	auto[1]	auto[1]	136750	1			T15	3		T16	3		T19	3
all_values[1]	auto[0]	auto[0]	66670	1			T15	1		T16	1		T18	1
all_values[1]	auto[0]	auto[1]	59850	1			T15	1		T16	1		T19	1
all_values[1]	auto[1]	auto[0]	10236700	1			T15	3		T16	3		T19	3
all_values[1]	auto[1]	auto[1]	14558700	1			T15	3		T16	3		T19	3
all_values[2]	auto[0]	auto[0]	7870	1			T15	2		T16	2		T18	1
all_values[2]	auto[0]	auto[1]	200	1			T4	1		T5	1		T6	1
all_values[2]	auto[1]	auto[0]	15996400	1			T15	1		T16	1		T19	1
all_values[2]	auto[1]	auto[1]	8917450	1			T15	5		T16	5		T19	5