Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::status_cg

Group : hmac_env_pkg::hmac_env_cov::status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
87.69	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	27	0	27	100.00
Crosses	168	24	144	85.71

Variables for Group hmac_env_pkg::hmac_env_cov::status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	2
sta_fifo_depth	17	0	17	100.00	100	1	1	0
sta_fifo_empty	2	0	2	100.00	100	1	1	2
sta_fifo_full	2	0	2	100.00	100	1	1	2

Crosses for Group hmac_env_pkg::hmac_env_cov::status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
fifo_empty_cross	16	0	16	100.00	100	1	1	0
fifo_full_cross	16	5	11	68.75	100	1	1	0
fifo_depth_cross	136	19	117	86.03	100	1	1	0

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

11279550

1

T2

11345

T3

11345

T4

18844

auto[1]

5649050

1

T2

14070

T3

14070

T4

7552

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

6368800

1

T2

14200

T3

14200

T4

10407

auto[1]

10559800

1

T2

11215

T3

11215

T4

15989

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9979950

1

T4

18362

T8

6999

T9

1795

auto[1]

6948650

1

T2

25415

T3

25415

T4

8034

---

Summary for Variable sta_fifo_depth

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	17	0	17	100.00

User Defined Bins for sta_fifo_depth

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	14853600	1			T2	8743		T3	8743		T4	24310
fifo_depth[1]	712350	1			T2	1836		T3	1836		T4	1010
fifo_depth[2]	421200	1			T2	1801		T3	1801		T4	543
fifo_depth[3]	222250	1			T2	1855		T3	1855		T4	229
fifo_depth[4]	177700	1			T2	1850		T3	1850		T4	147
fifo_depth[5]	121250	1			T2	1853		T3	1853		T4	51
fifo_depth[6]	115300	1			T2	1771		T3	1771		T4	66
fifo_depth[7]	94600	1			T2	1704		T3	1704		T4	20
fifo_depth[8]	79450	1			T2	1445		T3	1445		T4	16
fifo_depth[9]	55100	1			T2	1074		T3	1074		T4	4
fifo_depth[10]	35700	1			T2	703		T3	703		T7	7
fifo_depth[11]	21200	1			T2	419		T3	419		T7	5
fifo_depth[12]	10100	1			T2	198		T3	198		T7	4
fifo_depth[13]	5200	1			T2	98		T3	98		T7	6
fifo_depth[14]	2600	1			T2	48		T3	48		T7	4
fifo_depth[15]	750	1			T2	12		T3	12		T7	3
fifo_depth[16]	250	1			T2	5		T3	5		T36	5

---

Summary for Variable sta_fifo_empty

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_empty

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2075000

1

T2

16672

T3

16672

T4

2086

auto[1]

14853600

1

T2

8743

T3

8743

T4

24310

---

Summary for Variable sta_fifo_full

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_full

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16928350

1

T2

25410

T3

25410

T4

26396

auto[1]

250

1

T2

5

T3

5

T36

5

---

Summary for Cross fifo_empty_cross

Samples crossed: sta_fifo_empty hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for fifo_empty_cross

Bins

sta_fifo_empty

hmac_en

endian_swap

digest_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

103750

1

T4

266

T8

43

T9

24

auto[0]

auto[0]

auto[0]

auto[1]

160400

1

T4

333

T8

328

T9

67

auto[0]

auto[0]

auto[1]

auto[0]

338150

1

T4

718

T8

92

T9

158

auto[0]

auto[0]

auto[1]

auto[1]

85900

1

T4

165

T8

176

T9

92

auto[0]

auto[1]

auto[0]

auto[0]

317700

1

T2

3251

T3

3251

T4

179

auto[0]

auto[1]

auto[0]

auto[1]

416350

1

T2

6041

T3

6041

T4

118

auto[0]

auto[1]

auto[1]

auto[0]

328750

1

T2

4257

T3

4257

T4

105

auto[0]

auto[1]

auto[1]

auto[1]

324000

1

T2

3123

T3

3123

T4

202

auto[1]

auto[0]

auto[0]

auto[0]

1016150

1

T4

2500

T8

492

T9

121

auto[1]

auto[0]

auto[0]

auto[1]

1342200

1

T4

2243

T8

3164

T9

206

auto[1]

auto[0]

auto[1]

auto[0]

6293650

1

T4

10991

T8

1031

T9

923

auto[1]

auto[0]

auto[1]

auto[1]

639750

1

T4

1146

T8

1673

T9

204

auto[1]

auto[1]

auto[0]

auto[0]

1776600

1

T2

1683

T3

1683

T4

3129

auto[1]

auto[1]

auto[0]

auto[1]

1235650

1

T2

3225

T3

3225

T4

1639

auto[1]

auto[1]

auto[1]

auto[0]

1104800

1

T2

2154

T3

2154

T4

956

auto[1]

auto[1]

auto[1]

auto[1]

1444800

1

T2

1681

T3

1681

T4

1706

---

Summary for Cross fifo_full_cross

Samples crossed: sta_fifo_full hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	5	11	68.75	5

Automatically Generated Cross Bins for fifo_full_cross

Element holes

sta_fifo_full	hmac_en	endian_swap	digest_swap	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	*	*	--	--	4

Uncovered bins

sta_fifo_full	hmac_en	endian_swap	digest_swap	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[1]]	[auto[0]]	[auto[0]]	0	1	1

Covered bins

sta_fifo_full

hmac_en

endian_swap

digest_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

1119900

1

T4

2766

T8

535

T9

145

auto[0]

auto[0]

auto[0]

auto[1]

1502600

1

T4

2576

T8

3492

T9

273

auto[0]

auto[0]

auto[1]

auto[0]

6631800

1

T4

11709

T8

1123

T9

1081

auto[0]

auto[0]

auto[1]

auto[1]

725650

1

T4

1311

T8

1849

T9

296

auto[0]

auto[1]

auto[0]

auto[0]

2094300

1

T2

4934

T3

4934

T4

3308

auto[0]

auto[1]

auto[0]

auto[1]

1651900

1

T2

9264

T3

9264

T4

1757

auto[0]

auto[1]

auto[1]

auto[0]

1433450

1

T2

6409

T3

6409

T4

1061

auto[0]

auto[1]

auto[1]

auto[1]

1768750

1

T2

4803

T3

4803

T4

1908

auto[1]

auto[1]

auto[0]

auto[1]

100

1

T2

2

T3

2

T36

2

auto[1]

auto[1]

auto[1]

auto[0]

100

1

T2

2

T3

2

T36

2

auto[1]

auto[1]

auto[1]

auto[1]

50

1

T2

1

T3

1

T36

1

---

Summary for Cross fifo_depth_cross

Samples crossed: sta_fifo_depth hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	136	19	117	86.03	19

Automatically Generated Cross Bins for fifo_depth_cross

Element holes

sta_fifo_depth	hmac_en	endian_swap	digest_swap	COUNT	AT LEAST	NUMBER	STATUS
[fifo_depth[12]]	[auto[0]]	[auto[1]]	*	--	--	2
[fifo_depth[13]]	[auto[0]]	*	[auto[0]]	--	--	2
[fifo_depth[14]]	[auto[0]]	[auto[1]]	*	--	--	2
[fifo_depth[15]]	[auto[0]]	[auto[0]]	*	--	--	2
[fifo_depth[16]]	[auto[0]]	*	*	--	--	4

Uncovered bins

sta_fifo_depth	hmac_en	endian_swap	digest_swap	COUNT	AT LEAST	NUMBER	STATUS
[fifo_depth[9] , fifo_depth[10]]	[auto[0]]	[auto[0]]	[auto[1]]	--	--	2
[fifo_depth[11]]	[auto[0]]	[auto[0]]	[auto[1]]	0	1	1
[fifo_depth[11]]	[auto[0]]	[auto[1]]	[auto[0]]	0	1	1
[fifo_depth[14]]	[auto[0]]	[auto[0]]	[auto[1]]	0	1	1
[fifo_depth[15]]	[auto[0]]	[auto[1]]	[auto[0]]	0	1	1
[fifo_depth[16]]	[auto[1]]	[auto[0]]	[auto[0]]	0	1	1

Covered bins

sta_fifo_depth	hmac_en	endian_swap	digest_swap	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	auto[0]	auto[0]	auto[0]	1016150	1			T4	2500		T8	492		T9	121
fifo_depth[0]	auto[0]	auto[0]	auto[1]	1342200	1			T4	2243		T8	3164		T9	206
fifo_depth[0]	auto[0]	auto[1]	auto[0]	6293650	1			T4	10991		T8	1031		T9	923
fifo_depth[0]	auto[0]	auto[1]	auto[1]	639750	1			T4	1146		T8	1673		T9	204
fifo_depth[0]	auto[1]	auto[0]	auto[0]	1776600	1			T2	1683		T3	1683		T4	3129
fifo_depth[0]	auto[1]	auto[0]	auto[1]	1235650	1			T2	3225		T3	3225		T4	1639
fifo_depth[0]	auto[1]	auto[1]	auto[0]	1104800	1			T2	2154		T3	2154		T4	956
fifo_depth[0]	auto[1]	auto[1]	auto[1]	1444800	1			T2	1681		T3	1681		T4	1706
fifo_depth[1]	auto[0]	auto[0]	auto[0]	47450	1			T4	115		T8	17		T9	5
fifo_depth[1]	auto[0]	auto[0]	auto[1]	76850	1			T4	156		T8	171		T9	18
fifo_depth[1]	auto[0]	auto[1]	auto[0]	192400	1			T4	359		T8	50		T9	61
fifo_depth[1]	auto[0]	auto[1]	auto[1]	37950	1			T4	72		T8	91		T9	6
fifo_depth[1]	auto[1]	auto[0]	auto[0]	89400	1			T2	333		T3	333		T4	78
fifo_depth[1]	auto[1]	auto[0]	auto[1]	87700	1			T2	674		T3	674		T4	61
fifo_depth[1]	auto[1]	auto[1]	auto[0]	84900	1			T2	477		T3	477		T4	69
fifo_depth[1]	auto[1]	auto[1]	auto[1]	95700	1			T2	352		T3	352		T4	100
fifo_depth[2]	auto[0]	auto[0]	auto[0]	34800	1			T4	101		T8	15		T9	6
fifo_depth[2]	auto[0]	auto[0]	auto[1]	46200	1			T4	93		T8	107		T9	16
fifo_depth[2]	auto[0]	auto[1]	auto[0]	78450	1			T4	175		T8	33		T9	44
fifo_depth[2]	auto[0]	auto[1]	auto[1]	23700	1			T4	41		T8	58		T9	31
fifo_depth[2]	auto[1]	auto[0]	auto[0]	56450	1			T2	343		T3	343		T4	42
fifo_depth[2]	auto[1]	auto[0]	auto[1]	64800	1			T2	654		T3	654		T4	22
fifo_depth[2]	auto[1]	auto[1]	auto[0]	52600	1			T2	453		T3	453		T4	20
fifo_depth[2]	auto[1]	auto[1]	auto[1]	64200	1			T2	351		T3	351		T4	49
fifo_depth[3]	auto[0]	auto[0]	auto[0]	9650	1			T4	20		T8	6		T9	4
fifo_depth[3]	auto[0]	auto[0]	auto[1]	18400	1			T4	37		T8	32		T9	15
fifo_depth[3]	auto[0]	auto[1]	auto[0]	29800	1			T4	82		T8	8		T9	15
fifo_depth[3]	auto[0]	auto[1]	auto[1]	9450	1			T4	18		T8	21		T9	9
fifo_depth[3]	auto[1]	auto[0]	auto[0]	34850	1			T2	375		T3	375		T4	13
fifo_depth[3]	auto[1]	auto[0]	auto[1]	46150	1			T2	680		T3	680		T4	15
fifo_depth[3]	auto[1]	auto[1]	auto[0]	35500	1			T2	461		T3	461		T4	12
fifo_depth[3]	auto[1]	auto[1]	auto[1]	38450	1			T2	339		T3	339		T4	32
fifo_depth[4]	auto[0]	auto[0]	auto[0]	8300	1			T4	22		T8	5		T9	5
fifo_depth[4]	auto[0]	auto[0]	auto[1]	10850	1			T4	26		T8	12		T9	10
fifo_depth[4]	auto[0]	auto[1]	auto[0]	18600	1			T4	41		T8	1		T9	16
fifo_depth[4]	auto[0]	auto[1]	auto[1]	6050	1			T4	10		T8	5		T9	30
fifo_depth[4]	auto[1]	auto[0]	auto[0]	33950	1			T2	359		T3	359		T4	29
fifo_depth[4]	auto[1]	auto[0]	auto[1]	42100	1			T2	670		T3	670		T4	9
fifo_depth[4]	auto[1]	auto[1]	auto[0]	30600	1			T2	471		T3	471		T4	2
fifo_depth[4]	auto[1]	auto[1]	auto[1]	27250	1			T2	350		T3	350		T4	8
fifo_depth[5]	auto[0]	auto[0]	auto[0]	900	1			T4	2		T9	3		T5	2
fifo_depth[5]	auto[0]	auto[0]	auto[1]	4050	1			T4	8		T8	5		T9	7
fifo_depth[5]	auto[0]	auto[1]	auto[0]	5500	1			T4	15		T9	9		T5	15
fifo_depth[5]	auto[0]	auto[1]	auto[1]	3600	1			T4	11		T8	1		T9	4
fifo_depth[5]	auto[1]	auto[0]	auto[0]	22100	1			T2	353		T3	353		T4	5
fifo_depth[5]	auto[1]	auto[0]	auto[1]	36500	1			T2	676		T3	676		T4	4
fifo_depth[5]	auto[1]	auto[1]	auto[0]	26100	1			T2	477		T3	477		T4	1
fifo_depth[5]	auto[1]	auto[1]	auto[1]	22500	1			T2	347		T3	347		T4	5
fifo_depth[6]	auto[0]	auto[0]	auto[0]	1250	1			T4	5		T5	5		T6	5
fifo_depth[6]	auto[0]	auto[0]	auto[1]	3100	1			T4	11		T8	1		T9	1
fifo_depth[6]	auto[0]	auto[1]	auto[0]	7950	1			T4	28		T9	5		T5	28
fifo_depth[6]	auto[0]	auto[1]	auto[1]	2600	1			T4	5		T9	7		T5	5
fifo_depth[6]	auto[1]	auto[0]	auto[0]	21300	1			T2	354		T3	354		T4	8
fifo_depth[6]	auto[1]	auto[0]	auto[1]	34850	1			T2	636		T3	636		T4	5
fifo_depth[6]	auto[1]	auto[1]	auto[0]	23450	1			T2	430		T3	430		T9	11
fifo_depth[6]	auto[1]	auto[1]	auto[1]	20800	1			T2	351		T3	351		T4	4
fifo_depth[7]	auto[0]	auto[0]	auto[0]	450	1			T7	1		T95	8		T34	1
fifo_depth[7]	auto[0]	auto[0]	auto[1]	350	1			T7	1		T95	6		T34	1
fifo_depth[7]	auto[0]	auto[1]	auto[0]	3400	1			T4	11		T9	5		T5	11
fifo_depth[7]	auto[0]	auto[1]	auto[1]	1200	1			T4	4		T9	4		T5	4
fifo_depth[7]	auto[1]	auto[0]	auto[0]	18150	1			T2	335		T3	335		T4	1
fifo_depth[7]	auto[1]	auto[0]	auto[1]	31450	1			T2	615		T3	615		T4	1
fifo_depth[7]	auto[1]	auto[1]	auto[0]	21700	1			T2	422		T3	422		T4	1
fifo_depth[7]	auto[1]	auto[1]	auto[1]	17900	1			T2	332		T3	332		T4	2
fifo_depth[8]	auto[0]	auto[0]	auto[0]	650	1			T4	1		T9	1		T5	1
fifo_depth[8]	auto[0]	auto[0]	auto[1]	500	1			T4	2		T5	2		T6	2
fifo_depth[8]	auto[0]	auto[1]	auto[0]	1350	1			T4	4		T9	3		T5	4
fifo_depth[8]	auto[0]	auto[1]	auto[1]	1000	1			T4	4		T9	1		T5	4
fifo_depth[8]	auto[1]	auto[0]	auto[0]	16200	1			T2	299		T3	299		T4	3
fifo_depth[8]	auto[1]	auto[0]	auto[1]	26550	1			T2	518		T3	518		T4	1
fifo_depth[8]	auto[1]	auto[1]	auto[0]	19400	1			T2	378		T3	378		T9	6
fifo_depth[8]	auto[1]	auto[1]	auto[1]	13800	1			T2	250		T3	250		T4	1
fifo_depth[9]	auto[0]	auto[0]	auto[0]	100	1			T7	2		T34	2		T35	2
fifo_depth[9]	auto[0]	auto[1]	auto[0]	650	1			T4	3		T5	3		T6	3
fifo_depth[9]	auto[0]	auto[1]	auto[1]	50	1			T95	1		T51	1		T96	1
fifo_depth[9]	auto[1]	auto[0]	auto[0]	10900	1			T2	216		T3	216		T7	1
fifo_depth[9]	auto[1]	auto[0]	auto[1]	19550	1			T2	389		T3	389		T36	389
fifo_depth[9]	auto[1]	auto[1]	auto[0]	13900	1			T2	278		T3	278		T36	278
fifo_depth[9]	auto[1]	auto[1]	auto[1]	9950	1			T2	191		T3	191		T4	1
fifo_depth[10]	auto[0]	auto[0]	auto[0]	50	1			T7	1		T34	1		T35	1
fifo_depth[10]	auto[0]	auto[1]	auto[0]	50	1			T7	1		T34	1		T35	1
fifo_depth[10]	auto[0]	auto[1]	auto[1]	100	1			T7	1		T95	1		T34	1
fifo_depth[10]	auto[1]	auto[0]	auto[0]	6950	1			T2	137		T3	137		T36	137
fifo_depth[10]	auto[1]	auto[0]	auto[1]	12100	1			T2	239		T3	239		T7	3
fifo_depth[10]	auto[1]	auto[1]	auto[0]	9600	1			T2	191		T3	191		T7	1
fifo_depth[10]	auto[1]	auto[1]	auto[1]	6850	1			T2	136		T3	136		T36	136
fifo_depth[11]	auto[0]	auto[0]	auto[0]	50	1			T7	1		T34	1		T35	1
fifo_depth[11]	auto[0]	auto[1]	auto[1]	100	1			T7	2		T34	2		T35	2
fifo_depth[11]	auto[1]	auto[0]	auto[0]	4150	1			T2	82		T3	82		T7	1
fifo_depth[11]	auto[1]	auto[0]	auto[1]	8000	1			T2	159		T3	159		T7	1
fifo_depth[11]	auto[1]	auto[1]	auto[0]	5850	1			T2	117		T3	117		T36	117
fifo_depth[11]	auto[1]	auto[1]	auto[1]	3050	1			T2	61		T3	61		T36	61
fifo_depth[12]	auto[0]	auto[0]	auto[0]	50	1			T7	1		T34	1		T35	1
fifo_depth[12]	auto[0]	auto[0]	auto[1]	50	1			T7	1		T34	1		T35	1
fifo_depth[12]	auto[1]	auto[0]	auto[0]	2000	1			T2	39		T3	39		T7	1
fifo_depth[12]	auto[1]	auto[0]	auto[1]	3700	1			T2	74		T3	74		T36	74
fifo_depth[12]	auto[1]	auto[1]	auto[0]	2400	1			T2	48		T3	48		T36	48
fifo_depth[12]	auto[1]	auto[1]	auto[1]	1900	1			T2	37		T3	37		T7	1
fifo_depth[13]	auto[0]	auto[0]	auto[1]	50	1			T7	1		T34	1		T35	1
fifo_depth[13]	auto[0]	auto[1]	auto[1]	50	1			T7	1		T34	1		T35	1
fifo_depth[13]	auto[1]	auto[0]	auto[0]	850	1			T2	17		T3	17		T36	17
fifo_depth[13]	auto[1]	auto[0]	auto[1]	1800	1			T2	35		T3	35		T7	1
fifo_depth[13]	auto[1]	auto[1]	auto[0]	1600	1			T2	31		T3	31		T7	1
fifo_depth[13]	auto[1]	auto[1]	auto[1]	850	1			T2	15		T3	15		T7	2
fifo_depth[14]	auto[0]	auto[0]	auto[0]	50	1			T7	1		T34	1		T35	1
fifo_depth[14]	auto[1]	auto[0]	auto[0]	250	1			T2	5		T3	5		T36	5
fifo_depth[14]	auto[1]	auto[0]	auto[1]	800	1			T2	16		T3	16		T36	16
fifo_depth[14]	auto[1]	auto[1]	auto[0]	850	1			T2	17		T3	17		T36	17
fifo_depth[14]	auto[1]	auto[1]	auto[1]	650	1			T2	10		T3	10		T7	3
fifo_depth[15]	auto[0]	auto[1]	auto[1]	50	1			T7	1		T34	1		T35	1
fifo_depth[15]	auto[1]	auto[0]	auto[0]	200	1			T2	4		T3	4		T36	4
fifo_depth[15]	auto[1]	auto[0]	auto[1]	200	1			T2	4		T3	4		T36	4
fifo_depth[15]	auto[1]	auto[1]	auto[0]	200	1			T2	4		T3	4		T36	4
fifo_depth[15]	auto[1]	auto[1]	auto[1]	100	1			T7	2		T34	2		T35	2
fifo_depth[16]	auto[1]	auto[0]	auto[1]	100	1			T2	2		T3	2		T36	2
fifo_depth[16]	auto[1]	auto[1]	auto[0]	100	1			T2	2		T3	2		T36	2
fifo_depth[16]	auto[1]	auto[1]	auto[1]	50	1			T2	1		T3	1		T36	1