Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	24921920	1			T15	8		T16	8		T18	1
all_pins[1]	24921920	1			T15	8		T16	8		T18	1
all_pins[2]	24921920	1			T15	8		T16	8		T18	1

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	51066360	1			T15	13		T16	13		T18	3
values[0x1]	23699400	1			T15	11		T16	11		T19	11
transitions[0x0=>0x1]	20920350	1			T15	7		T16	7		T19	7
transitions[0x1=>0x0]	20920400	1			T15	8		T16	8		T19	8

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	24783120	1			T15	5		T16	5		T18	1
all_pins[0]	values[0x1]	138800	1			T15	3		T16	3		T19	3
all_pins[0]	transitions[0x0=>0x1]	138750	1			T15	2		T16	2		T19	2
all_pins[0]	transitions[0x1=>0x0]	8917450	1			T15	5		T16	5		T19	5
all_pins[1]	values[0x0]	10278770	1			T15	5		T16	5		T18	1
all_pins[1]	values[0x1]	14643150	1			T15	3		T16	3		T19	3
all_pins[1]	transitions[0x0=>0x1]	14541900	1			T15	3		T16	3		T19	3
all_pins[1]	transitions[0x1=>0x0]	37550	1			T15	3		T16	3		T19	3
all_pins[2]	values[0x0]	16004470	1			T15	3		T16	3		T18	1
all_pins[2]	values[0x1]	8917450	1			T15	5		T16	5		T19	5
all_pins[2]	transitions[0x0=>0x1]	6239700	1			T15	2		T16	2		T19	2
all_pins[2]	transitions[0x1=>0x0]	11965400	1			T2	9639		T3	9639		T4	19373