Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
92.59	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	18	2	16	88.89

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	18	2	16	88.89	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	1950	1			T15	7		T16	7		T19	7
all_values[1]	1950	1			T15	7		T16	7		T19	7
all_values[2]	1950	1			T15	7		T16	7		T19	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3700

1

T15

10

T16

10

T19

10

auto[1]

2150

1

T15

11

T16

11

T19

11

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2650

1

T15

5

T16

5

T19

5

auto[1]

3200

1

T15

16

T16

16

T19

16

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3800

1

T15

12

T16

12

T19

12

auto[1]

2050

1

T15

9

T16

9

T19

9

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	18	2	16	88.89	2
Automatically Generated Cross Bins	18	2	16	88.89	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Uncovered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[0]]	[auto[0]]	[auto[1]]	[auto[1]]	0	1	1
[all_values[2]]	[auto[0]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

cp_intr

cp_intr_test

cp_intr_en

cp_intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_values[0]

auto[0]

auto[0]

auto[0]

850

1

T15

1

T16

1

T19

1

all_values[0]

auto[0]

auto[0]

auto[1]

100

1

T15

2

T16

2

T19

2

all_values[0]

auto[0]

auto[1]

auto[0]

200

1

T4

1

T5

1

T6

1

all_values[0]

auto[1]

auto[0]

auto[1]

500

1

T15

2

T16

2

T19

2

all_values[0]

auto[1]

auto[1]

auto[1]

300

1

T15

2

T16

2

T19

2

all_values[1]

auto[0]

auto[0]

auto[0]

700

1

T15

2

T16

2

T19

2

all_values[1]

auto[0]

auto[0]

auto[1]

200

1

T4

1

T5

1

T6

1

all_values[1]

auto[0]

auto[1]

auto[0]

50

1

T15

1

T16

1

T19

1

all_values[1]

auto[0]

auto[1]

auto[1]

450

1

T15

1

T16

1

T19

1

all_values[1]

auto[1]

auto[0]

auto[1]

450

1

T15

1

T16

1

T19

1

all_values[1]

auto[1]

auto[1]

auto[1]

100

1

T15

2

T16

2

T19

2

all_values[2]

auto[0]

auto[0]

auto[0]

250

1

T15

1

T16

1

T19

1

all_values[2]

auto[0]

auto[1]

auto[0]

600

1

T4

3

T5

3

T6

3

all_values[2]

auto[0]

auto[1]

auto[1]

400

1

T15

4

T16

4

T19

4

all_values[2]

auto[1]

auto[0]

auto[1]

650

1

T15

1

T16

1

T19

1

all_values[2]

auto[1]

auto[1]

auto[1]

50

1

T15

1

T16

1

T19

1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal