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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.56 99.53 98.47 100.00 96.00 99.76 99.49 89.68


Total test records in report: 920
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T752 /workspace/coverage/default/169.hmac_stress_all_with_rand_reset.54796536319769856371036069668090967435222772658276072711275712440839173467735 Nov 22 01:10:52 PM PST 23 Nov 22 01:22:17 PM PST 23 80460760838 ps
T753 /workspace/coverage/default/17.hmac_long_msg.104285316408835800787020091166090241040978357469730627574394186637422960132792 Nov 22 01:09:54 PM PST 23 Nov 22 01:11:54 PM PST 23 14959266997 ps
T754 /workspace/coverage/default/24.hmac_long_msg.93817761070094850546951368871250570801452227039830524054863789247769114505482 Nov 22 01:09:50 PM PST 23 Nov 22 01:11:46 PM PST 23 14959266997 ps
T755 /workspace/coverage/default/32.hmac_stress_all.6552381720600886805314599754438723177141942901228688362310703065684940488224 Nov 22 01:09:57 PM PST 23 Nov 22 01:28:27 PM PST 23 146644856361 ps
T756 /workspace/coverage/default/6.hmac_back_pressure.5016687346034974554927930557232029663464511453655624786350330361589642539606 Nov 22 01:09:06 PM PST 23 Nov 22 01:10:04 PM PST 23 2592169506 ps
T757 /workspace/coverage/default/188.hmac_stress_all_with_rand_reset.35037158930994234675178611099801713005416231221953202078774794401870716477008 Nov 22 01:11:02 PM PST 23 Nov 22 01:22:39 PM PST 23 80460760838 ps
T758 /workspace/coverage/default/98.hmac_stress_all_with_rand_reset.100970627230632920540102532355813435347461002578883286436779957058032547615057 Nov 22 01:10:49 PM PST 23 Nov 22 01:22:47 PM PST 23 80460760838 ps
T759 /workspace/coverage/default/22.hmac_test_hmac_vectors.28075653923006372815736449540367841051117892203375565487757512967070453763675 Nov 22 01:10:19 PM PST 23 Nov 22 01:10:23 PM PST 23 76314633 ps
T760 /workspace/coverage/default/26.hmac_test_hmac_vectors.87083196937261390679208130001458736386531147553632243762266824284201940092372 Nov 22 01:10:19 PM PST 23 Nov 22 01:10:22 PM PST 23 76314633 ps
T761 /workspace/coverage/default/24.hmac_test_hmac_vectors.27805130087350298182396931220253257086647791829878246495324811231604342026204 Nov 22 01:09:49 PM PST 23 Nov 22 01:09:52 PM PST 23 76314633 ps
T762 /workspace/coverage/default/23.hmac_long_msg.70759531892766930535030768816038067911547492898409028949053851750872512107490 Nov 22 01:09:39 PM PST 23 Nov 22 01:11:37 PM PST 23 14959266997 ps
T763 /workspace/coverage/default/29.hmac_wipe_secret.69402788928122187507057648611293495797382257250859313563162985621002327681475 Nov 22 01:10:24 PM PST 23 Nov 22 01:11:31 PM PST 23 8070750677 ps
T764 /workspace/coverage/default/35.hmac_stress_all.54573531560388999044841958319090311921090991023771165535766239116052474091045 Nov 22 01:10:17 PM PST 23 Nov 22 01:29:01 PM PST 23 146644856361 ps
T765 /workspace/coverage/default/22.hmac_stress_all_with_rand_reset.48537595660090677380355807639816607397646158095307734876837505950485474038797 Nov 22 01:09:39 PM PST 23 Nov 22 01:21:30 PM PST 23 80460760838 ps
T766 /workspace/coverage/default/29.hmac_back_pressure.65022943849293824943145363960641007666272548221242541253291146947849584223824 Nov 22 01:10:09 PM PST 23 Nov 22 01:11:02 PM PST 23 2592169506 ps
T767 /workspace/coverage/default/147.hmac_stress_all_with_rand_reset.101952507453985820795515005250381917619622927702540842666207689053736857912646 Nov 22 01:11:09 PM PST 23 Nov 22 01:22:56 PM PST 23 80460760838 ps
T768 /workspace/coverage/default/19.hmac_alert_test.2545832180563489001983219544483207142293392608587115963745368428239192226858 Nov 22 01:10:01 PM PST 23 Nov 22 01:10:04 PM PST 23 18011528 ps
T769 /workspace/coverage/default/16.hmac_alert_test.24433826398651128360332349276455835092028152650521521086549719866730001616475 Nov 22 01:09:45 PM PST 23 Nov 22 01:09:48 PM PST 23 18011528 ps
T770 /workspace/coverage/default/49.hmac_stress_all.47870348970292464218291258431422461770064488361607325827008395360468240645519 Nov 22 01:10:20 PM PST 23 Nov 22 01:29:36 PM PST 23 146644856361 ps
T771 /workspace/coverage/default/45.hmac_alert_test.82273432404845294186186129020656445528207072521106125355599933458041836219099 Nov 22 01:10:27 PM PST 23 Nov 22 01:10:30 PM PST 23 18011528 ps
T772 /workspace/coverage/default/30.hmac_error.60253627976806676684325091035695484665334989462433373888087474340154698211666 Nov 22 01:10:19 PM PST 23 Nov 22 01:13:21 PM PST 23 26556692074 ps
T773 /workspace/coverage/default/5.hmac_long_msg.7494369091633749435299231126535214597281536053317877638673005728793313478337 Nov 22 01:09:02 PM PST 23 Nov 22 01:11:12 PM PST 23 14959266997 ps
T774 /workspace/coverage/default/45.hmac_test_sha_vectors.83715115188210061562415086416376757924464200304032109197420725702056026690220 Nov 22 01:10:18 PM PST 23 Nov 22 01:18:02 PM PST 23 63914107498 ps
T63 /workspace/coverage/default/4.hmac_sec_cm.50573244111593990703848215216868200108252572949528878224348033565362357807451 Nov 22 01:09:01 PM PST 23 Nov 22 01:09:12 PM PST 23 100939436 ps
T775 /workspace/coverage/default/0.hmac_smoke.72414746887461820678833181077585245368375001250299584794727925984045119360880 Nov 22 01:08:58 PM PST 23 Nov 22 01:09:11 PM PST 23 631560191 ps
T776 /workspace/coverage/default/40.hmac_error.36785589856736320081820661277818612401948923560619257183508622888501393115825 Nov 22 01:10:12 PM PST 23 Nov 22 01:13:21 PM PST 23 26556692074 ps
T777 /workspace/coverage/default/14.hmac_stress_all.46349640607441239259255510243689095529165902787217669906064256675367788030441 Nov 22 01:09:24 PM PST 23 Nov 22 01:28:32 PM PST 23 146644856361 ps
T778 /workspace/coverage/default/25.hmac_test_sha_vectors.71687761351075497440746573412729349926184380122385380737578889698283506023481 Nov 22 01:10:12 PM PST 23 Nov 22 01:17:29 PM PST 23 63914107498 ps
T779 /workspace/coverage/default/29.hmac_alert_test.16055472085482780520837567406820621347175563949457837103307381443245333172465 Nov 22 01:10:12 PM PST 23 Nov 22 01:10:16 PM PST 23 18011528 ps
T780 /workspace/coverage/default/0.hmac_test_hmac_vectors.97272393288382164064240109558321028832640944615282274181816223935673522383944 Nov 22 01:08:36 PM PST 23 Nov 22 01:08:50 PM PST 23 76314633 ps
T781 /workspace/coverage/default/3.hmac_stress_all.42132382536840739463944490222732170840855102806184029355428035274587455507936 Nov 22 01:08:54 PM PST 23 Nov 22 01:27:31 PM PST 23 146644856361 ps
T782 /workspace/coverage/default/21.hmac_burst_wr.58696601320989395877857457411046035397206499462266098849056246452918028918325 Nov 22 01:10:18 PM PST 23 Nov 22 01:10:58 PM PST 23 4504100639 ps
T783 /workspace/coverage/default/90.hmac_stress_all_with_rand_reset.78333542888040560827499368551437201387330336294730039377453970720936457397608 Nov 22 01:10:44 PM PST 23 Nov 22 01:21:56 PM PST 23 80460760838 ps
T784 /workspace/coverage/default/24.hmac_wipe_secret.2464605301201010206736581209751837111000513625192252175527075723874762029176 Nov 22 01:10:03 PM PST 23 Nov 22 01:11:11 PM PST 23 8070750677 ps
T785 /workspace/coverage/default/49.hmac_back_pressure.26620030177374814849248439532560656539663653372967758094396469516327778351521 Nov 22 01:10:51 PM PST 23 Nov 22 01:11:40 PM PST 23 2592169506 ps
T786 /workspace/coverage/default/175.hmac_stress_all_with_rand_reset.63071121722258313084609520214818879859355256782004453524254445181992688666849 Nov 22 01:10:51 PM PST 23 Nov 22 01:22:12 PM PST 23 80460760838 ps
T787 /workspace/coverage/default/1.hmac_smoke.84391153140511479543412056008529249817882957971148895242478897989408314843989 Nov 22 01:08:36 PM PST 23 Nov 22 01:08:53 PM PST 23 631560191 ps
T788 /workspace/coverage/default/19.hmac_smoke.26120036150642904277386390568717386862872788154109859356013251541233252151077 Nov 22 01:09:39 PM PST 23 Nov 22 01:09:45 PM PST 23 631560191 ps
T789 /workspace/coverage/default/170.hmac_stress_all_with_rand_reset.113089053848548424145257301649441635791369418174618196827963007387767995800047 Nov 22 01:11:03 PM PST 23 Nov 22 01:22:59 PM PST 23 80460760838 ps
T790 /workspace/coverage/default/6.hmac_test_sha_vectors.47566200819789722894054846989064941271884262747542144445769956907238389067305 Nov 22 01:09:02 PM PST 23 Nov 22 01:17:02 PM PST 23 63914107498 ps
T791 /workspace/coverage/default/48.hmac_error.99693347920154517548574180539396554721062460517778544685894882351378812970568 Nov 22 01:11:04 PM PST 23 Nov 22 01:14:17 PM PST 23 26556692074 ps
T792 /workspace/coverage/default/45.hmac_long_msg.69849278480625734640214900277422058326003126922534317660517627320020305003582 Nov 22 01:10:21 PM PST 23 Nov 22 01:12:17 PM PST 23 14959266997 ps
T793 /workspace/coverage/default/4.hmac_long_msg.91839390754830344102821707305867083525001605089441880356982435548839854637680 Nov 22 01:09:04 PM PST 23 Nov 22 01:11:13 PM PST 23 14959266997 ps
T794 /workspace/coverage/default/15.hmac_stress_all.82360063034273481799402468621439085946696129210178858092422214034277761903706 Nov 22 01:09:58 PM PST 23 Nov 22 01:29:11 PM PST 23 146644856361 ps
T795 /workspace/coverage/default/42.hmac_datapath_stress.12603306644589780877204465446954967066729470276960331404731341699020161919391 Nov 22 01:10:13 PM PST 23 Nov 22 01:12:41 PM PST 23 4863401336 ps
T796 /workspace/coverage/default/38.hmac_back_pressure.3237565318769489093609683473294605105954400450095115363200049420974594091724 Nov 22 01:10:13 PM PST 23 Nov 22 01:11:04 PM PST 23 2592169506 ps
T797 /workspace/coverage/default/41.hmac_alert_test.9237643209486945306399593461584767441774636195103725858134146029825822115087 Nov 22 01:10:13 PM PST 23 Nov 22 01:10:18 PM PST 23 18011528 ps
T798 /workspace/coverage/default/123.hmac_stress_all_with_rand_reset.102590549922966257737701121597283261587812231869426748817198947611264902287393 Nov 22 01:11:05 PM PST 23 Nov 22 01:22:44 PM PST 23 80460760838 ps
T799 /workspace/coverage/default/182.hmac_stress_all_with_rand_reset.28258772035000733955803674570887913553457379764449312741258360419439599694628 Nov 22 01:10:52 PM PST 23 Nov 22 01:22:25 PM PST 23 80460760838 ps
T800 /workspace/coverage/default/12.hmac_smoke.1353572839683301165988588020668273847504666291580526927377097035153757318527 Nov 22 01:09:27 PM PST 23 Nov 22 01:09:33 PM PST 23 631560191 ps
T801 /workspace/coverage/default/34.hmac_test_sha_vectors.94325875561803430832154917707234442460048419989970818459556695364531896758348 Nov 22 01:10:20 PM PST 23 Nov 22 01:17:58 PM PST 23 63914107498 ps
T802 /workspace/coverage/default/16.hmac_error.112498185805051797102983750960122054687278773117850789513912858752172890209378 Nov 22 01:09:48 PM PST 23 Nov 22 01:12:58 PM PST 23 26556692074 ps
T803 /workspace/coverage/default/3.hmac_alert_test.33351284504102726559543569686360893141067467499213369493195721425736719421481 Nov 22 01:09:00 PM PST 23 Nov 22 01:09:09 PM PST 23 18011528 ps
T804 /workspace/coverage/default/39.hmac_long_msg.67740206753319185472381112698314521209023445387114938669487777445331834928964 Nov 22 01:10:08 PM PST 23 Nov 22 01:12:10 PM PST 23 14959266997 ps
T805 /workspace/coverage/default/12.hmac_datapath_stress.25818208657856991933149278314520409542046804107956527285664465994312792409605 Nov 22 01:09:29 PM PST 23 Nov 22 01:11:57 PM PST 23 4863401336 ps
T806 /workspace/coverage/default/42.hmac_back_pressure.100907042490828698378947877246565861389442496107335231737809105976534532856590 Nov 22 01:10:12 PM PST 23 Nov 22 01:11:04 PM PST 23 2592169506 ps
T807 /workspace/coverage/default/183.hmac_stress_all_with_rand_reset.59628274480566391100638277620395160399506624908563644401854212367116531683468 Nov 22 01:11:10 PM PST 23 Nov 22 01:23:01 PM PST 23 80460760838 ps
T808 /workspace/coverage/default/81.hmac_stress_all_with_rand_reset.82947734395470532850185418811699796489536321912542253002151231893354209723752 Nov 22 01:10:58 PM PST 23 Nov 22 01:22:53 PM PST 23 80460760838 ps
T809 /workspace/coverage/default/30.hmac_alert_test.33007241300089897980477322966575421123765714640144082616687635871877360653754 Nov 22 01:10:02 PM PST 23 Nov 22 01:10:06 PM PST 23 18011528 ps
T810 /workspace/coverage/default/7.hmac_error.63263009098962652029015406098235724223020074064458728022549583728948789139149 Nov 22 01:09:00 PM PST 23 Nov 22 01:12:26 PM PST 23 26556692074 ps
T811 /workspace/coverage/default/37.hmac_stress_all.74084091726972276741135098354785680743541074430044686268060161725484276738980 Nov 22 01:10:04 PM PST 23 Nov 22 01:28:44 PM PST 23 146644856361 ps
T812 /workspace/coverage/default/119.hmac_stress_all_with_rand_reset.7072784103259491869076615775210451427801394441717990008612101142129485381387 Nov 22 01:11:01 PM PST 23 Nov 22 01:22:30 PM PST 23 80460760838 ps
T813 /workspace/coverage/default/46.hmac_burst_wr.60671783833658307777097793071162922003418785402056676161254558854907773914644 Nov 22 01:10:19 PM PST 23 Nov 22 01:10:59 PM PST 23 4504100639 ps
T814 /workspace/coverage/default/10.hmac_datapath_stress.37905309225722407093226839021177263784271493814023625091126663635854611016585 Nov 22 01:09:28 PM PST 23 Nov 22 01:11:58 PM PST 23 4863401336 ps
T815 /workspace/coverage/default/32.hmac_stress_all_with_rand_reset.30407573094351004397643522373270116206105356117999952838061848248589837923728 Nov 22 01:10:00 PM PST 23 Nov 22 01:21:49 PM PST 23 80460760838 ps
T816 /workspace/coverage/default/35.hmac_datapath_stress.96798244720171238906258974273182881074579411725164708209267129369824379797570 Nov 22 01:11:03 PM PST 23 Nov 22 01:13:29 PM PST 23 4863401336 ps
T817 /workspace/coverage/default/37.hmac_test_sha_vectors.6001252141300033840856422514573673277626531137339715359778918225139955647767 Nov 22 01:10:07 PM PST 23 Nov 22 01:17:57 PM PST 23 63914107498 ps
T818 /workspace/coverage/default/19.hmac_stress_all.72767223599292365526164892765486662887592830861024957152475592754719255293921 Nov 22 01:09:52 PM PST 23 Nov 22 01:29:26 PM PST 23 146644856361 ps
T819 /workspace/coverage/default/4.hmac_test_hmac_vectors.107619291229238758545993937431696410341382792823392562241677179210924537989956 Nov 22 01:09:06 PM PST 23 Nov 22 01:09:15 PM PST 23 76314633 ps
T820 /workspace/coverage/default/29.hmac_test_hmac_vectors.67506614704926521939315676808637448318316488446414934129561604726758555332356 Nov 22 01:10:14 PM PST 23 Nov 22 01:10:19 PM PST 23 76314633 ps
T821 /workspace/coverage/default/9.hmac_back_pressure.59286087351892044097921343481314923075718503648412219004106412008603346456498 Nov 22 01:09:20 PM PST 23 Nov 22 01:10:11 PM PST 23 2592169506 ps
T822 /workspace/coverage/default/11.hmac_burst_wr.10265314528029318607785347283985880101282918847351490598948588249681717535082 Nov 22 01:09:30 PM PST 23 Nov 22 01:10:09 PM PST 23 4504100639 ps
T823 /workspace/coverage/default/37.hmac_back_pressure.95462103025943925256467647576315340714631203228689115965218785691663550290946 Nov 22 01:10:06 PM PST 23 Nov 22 01:11:00 PM PST 23 2592169506 ps
T824 /workspace/coverage/default/48.hmac_stress_all_with_rand_reset.51782927358744592556444530595884728119062805817982412012295537503414059834997 Nov 22 01:10:59 PM PST 23 Nov 22 01:22:27 PM PST 23 80460760838 ps
T825 /workspace/coverage/default/39.hmac_stress_all_with_rand_reset.64282861643787670696855232969095972160342696920275446559594180039351738208428 Nov 22 01:10:05 PM PST 23 Nov 22 01:21:46 PM PST 23 80460760838 ps
T826 /workspace/coverage/default/46.hmac_test_hmac_vectors.2222812810962687927851011545955601173447837338685036316218730880371641426237 Nov 22 01:10:32 PM PST 23 Nov 22 01:10:34 PM PST 23 76314633 ps
T827 /workspace/coverage/default/36.hmac_error.5875882958705385501082834834147552360090670552809796756992083144281307854357 Nov 22 01:10:05 PM PST 23 Nov 22 01:13:31 PM PST 23 26556692074 ps
T828 /workspace/coverage/default/0.hmac_wipe_secret.659404354696676300612543290036983373326166704145900111250198445944268153751 Nov 22 01:08:51 PM PST 23 Nov 22 01:09:58 PM PST 23 8070750677 ps
T829 /workspace/coverage/default/37.hmac_smoke.39193870780123273998833811880907556041591531406895218992939141570813927025861 Nov 22 01:10:01 PM PST 23 Nov 22 01:10:08 PM PST 23 631560191 ps
T830 /workspace/coverage/default/82.hmac_stress_all_with_rand_reset.67593259634799466891026231057457584911307635993213876571695830682382031880936 Nov 22 01:10:46 PM PST 23 Nov 22 01:22:16 PM PST 23 80460760838 ps
T831 /workspace/coverage/default/32.hmac_error.105384469685889978149138559297151262172330691518854957743091176258138483440623 Nov 22 01:10:04 PM PST 23 Nov 22 01:13:22 PM PST 23 26556692074 ps
T832 /workspace/coverage/default/45.hmac_stress_all.84583802421945441334603218410596063407613045862728632365827139752382240721695 Nov 22 01:10:25 PM PST 23 Nov 22 01:29:13 PM PST 23 146644856361 ps
T833 /workspace/coverage/default/13.hmac_alert_test.75906308292552899334234284830982334253329010578881330176907124155859130974339 Nov 22 01:09:29 PM PST 23 Nov 22 01:09:30 PM PST 23 18011528 ps
T834 /workspace/coverage/default/9.hmac_smoke.103745993882702760986883523153643038114407828050113956417473768024250034339829 Nov 22 01:09:08 PM PST 23 Nov 22 01:09:20 PM PST 23 631560191 ps
T835 /workspace/coverage/default/51.hmac_stress_all_with_rand_reset.76750896491341484788013281305240345305389427093393647688831434367479083536777 Nov 22 01:10:22 PM PST 23 Nov 22 01:22:24 PM PST 23 80460760838 ps
T836 /workspace/coverage/default/161.hmac_stress_all_with_rand_reset.96092034156200668817563468616877148628434133109414497738553594321547749404798 Nov 22 01:11:01 PM PST 23 Nov 22 01:22:12 PM PST 23 80460760838 ps
T837 /workspace/coverage/default/33.hmac_long_msg.37499862829091529528352815289325317819838592637379618241738230370206103521114 Nov 22 01:10:13 PM PST 23 Nov 22 01:12:12 PM PST 23 14959266997 ps
T838 /workspace/coverage/default/4.hmac_alert_test.110378409693765838326357311426910103373065039628094133705148061490745906127560 Nov 22 01:09:06 PM PST 23 Nov 22 01:09:14 PM PST 23 18011528 ps
T839 /workspace/coverage/default/29.hmac_datapath_stress.13693979880261802821550058842408311523715121638124473782896669406650956536920 Nov 22 01:10:13 PM PST 23 Nov 22 01:12:41 PM PST 23 4863401336 ps
T840 /workspace/coverage/default/17.hmac_stress_all.35408921512235022681794312812595356023522312059527366367596430788129610551306 Nov 22 01:09:43 PM PST 23 Nov 22 01:28:08 PM PST 23 146644856361 ps
T841 /workspace/coverage/default/64.hmac_stress_all_with_rand_reset.55707874402733531582184450246215650282286039410807860158806820110799845640929 Nov 22 01:10:30 PM PST 23 Nov 22 01:22:28 PM PST 23 80460760838 ps
T842 /workspace/coverage/default/24.hmac_datapath_stress.15194389245242236183507626794103287662244732857542647960708028793766372531785 Nov 22 01:09:52 PM PST 23 Nov 22 01:12:16 PM PST 23 4863401336 ps
T843 /workspace/coverage/default/11.hmac_test_sha_vectors.71686496713069040306843959502598792596234767761959598712976682543511991935362 Nov 22 01:09:24 PM PST 23 Nov 22 01:17:15 PM PST 23 63914107498 ps
T844 /workspace/coverage/default/8.hmac_test_sha_vectors.24102191450723606743110128874874974840745597394489692272340717175733092227515 Nov 22 01:09:06 PM PST 23 Nov 22 01:17:05 PM PST 23 63914107498 ps
T845 /workspace/coverage/default/15.hmac_smoke.69985518805562741887230222065568524095269067172248010839031155016799517983875 Nov 22 01:09:22 PM PST 23 Nov 22 01:09:28 PM PST 23 631560191 ps
T846 /workspace/coverage/default/85.hmac_stress_all_with_rand_reset.91262450200378849598451200945775894254351614455710370130591710318507394764703 Nov 22 01:10:44 PM PST 23 Nov 22 01:22:13 PM PST 23 80460760838 ps
T847 /workspace/coverage/default/48.hmac_test_sha_vectors.81343871402111972013586743572286185792644799075395839545048930734662083439602 Nov 22 01:10:58 PM PST 23 Nov 22 01:18:32 PM PST 23 63914107498 ps
T848 /workspace/coverage/default/167.hmac_stress_all_with_rand_reset.44385886901755246547673101246078509406113347158069654040686651107112941304803 Nov 22 01:10:59 PM PST 23 Nov 22 01:22:54 PM PST 23 80460760838 ps
T849 /workspace/coverage/default/40.hmac_back_pressure.16319871563909061394357442725608622144622106877046884732208399737162029874798 Nov 22 01:10:04 PM PST 23 Nov 22 01:10:58 PM PST 23 2592169506 ps
T850 /workspace/coverage/default/136.hmac_stress_all_with_rand_reset.109245218595707176063294709979648483200560174164614386523613350465236803909527 Nov 22 01:11:14 PM PST 23 Nov 22 01:23:21 PM PST 23 80460760838 ps
T851 /workspace/coverage/default/95.hmac_stress_all_with_rand_reset.66841129568314432608563670030376094128633804366951928940513299972368638578942 Nov 22 01:10:38 PM PST 23 Nov 22 01:22:32 PM PST 23 80460760838 ps
T852 /workspace/coverage/default/12.hmac_alert_test.34001662806366750698164799174515614196776042965351253799520066973139118293410 Nov 22 01:09:25 PM PST 23 Nov 22 01:09:27 PM PST 23 18011528 ps
T853 /workspace/coverage/default/22.hmac_test_sha_vectors.81634430652687797767517799378440126256266066061782577129595074967321645643976 Nov 22 01:10:11 PM PST 23 Nov 22 01:17:56 PM PST 23 63914107498 ps
T854 /workspace/coverage/default/17.hmac_datapath_stress.93047631796547629274441735706799091669946141304574895065100306304336837195508 Nov 22 01:09:41 PM PST 23 Nov 22 01:12:06 PM PST 23 4863401336 ps
T855 /workspace/coverage/default/42.hmac_test_hmac_vectors.90787418282493648834304860584152846056026715355133266670798064964828804420284 Nov 22 01:10:19 PM PST 23 Nov 22 01:10:23 PM PST 23 76314633 ps
T856 /workspace/coverage/default/22.hmac_datapath_stress.38572123903152824040039393639745754962786506997427756780899817593609510585799 Nov 22 01:10:16 PM PST 23 Nov 22 01:12:42 PM PST 23 4863401336 ps
T857 /workspace/coverage/default/140.hmac_stress_all_with_rand_reset.88389226014706121810085725526422730626770052490929740542951868293273789648045 Nov 22 01:10:44 PM PST 23 Nov 22 01:22:52 PM PST 23 80460760838 ps
T858 /workspace/coverage/default/39.hmac_datapath_stress.84643814850501961266096646909425972951185307013881209292653285652074862580512 Nov 22 01:10:05 PM PST 23 Nov 22 01:12:30 PM PST 23 4863401336 ps
T859 /workspace/coverage/default/42.hmac_burst_wr.55242646744832736260245018926585788365439485981476868796743648612286793163786 Nov 22 01:10:13 PM PST 23 Nov 22 01:10:53 PM PST 23 4504100639 ps
T860 /workspace/coverage/default/7.hmac_smoke.37949611309712832811143691131388077348110564539337231327866101593079592598635 Nov 22 01:09:01 PM PST 23 Nov 22 01:09:15 PM PST 23 631560191 ps
T861 /workspace/coverage/default/38.hmac_smoke.87698210905537612671628461309916932567617666712943153029491563227111479494738 Nov 22 01:10:11 PM PST 23 Nov 22 01:10:19 PM PST 23 631560191 ps
T862 /workspace/coverage/default/10.hmac_stress_all.102690644148279516861989729534410457709651001507061167810070530274661157219521 Nov 22 01:09:27 PM PST 23 Nov 22 01:28:27 PM PST 23 146644856361 ps
T863 /workspace/coverage/default/19.hmac_wipe_secret.112500188495994465687643875514747189212925929002034486802975424049951823307189 Nov 22 01:09:49 PM PST 23 Nov 22 01:10:51 PM PST 23 8070750677 ps
T864 /workspace/coverage/default/19.hmac_test_sha_vectors.43042093124483481822473925517969271664514297076111538914861294300768855992743 Nov 22 01:09:40 PM PST 23 Nov 22 01:17:16 PM PST 23 63914107498 ps
T865 /workspace/coverage/default/86.hmac_stress_all_with_rand_reset.39101562049096300017597752681027989736737099601622865249728407702581162756083 Nov 22 01:10:45 PM PST 23 Nov 22 01:22:38 PM PST 23 80460760838 ps
T866 /workspace/coverage/default/37.hmac_wipe_secret.11625760185031261433015878131967278980095796279498740832169477404054692794716 Nov 22 01:10:13 PM PST 23 Nov 22 01:11:22 PM PST 23 8070750677 ps
T867 /workspace/coverage/default/0.hmac_stress_all_with_rand_reset.75085556379723211402461991207385680801901308489048922512955798848810693998335 Nov 22 01:08:40 PM PST 23 Nov 22 01:20:37 PM PST 23 80460760838 ps
T868 /workspace/coverage/default/22.hmac_smoke.65305770278023125094736175127683803196347457797696540828200933710369403431921 Nov 22 01:10:24 PM PST 23 Nov 22 01:10:32 PM PST 23 631560191 ps
T869 /workspace/coverage/default/46.hmac_error.1059962550074423254141004187120706672644848470596660324193532430036028182386 Nov 22 01:10:34 PM PST 23 Nov 22 01:13:39 PM PST 23 26556692074 ps
T870 /workspace/coverage/default/143.hmac_stress_all_with_rand_reset.5466957646941995126295371556842223497536995110517533430595514144213282497509 Nov 22 01:10:45 PM PST 23 Nov 22 01:22:48 PM PST 23 80460760838 ps
T871 /workspace/coverage/default/58.hmac_stress_all_with_rand_reset.60505866659178617628333129414270604727233111332820554893216113072727252303623 Nov 22 01:10:20 PM PST 23 Nov 22 01:22:14 PM PST 23 80460760838 ps
T872 /workspace/coverage/default/13.hmac_stress_all.102018532095704025316842806644898137532503964400658844156118909388466258169256 Nov 22 01:09:31 PM PST 23 Nov 22 01:28:56 PM PST 23 146644856361 ps
T873 /workspace/coverage/default/68.hmac_stress_all_with_rand_reset.66987583525677632963427351180022545264631576514788982343956858648527135775534 Nov 22 01:10:39 PM PST 23 Nov 22 01:22:25 PM PST 23 80460760838 ps
T874 /workspace/coverage/default/22.hmac_error.48491310595243807704474290654552569393721332985205670080882036475715004657416 Nov 22 01:10:19 PM PST 23 Nov 22 01:13:24 PM PST 23 26556692074 ps
T875 /workspace/coverage/default/20.hmac_smoke.41727245499162642900864861839231284078386102435165143411376254499433465921518 Nov 22 01:09:49 PM PST 23 Nov 22 01:09:55 PM PST 23 631560191 ps
T876 /workspace/coverage/cover_reg_top/0.hmac_intr_test.18769058790675859393629097636195621296763493015187824189535818171087240991986 Nov 22 01:06:26 PM PST 23 Nov 22 01:06:28 PM PST 23 22993631 ps
T877 /workspace/coverage/cover_reg_top/1.hmac_intr_test.25931961156590390763214447650067486514655819517304025182524485979809971363230 Nov 22 01:06:31 PM PST 23 Nov 22 01:06:33 PM PST 23 22993631 ps
T878 /workspace/coverage/cover_reg_top/10.hmac_intr_test.81700936131488190676644948534023075211912404901187913562682646409266968359495 Nov 22 01:06:41 PM PST 23 Nov 22 01:06:43 PM PST 23 22993631 ps
T879 /workspace/coverage/cover_reg_top/35.hmac_intr_test.51955662355113237793412118261745437059377675702903386129826320148659322626512 Nov 22 01:06:46 PM PST 23 Nov 22 01:06:51 PM PST 23 22993631 ps
T880 /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.26893817074102407386453189960777897384268129906394556574337803124063482700390 Nov 22 01:06:28 PM PST 23 Nov 22 01:06:31 PM PST 23 89028817 ps
T881 /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.41043734202465201721992828192696860426034806158324202657842493717871268435506 Nov 22 01:06:43 PM PST 23 Nov 22 01:06:49 PM PST 23 89028817 ps
T882 /workspace/coverage/cover_reg_top/9.hmac_csr_rw.83113417884650319135477380425107613444193766161753700979664084088726345624365 Nov 22 01:06:42 PM PST 23 Nov 22 01:06:47 PM PST 23 31297136 ps
T883 /workspace/coverage/cover_reg_top/26.hmac_intr_test.17013352821696429655026163866633664839403336627626798495287769977905890464428 Nov 22 01:06:49 PM PST 23 Nov 22 01:06:52 PM PST 23 22993631 ps
T884 /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.90829830488346250994268754947279653731127026662832499953721990528357582689648 Nov 22 01:06:41 PM PST 23 Nov 22 01:06:43 PM PST 23 89028817 ps
T885 /workspace/coverage/cover_reg_top/16.hmac_tl_errors.63986638103061272423628253304125161449452973576893988081334802047699479795759 Nov 22 01:06:50 PM PST 23 Nov 22 01:06:54 PM PST 23 199170793 ps
T886 /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.23554572190949335432714747129093369365225267711087409958534765297114404492008 Nov 22 01:06:33 PM PST 23 Nov 22 01:17:53 PM PST 23 129656135129 ps
T887 /workspace/coverage/cover_reg_top/0.hmac_tl_errors.68424127896913831127640611737503797891984625424217676592038072366555521072564 Nov 22 01:06:30 PM PST 23 Nov 22 01:06:34 PM PST 23 199170793 ps
T888 /workspace/coverage/cover_reg_top/12.hmac_intr_test.87317631350839817860642104404245378877204255435476579976558846356849170446913 Nov 22 01:06:42 PM PST 23 Nov 22 01:06:45 PM PST 23 22993631 ps
T889 /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.17612620068123257800049959092410402562021007730109714849130459162453755308942 Nov 22 01:06:42 PM PST 23 Nov 22 01:18:09 PM PST 23 129656135129 ps
T890 /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.32152690651486552866211658954023560545071883365416763625487285123877299801337 Nov 22 01:06:39 PM PST 23 Nov 22 01:17:54 PM PST 23 129656135129 ps
T891 /workspace/coverage/cover_reg_top/7.hmac_tl_errors.13103779409574486687291450996223120526224035476289679506995218074261387538265 Nov 22 01:06:37 PM PST 23 Nov 22 01:06:40 PM PST 23 199170793 ps
T892 /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.37086170603258210063105700876018483988333653710620673597472897725867019203513 Nov 22 01:06:39 PM PST 23 Nov 22 01:06:43 PM PST 23 179635235 ps
T893 /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.75456923003416060479356984616673357360745659115262994813463052120411258757171 Nov 22 01:06:27 PM PST 23 Nov 22 01:06:31 PM PST 23 179635235 ps
T894 /workspace/coverage/cover_reg_top/1.hmac_tl_errors.83708567248834521380285671635403264707990649198706019663567214146139416788676 Nov 22 01:06:21 PM PST 23 Nov 22 01:06:24 PM PST 23 199170793 ps
T895 /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.109534006337744714916444574403365695501637615256798078651365224550960869189865 Nov 22 01:06:43 PM PST 23 Nov 22 01:17:47 PM PST 23 129656135129 ps
T896 /workspace/coverage/cover_reg_top/5.hmac_intr_test.101144809695792469813593794660767803044229632091410049433357210194176578858726 Nov 22 01:06:22 PM PST 23 Nov 22 01:06:24 PM PST 23 22993631 ps
T897 /workspace/coverage/cover_reg_top/8.hmac_intr_test.92889851021535615666263403921695664527091764722304854155855258311165009411983 Nov 22 01:06:42 PM PST 23 Nov 22 01:06:46 PM PST 23 22993631 ps
T898 /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.11197252489284732597627518357615745399308311921818248038312999994082556844555 Nov 22 01:06:26 PM PST 23 Nov 22 01:06:28 PM PST 23 180081660 ps
T899 /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.12382214882284997806121175450943881612043256282312158682517299394224459824942 Nov 22 01:06:55 PM PST 23 Nov 22 01:06:57 PM PST 23 89028817 ps
T900 /workspace/coverage/cover_reg_top/21.hmac_intr_test.44807618878180178850648844788069161960014903539004416388285197730753236367283 Nov 22 01:06:58 PM PST 23 Nov 22 01:07:00 PM PST 23 22993631 ps
T901 /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.24898436190713502121777643079420186093840073249472737513481537627707875615102 Nov 22 01:06:24 PM PST 23 Nov 22 01:17:16 PM PST 23 129656135129 ps
T902 /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.75060704352913979794328764702776657251810607320288505760452168219668831854957 Nov 22 01:06:34 PM PST 23 Nov 22 01:06:37 PM PST 23 180081660 ps
T903 /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.18714079659344233050835942507533711767928629350147512001262817628256315942405 Nov 22 01:06:41 PM PST 23 Nov 22 01:18:01 PM PST 23 129656135129 ps
T904 /workspace/coverage/cover_reg_top/13.hmac_tl_errors.32072926608328802645760489959966738220898978054028171790121471385437625340258 Nov 22 01:06:41 PM PST 23 Nov 22 01:06:44 PM PST 23 199170793 ps
T905 /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.92079299055080460692898314360223110054178736212464897821278513277924943079914 Nov 22 01:06:36 PM PST 23 Nov 22 01:17:50 PM PST 23 129656135129 ps
T906 /workspace/coverage/cover_reg_top/31.hmac_intr_test.32475122038178172635556639427223766021067844683839706274009358743620484541603 Nov 22 01:06:47 PM PST 23 Nov 22 01:06:51 PM PST 23 22993631 ps
T907 /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.11833040375516702010314075432040228137357796672566361472830877755710805647731 Nov 22 01:06:42 PM PST 23 Nov 22 01:06:48 PM PST 23 89028817 ps
T908 /workspace/coverage/cover_reg_top/3.hmac_intr_test.55561582072620436045940390845748204169990013408256899883178789681423075450960 Nov 22 01:06:33 PM PST 23 Nov 22 01:06:34 PM PST 23 22993631 ps
T909 /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.38048355777500985777585857482834167224258742096972982325757950316274591521812 Nov 22 01:06:42 PM PST 23 Nov 22 01:18:04 PM PST 23 129656135129 ps
T910 /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.47162709958818837125449277027172766892106174717301487188822260338454325090291 Nov 22 01:06:26 PM PST 23 Nov 22 01:17:24 PM PST 23 129656135129 ps
T911 /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.21239614965266668912457518355531445911201708877264513071347355437025570291995 Nov 22 01:06:58 PM PST 23 Nov 22 01:18:20 PM PST 23 129656135129 ps
T912 /workspace/coverage/cover_reg_top/14.hmac_intr_test.3910089613191760431020209421007820991911791174842317522224214513228494894303 Nov 22 01:06:42 PM PST 23 Nov 22 01:06:47 PM PST 23 22993631 ps
T913 /workspace/coverage/cover_reg_top/13.hmac_intr_test.41746418706543951586324699752761362649152983362069734754714644379317817057294 Nov 22 01:06:42 PM PST 23 Nov 22 01:06:45 PM PST 23 22993631 ps
T914 /workspace/coverage/cover_reg_top/17.hmac_csr_rw.18988652545367393329786271264028103006196201115092075167928309439810126798437 Nov 22 01:06:50 PM PST 23 Nov 22 01:06:52 PM PST 23 31297136 ps
T915 /workspace/coverage/cover_reg_top/2.hmac_tl_errors.69114806898031137120510992005215155774175123229103235871294892178916457549212 Nov 22 01:06:31 PM PST 23 Nov 22 01:06:35 PM PST 23 199170793 ps
T916 /workspace/coverage/cover_reg_top/23.hmac_intr_test.102755931660159191108866666244282354636211544265974990651916355406378623948439 Nov 22 01:06:43 PM PST 23 Nov 22 01:06:48 PM PST 23 22993631 ps
T917 /workspace/coverage/cover_reg_top/27.hmac_intr_test.4920424663731858451489967598374762835055743447560496232739433277125054722099 Nov 22 01:06:58 PM PST 23 Nov 22 01:07:00 PM PST 23 22993631 ps
T918 /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.23287517197984444320918219362443314730278089041007044448006972226648866733481 Nov 22 01:06:40 PM PST 23 Nov 22 01:06:43 PM PST 23 89028817 ps
T919 /workspace/coverage/cover_reg_top/36.hmac_intr_test.105373550734081361564803896744987721909248822361492108923111487684970996606909 Nov 22 01:06:46 PM PST 23 Nov 22 01:06:50 PM PST 23 22993631 ps
T920 /workspace/coverage/cover_reg_top/2.hmac_intr_test.32472157335663882202506620541043277570325103670801798632885544126555544566465 Nov 22 01:06:33 PM PST 23 Nov 22 01:06:34 PM PST 23 22993631 ps

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.49734910213641612051546293052539802051385515476430087101658934481023979049073
Short name T13
Test name
Test status
Simulation time 1011878577 ps
CPU time 6.37 seconds
Started Nov 22 01:06:30 PM PST 23
Finished Nov 22 01:06:38 PM PST 23
Peak memory 196844 kb
Host smart-ea057159-5ec2-469e-83d1-f30928a0efea
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49734910213641612051546293052539802051385515476430087101658934481023979049073 -assert nopo
stproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover
_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_bit_bash.49734910213641612051546293052539802051385515476430087101658934481023979049073
Directory /workspace/3.hmac_csr_bit_bash/latest

Test location /workspace/coverage/default/106.hmac_stress_all_with_rand_reset.30803853475245576817250041965501394539271525059781564777572194772978429092414
Short name T4
Test name
Test status
Simulation time 80460760838 ps
CPU time 702.23 seconds
Started Nov 22 01:11:01 PM PST 23
Finished Nov 22 01:22:45 PM PST 23
Peak memory 209308 kb
Host smart-075e26c3-4101-4452-b4ee-e3909310dba4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=30803853475245576817250041965501394539271525059781564777572194772978429092414 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 106.hmac_stress_all_with_rand_reset.30803853475245576817250041965501394539271525059781564777572194772978429092414
Directory /workspace/106.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.29904664304044779645256094124581534567566891773534888637482674643117007435144
Short name T17
Test name
Test status
Simulation time 129656135129 ps
CPU time 666.06 seconds
Started Nov 22 01:06:41 PM PST 23
Finished Nov 22 01:17:48 PM PST 23
Peak memory 216424 kb
Host smart-5e934bea-033e-4729-93df-c950c7bb95e3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990466430404477964525609412458153456756689
1773534888637482674643117007435144 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_csr_mem_rw_with_rand_reset.2990466430404477964525609
4124581534567566891773534888637482674643117007435144
Directory /workspace/9.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/1.hmac_datapath_stress.65095824689841339726550757959538699870039285356261249668762965145652230367020
Short name T37
Test name
Test status
Simulation time 4863401336 ps
CPU time 136.95 seconds
Started Nov 22 01:08:52 PM PST 23
Finished Nov 22 01:11:15 PM PST 23
Peak memory 198448 kb
Host smart-85343323-b24c-441c-99b3-19438678212b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=65095824689841339726550757959538699870039285356261249668762965145652230367020 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.hmac_datapath_stress.65095824689841339726550757959538699870039285356261249668762965145652230367020
Directory /workspace/1.hmac_datapath_stress/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_intr_test.29329204359743972007308118571982484042705279052555870942873708035892790511645
Short name T16
Test name
Test status
Simulation time 22993631 ps
CPU time 0.59 seconds
Started Nov 22 01:06:41 PM PST 23
Finished Nov 22 01:06:43 PM PST 23
Peak memory 183620 kb
Host smart-dacc392e-a4b1-4009-ae8f-a2e606fe3f6a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29329204359743972007308118571982484042705279052555870942873708035892790511645 -assert nopostproc +U
VM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 11.hmac_intr_test.29329204359743972007308118571982484042705279052555870942873708035892790511645
Directory /workspace/11.hmac_intr_test/latest

Test location /workspace/coverage/default/42.hmac_stress_all.113189391210954719670258667489607820812924698537165511714606213839924157205233
Short name T51
Test name
Test status
Simulation time 146644856361 ps
CPU time 1097.66 seconds
Started Nov 22 01:10:14 PM PST 23
Finished Nov 22 01:28:36 PM PST 23
Peak memory 210872 kb
Host smart-d3e5db1e-b772-4c7f-a88e-09fb0758731a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113189391210954719670258
667489607820812924698537165511714606213839924157205233 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_stress_all.1131893912109547196702
58667489607820812924698537165511714606213839924157205233
Directory /workspace/42.hmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.96948734817094288184968181591556120994288742181136187182605749675043104709209
Short name T75
Test name
Test status
Simulation time 180081660 ps
CPU time 1.9 seconds
Started Nov 22 01:06:33 PM PST 23
Finished Nov 22 01:06:36 PM PST 23
Peak memory 198736 kb
Host smart-26209dcc-ea94-4ef1-b825-1c95153b253d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96948734817094288184968181591556120994288742181136187182605749675043104709209 -assert n
opostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_intg_err.96948734817094288184968181591556120994288742181136187182605749675043104709209
Directory /workspace/1.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/13.hmac_back_pressure.26010155330637065313095963230856044888563358497237965247117783747008688990429
Short name T40
Test name
Test status
Simulation time 2592169506 ps
CPU time 48.19 seconds
Started Nov 22 01:09:27 PM PST 23
Finished Nov 22 01:10:17 PM PST 23
Peak memory 231312 kb
Host smart-777d9f68-50e8-4f79-ac54-0f7235851c41
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=26010155330637065313095963230856044888563358497237965247117783747008688990429 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 13.hmac_back_pressure.26010155330637065313095963230856044888563358497237965247117783747008688990429
Directory /workspace/13.hmac_back_pressure/latest

Test location /workspace/coverage/default/0.hmac_sec_cm.99331175998109571230887712914558605999757727203931010116797114945070409123200
Short name T62
Test name
Test status
Simulation time 100939436 ps
CPU time 0.85 seconds
Started Nov 22 01:08:51 PM PST 23
Finished Nov 22 01:08:59 PM PST 23
Peak memory 215488 kb
Host smart-6c7650a0-9cb4-4c8d-8164-5c0333ab2076
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99331175998109571230887712914558605999757727203931010116797114945070409123200 -assert nopostpro
c +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 0.hmac_sec_cm.99331175998109571230887712914558605999757727203931010116797114945070409123200
Directory /workspace/0.hmac_sec_cm/latest

Test location /workspace/coverage/default/15.hmac_error.39621184449806822381563002524326429345170981067656431192464084918176690244815
Short name T209
Test name
Test status
Simulation time 26556692074 ps
CPU time 196.43 seconds
Started Nov 22 01:09:40 PM PST 23
Finished Nov 22 01:12:58 PM PST 23
Peak memory 198616 kb
Host smart-0922a29f-30ba-427c-a24f-3446c15e4396
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39621184449806822381563002524326429345170981067656431192464084918176690244815 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 15.hmac_error.39621184449806822381563002524326429345170981067656431192464084918176690244815
Directory /workspace/15.hmac_error/latest

Test location /workspace/coverage/default/0.hmac_alert_test.100154181819847133091006267625546448040223454780897670107563156834182377531365
Short name T259
Test name
Test status
Simulation time 18011528 ps
CPU time 0.54 seconds
Started Nov 22 01:08:53 PM PST 23
Finished Nov 22 01:08:59 PM PST 23
Peak memory 192728 kb
Host smart-b84f1975-4908-4566-9299-2c639e8bc21f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100154181819847133091006267625546448040223454780897670107563156834182377531365 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 0.hmac_alert_test.100154181819847133091006267625546448040223454780897670107563156834182377531365
Directory /workspace/0.hmac_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.48265488455490668595276922371195337803643858481237989151352031006016573679159
Short name T89
Test name
Test status
Simulation time 89028817 ps
CPU time 1.05 seconds
Started Nov 22 01:06:35 PM PST 23
Finished Nov 22 01:06:37 PM PST 23
Peak memory 197532 kb
Host smart-dfe57de9-e6ec-4697-8a15-801f8c75e6de
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48265488455490668595276922371195337803643858481237989151352031006016573679159
-assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_same_csr_outstanding.48265488455490668595276922371195337803643858481237989151352031006016573679159
Directory /workspace/0.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.60071855061299180122761212960522794520956583663339416130512076289950994750147
Short name T118
Test name
Test status
Simulation time 179635235 ps
CPU time 1.88 seconds
Started Nov 22 01:06:28 PM PST 23
Finished Nov 22 01:06:31 PM PST 23
Peak memory 197020 kb
Host smart-33b49545-2671-485b-863f-3ce47859887c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60071855061299180122761212960522794520956583663339416130512076289950994750147 -assert nopo
stproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover
_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_aliasing.60071855061299180122761212960522794520956583663339416130512076289950994750147
Directory /workspace/0.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.104070285326939712423621215973879177306269720690045086876598792879844876914946
Short name T20
Test name
Test status
Simulation time 1011878577 ps
CPU time 6.37 seconds
Started Nov 22 01:06:31 PM PST 23
Finished Nov 22 01:06:38 PM PST 23
Peak memory 197148 kb
Host smart-61b4adae-1bde-4fa8-9dfe-55b4163f1e4c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104070285326939712423621215973879177306269720690045086876598792879844876914946 -assert nop
ostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_bit_bash.104070285326939712423621215973879177306269720690045086876598792879844876914946
Directory /workspace/0.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.111655710527481110603859598752439364195059529545727478291838750814202969811400
Short name T143
Test name
Test status
Simulation time 30475714 ps
CPU time 0.66 seconds
Started Nov 22 01:06:26 PM PST 23
Finished Nov 22 01:06:27 PM PST 23
Peak memory 194316 kb
Host smart-3ac3e7fc-620e-4ce9-900a-804c9c223f88
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111655710527481110603859598752439364195059529545727478291838750814202969811400 -assert nop
ostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_hw_reset.111655710527481110603859598752439364195059529545727478291838750814202969811400
Directory /workspace/0.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.92079299055080460692898314360223110054178736212464897821278513277924943079914
Short name T905
Test name
Test status
Simulation time 129656135129 ps
CPU time 672.58 seconds
Started Nov 22 01:06:36 PM PST 23
Finished Nov 22 01:17:50 PM PST 23
Peak memory 216444 kb
Host smart-e1166ce8-efc5-4018-8e10-2926171f7b93
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9207929905508046069289831436022311005417873
6212464897821278513277924943079914 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_mem_rw_with_rand_reset.9207929905508046069289831
4360223110054178736212464897821278513277924943079914
Directory /workspace/0.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_rw.6387533970401782576340484022780879659635030904239645427012266438211629290469
Short name T14
Test name
Test status
Simulation time 31297136 ps
CPU time 0.67 seconds
Started Nov 22 01:06:25 PM PST 23
Finished Nov 22 01:06:26 PM PST 23
Peak memory 194920 kb
Host smart-fb87dba4-14f3-4e29-a2e3-1182ee20c68c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6387533970401782576340484022780879659635030904239645427012266438211629290469 -assert nopostproc
+UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 0.hmac_csr_rw.6387533970401782576340484022780879659635030904239645427012266438211629290469
Directory /workspace/0.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_intr_test.18769058790675859393629097636195621296763493015187824189535818171087240991986
Short name T876
Test name
Test status
Simulation time 22993631 ps
CPU time 0.58 seconds
Started Nov 22 01:06:26 PM PST 23
Finished Nov 22 01:06:28 PM PST 23
Peak memory 184224 kb
Host smart-eb397718-1e3b-4424-b8a3-c4ea42f0b67d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18769058790675859393629097636195621296763493015187824189535818171087240991986 -assert nopostproc +U
VM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 0.hmac_intr_test.18769058790675859393629097636195621296763493015187824189535818171087240991986
Directory /workspace/0.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_errors.68424127896913831127640611737503797891984625424217676592038072366555521072564
Short name T887
Test name
Test status
Simulation time 199170793 ps
CPU time 2.28 seconds
Started Nov 22 01:06:30 PM PST 23
Finished Nov 22 01:06:34 PM PST 23
Peak memory 198696 kb
Host smart-3d42f6ac-7259-41e1-8375-7fe68891d18a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68424127896913831127640611737503797891984625424217676592038072366555521072564 -assert nopostproc +U
VM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 0.hmac_tl_errors.68424127896913831127640611737503797891984625424217676592038072366555521072564
Directory /workspace/0.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.11197252489284732597627518357615745399308311921818248038312999994082556844555
Short name T898
Test name
Test status
Simulation time 180081660 ps
CPU time 1.81 seconds
Started Nov 22 01:06:26 PM PST 23
Finished Nov 22 01:06:28 PM PST 23
Peak memory 198724 kb
Host smart-a3927859-80ee-4215-ae9e-cf7f3a44b9c2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11197252489284732597627518357615745399308311921818248038312999994082556844555 -assert n
opostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_intg_err.11197252489284732597627518357615745399308311921818248038312999994082556844555
Directory /workspace/0.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.75456923003416060479356984616673357360745659115262994813463052120411258757171
Short name T893
Test name
Test status
Simulation time 179635235 ps
CPU time 1.83 seconds
Started Nov 22 01:06:27 PM PST 23
Finished Nov 22 01:06:31 PM PST 23
Peak memory 196892 kb
Host smart-8a64f613-580a-4c78-803f-22626380cd3c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75456923003416060479356984616673357360745659115262994813463052120411258757171 -assert nopo
stproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover
_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_aliasing.75456923003416060479356984616673357360745659115262994813463052120411258757171
Directory /workspace/1.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.31193498933883877276396155415678012710008663787662666344653871359307358507796
Short name T136
Test name
Test status
Simulation time 1011878577 ps
CPU time 6.49 seconds
Started Nov 22 01:06:40 PM PST 23
Finished Nov 22 01:06:48 PM PST 23
Peak memory 197116 kb
Host smart-dd4fe0f1-c4db-4339-8270-69a0fdff800f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31193498933883877276396155415678012710008663787662666344653871359307358507796 -assert nopo
stproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover
_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_bit_bash.31193498933883877276396155415678012710008663787662666344653871359307358507796
Directory /workspace/1.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.113313885329440434982932832386816092003130704465412572792599287982167514324559
Short name T80
Test name
Test status
Simulation time 30475714 ps
CPU time 0.72 seconds
Started Nov 22 01:06:28 PM PST 23
Finished Nov 22 01:06:31 PM PST 23
Peak memory 194332 kb
Host smart-9a197af8-2467-4b7d-869f-87e4262926f4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113313885329440434982932832386816092003130704465412572792599287982167514324559 -assert nop
ostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_hw_reset.113313885329440434982932832386816092003130704465412572792599287982167514324559
Directory /workspace/1.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.58848671492114131324039589457120365050228042080810098472244035704094929918290
Short name T162
Test name
Test status
Simulation time 129656135129 ps
CPU time 700.58 seconds
Started Nov 22 01:06:23 PM PST 23
Finished Nov 22 01:18:05 PM PST 23
Peak memory 216488 kb
Host smart-b33bcbd9-48bf-492f-a534-d3b01530b9c9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5884867149211413132403958945712036505022804
2080810098472244035704094929918290 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_mem_rw_with_rand_reset.5884867149211413132403958
9457120365050228042080810098472244035704094929918290
Directory /workspace/1.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_rw.55587378774971222786672100439714451819262407696363356948066405063374614963685
Short name T153
Test name
Test status
Simulation time 31297136 ps
CPU time 0.65 seconds
Started Nov 22 01:06:30 PM PST 23
Finished Nov 22 01:06:32 PM PST 23
Peak memory 194900 kb
Host smart-f9fe238e-c261-420c-b5e9-dce2d68bf54c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55587378774971222786672100439714451819262407696363356948066405063374614963685 -assert nopostproc
+UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 1.hmac_csr_rw.55587378774971222786672100439714451819262407696363356948066405063374614963685
Directory /workspace/1.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_intr_test.25931961156590390763214447650067486514655819517304025182524485979809971363230
Short name T877
Test name
Test status
Simulation time 22993631 ps
CPU time 0.58 seconds
Started Nov 22 01:06:31 PM PST 23
Finished Nov 22 01:06:33 PM PST 23
Peak memory 184180 kb
Host smart-85cda0b0-7fd0-4c17-8a47-4bb4387676d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25931961156590390763214447650067486514655819517304025182524485979809971363230 -assert nopostproc +U
VM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 1.hmac_intr_test.25931961156590390763214447650067486514655819517304025182524485979809971363230
Directory /workspace/1.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.26893817074102407386453189960777897384268129906394556574337803124063482700390
Short name T880
Test name
Test status
Simulation time 89028817 ps
CPU time 1.08 seconds
Started Nov 22 01:06:28 PM PST 23
Finished Nov 22 01:06:31 PM PST 23
Peak memory 197568 kb
Host smart-e775526d-fff8-46d2-8c1d-eaddaba61255
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26893817074102407386453189960777897384268129906394556574337803124063482700390
-assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_same_csr_outstanding.26893817074102407386453189960777897384268129906394556574337803124063482700390
Directory /workspace/1.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_errors.83708567248834521380285671635403264707990649198706019663567214146139416788676
Short name T894
Test name
Test status
Simulation time 199170793 ps
CPU time 2.23 seconds
Started Nov 22 01:06:21 PM PST 23
Finished Nov 22 01:06:24 PM PST 23
Peak memory 199088 kb
Host smart-49f734e2-984c-46c4-9c35-19dc38400e10
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83708567248834521380285671635403264707990649198706019663567214146139416788676 -assert nopostproc +U
VM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 1.hmac_tl_errors.83708567248834521380285671635403264707990649198706019663567214146139416788676
Directory /workspace/1.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.38048355777500985777585857482834167224258742096972982325757950316274591521812
Short name T909
Test name
Test status
Simulation time 129656135129 ps
CPU time 677.18 seconds
Started Nov 22 01:06:42 PM PST 23
Finished Nov 22 01:18:04 PM PST 23
Peak memory 216492 kb
Host smart-ca43321f-bf5f-4535-9683-c646c5d84201
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804835577750098577758585748283416722425874
2096972982325757950316274591521812 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_csr_mem_rw_with_rand_reset.380483557775009857775858
57482834167224258742096972982325757950316274591521812
Directory /workspace/10.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_rw.3034747132590464598846507226129572452631066080666324850060337965534160512452
Short name T159
Test name
Test status
Simulation time 31297136 ps
CPU time 0.66 seconds
Started Nov 22 01:06:41 PM PST 23
Finished Nov 22 01:06:43 PM PST 23
Peak memory 194876 kb
Host smart-45d0fed6-eaa2-45a9-ab9c-5f4ed3949bea
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034747132590464598846507226129572452631066080666324850060337965534160512452 -assert nopostproc
+UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 10.hmac_csr_rw.3034747132590464598846507226129572452631066080666324850060337965534160512452
Directory /workspace/10.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_intr_test.81700936131488190676644948534023075211912404901187913562682646409266968359495
Short name T878
Test name
Test status
Simulation time 22993631 ps
CPU time 0.57 seconds
Started Nov 22 01:06:41 PM PST 23
Finished Nov 22 01:06:43 PM PST 23
Peak memory 184204 kb
Host smart-3cc4c50a-e0f2-479d-afbc-7d3489b299c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81700936131488190676644948534023075211912404901187913562682646409266968359495 -assert nopostproc +U
VM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 10.hmac_intr_test.81700936131488190676644948534023075211912404901187913562682646409266968359495
Directory /workspace/10.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.90829830488346250994268754947279653731127026662832499953721990528357582689648
Short name T884
Test name
Test status
Simulation time 89028817 ps
CPU time 1.13 seconds
Started Nov 22 01:06:41 PM PST 23
Finished Nov 22 01:06:43 PM PST 23
Peak memory 197536 kb
Host smart-51f0c29d-b67d-4c4f-9e93-63ac4456756b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90829830488346250994268754947279653731127026662832499953721990528357582689648
-assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_same_csr_outstanding.90829830488346250994268754947279653731127026662832499953721990528357582689648
Directory /workspace/10.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_errors.99677804021461282496042188354171190349289278084620624992294172871868324591761
Short name T168
Test name
Test status
Simulation time 199170793 ps
CPU time 2.3 seconds
Started Nov 22 01:06:40 PM PST 23
Finished Nov 22 01:06:44 PM PST 23
Peak memory 199028 kb
Host smart-9c457e99-54d2-486b-aad4-016d403b4e35
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99677804021461282496042188354171190349289278084620624992294172871868324591761 -assert nopostproc +U
VM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 10.hmac_tl_errors.99677804021461282496042188354171190349289278084620624992294172871868324591761
Directory /workspace/10.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.13288948815939055743176019474442047660928448198464901577058080436125174962256
Short name T33
Test name
Test status
Simulation time 180081660 ps
CPU time 1.85 seconds
Started Nov 22 01:06:41 PM PST 23
Finished Nov 22 01:06:44 PM PST 23
Peak memory 198704 kb
Host smart-04cbb160-bd79-4e77-8b41-c4f698960560
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13288948815939055743176019474442047660928448198464901577058080436125174962256 -assert n
opostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_intg_err.13288948815939055743176019474442047660928448198464901577058080436125174962256
Directory /workspace/10.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.17612620068123257800049959092410402562021007730109714849130459162453755308942
Short name T889
Test name
Test status
Simulation time 129656135129 ps
CPU time 682.39 seconds
Started Nov 22 01:06:42 PM PST 23
Finished Nov 22 01:18:09 PM PST 23
Peak memory 216416 kb
Host smart-fc47107e-c328-419b-bab7-ba02a2ff0ac8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761262006812325780004995909241040256202100
7730109714849130459162453755308942 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_csr_mem_rw_with_rand_reset.176126200681232578000499
59092410402562021007730109714849130459162453755308942
Directory /workspace/11.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_rw.74351767945329824427966920207554084231117766675636635029529428237433917221617
Short name T83
Test name
Test status
Simulation time 31297136 ps
CPU time 0.68 seconds
Started Nov 22 01:06:43 PM PST 23
Finished Nov 22 01:06:48 PM PST 23
Peak memory 194884 kb
Host smart-7426ffe5-136c-4a91-b3cb-f91fd9c9f245
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74351767945329824427966920207554084231117766675636635029529428237433917221617 -assert nopostproc
+UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 11.hmac_csr_rw.74351767945329824427966920207554084231117766675636635029529428237433917221617
Directory /workspace/11.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.71241964086813775902679417706282847686846692900683731143625119854217444930725
Short name T173
Test name
Test status
Simulation time 89028817 ps
CPU time 1.14 seconds
Started Nov 22 01:06:43 PM PST 23
Finished Nov 22 01:06:49 PM PST 23
Peak memory 197536 kb
Host smart-8f25ba4f-e732-4bfb-9000-ce4c57c0f99c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71241964086813775902679417706282847686846692900683731143625119854217444930725
-assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_same_csr_outstanding.71241964086813775902679417706282847686846692900683731143625119854217444930725
Directory /workspace/11.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_errors.22811841081764974259822098476463600260742850854441681143511752419909596267163
Short name T161
Test name
Test status
Simulation time 199170793 ps
CPU time 2.34 seconds
Started Nov 22 01:06:42 PM PST 23
Finished Nov 22 01:06:48 PM PST 23
Peak memory 199012 kb
Host smart-3a32350d-d571-4aff-81f6-b1151997500d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22811841081764974259822098476463600260742850854441681143511752419909596267163 -assert nopostproc +U
VM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 11.hmac_tl_errors.22811841081764974259822098476463600260742850854441681143511752419909596267163
Directory /workspace/11.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.45675748273444092998450721801648259364068725640156305892068804710100445157699
Short name T107
Test name
Test status
Simulation time 180081660 ps
CPU time 1.86 seconds
Started Nov 22 01:06:42 PM PST 23
Finished Nov 22 01:06:49 PM PST 23
Peak memory 198672 kb
Host smart-902920db-a215-4d39-bd21-e657820f316a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45675748273444092998450721801648259364068725640156305892068804710100445157699 -assert n
opostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_intg_err.45675748273444092998450721801648259364068725640156305892068804710100445157699
Directory /workspace/11.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.18714079659344233050835942507533711767928629350147512001262817628256315942405
Short name T903
Test name
Test status
Simulation time 129656135129 ps
CPU time 678.39 seconds
Started Nov 22 01:06:41 PM PST 23
Finished Nov 22 01:18:01 PM PST 23
Peak memory 215792 kb
Host smart-c5d46262-8a9b-4edf-9685-59b27b0a4a1b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871407965934423305083594250753371176792862
9350147512001262817628256315942405 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_csr_mem_rw_with_rand_reset.187140796593442330508359
42507533711767928629350147512001262817628256315942405
Directory /workspace/12.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_rw.110890115851253023677142412094105732522714159762277131314950656824390816330528
Short name T125
Test name
Test status
Simulation time 31297136 ps
CPU time 0.65 seconds
Started Nov 22 01:06:42 PM PST 23
Finished Nov 22 01:06:47 PM PST 23
Peak memory 194844 kb
Host smart-b5f10212-59c1-44ba-bc03-d3a47008776f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110890115851253023677142412094105732522714159762277131314950656824390816330528 -assert nopostpro
c +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 12.hmac_csr_rw.110890115851253023677142412094105732522714159762277131314950656824390816330528
Directory /workspace/12.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_intr_test.87317631350839817860642104404245378877204255435476579976558846356849170446913
Short name T888
Test name
Test status
Simulation time 22993631 ps
CPU time 0.57 seconds
Started Nov 22 01:06:42 PM PST 23
Finished Nov 22 01:06:45 PM PST 23
Peak memory 184244 kb
Host smart-0f83a051-5963-4cec-874a-f3abd42c3d14
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87317631350839817860642104404245378877204255435476579976558846356849170446913 -assert nopostproc +U
VM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 12.hmac_intr_test.87317631350839817860642104404245378877204255435476579976558846356849170446913
Directory /workspace/12.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.96526955328385822213408353813307276600710924799105521272259321121669736393928
Short name T90
Test name
Test status
Simulation time 89028817 ps
CPU time 1.1 seconds
Started Nov 22 01:06:43 PM PST 23
Finished Nov 22 01:06:49 PM PST 23
Peak memory 197536 kb
Host smart-36fa7ee4-f8b7-4a19-a17c-caa190003234
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96526955328385822213408353813307276600710924799105521272259321121669736393928
-assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_same_csr_outstanding.96526955328385822213408353813307276600710924799105521272259321121669736393928
Directory /workspace/12.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_errors.61489422127117747196384420788111139410761499582510961204330683628068254614638
Short name T127
Test name
Test status
Simulation time 199170793 ps
CPU time 2.39 seconds
Started Nov 22 01:06:43 PM PST 23
Finished Nov 22 01:06:50 PM PST 23
Peak memory 199072 kb
Host smart-6e6af255-583a-422b-b216-10402994fc37
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61489422127117747196384420788111139410761499582510961204330683628068254614638 -assert nopostproc +U
VM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 12.hmac_tl_errors.61489422127117747196384420788111139410761499582510961204330683628068254614638
Directory /workspace/12.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.24245164961168011754320988600893153522872108052876404148528223603480290331193
Short name T120
Test name
Test status
Simulation time 180081660 ps
CPU time 1.87 seconds
Started Nov 22 01:06:41 PM PST 23
Finished Nov 22 01:06:44 PM PST 23
Peak memory 198712 kb
Host smart-4dbecde4-d8e7-438e-b6fe-2a64c1981ea9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24245164961168011754320988600893153522872108052876404148528223603480290331193 -assert n
opostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_intg_err.24245164961168011754320988600893153522872108052876404148528223603480290331193
Directory /workspace/12.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.93109712521227807935302619021142306056370231740150449141368665103408020337538
Short name T171
Test name
Test status
Simulation time 129656135129 ps
CPU time 692.39 seconds
Started Nov 22 01:06:43 PM PST 23
Finished Nov 22 01:18:20 PM PST 23
Peak memory 216460 kb
Host smart-6e5900cc-f5ba-405d-9b96-690c51b18778
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9310971252122780793530261902114230605637023
1740150449141368665103408020337538 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_csr_mem_rw_with_rand_reset.931097125212278079353026
19021142306056370231740150449141368665103408020337538
Directory /workspace/13.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_rw.22980721235919745096117843714470358375947777259861465098357382227349409504838
Short name T117
Test name
Test status
Simulation time 31297136 ps
CPU time 0.66 seconds
Started Nov 22 01:06:43 PM PST 23
Finished Nov 22 01:06:48 PM PST 23
Peak memory 194884 kb
Host smart-c4875410-ce38-4e1a-a30f-77b91a6bb8dd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22980721235919745096117843714470358375947777259861465098357382227349409504838 -assert nopostproc
+UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 13.hmac_csr_rw.22980721235919745096117843714470358375947777259861465098357382227349409504838
Directory /workspace/13.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_intr_test.41746418706543951586324699752761362649152983362069734754714644379317817057294
Short name T913
Test name
Test status
Simulation time 22993631 ps
CPU time 0.57 seconds
Started Nov 22 01:06:42 PM PST 23
Finished Nov 22 01:06:45 PM PST 23
Peak memory 184232 kb
Host smart-db97d516-2ffd-4dbc-8a45-ee31bbedc9b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41746418706543951586324699752761362649152983362069734754714644379317817057294 -assert nopostproc +U
VM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 13.hmac_intr_test.41746418706543951586324699752761362649152983362069734754714644379317817057294
Directory /workspace/13.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.23287517197984444320918219362443314730278089041007044448006972226648866733481
Short name T918
Test name
Test status
Simulation time 89028817 ps
CPU time 1.07 seconds
Started Nov 22 01:06:40 PM PST 23
Finished Nov 22 01:06:43 PM PST 23
Peak memory 197568 kb
Host smart-d30040d5-1088-4e4f-a816-3fff64c9eb9b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23287517197984444320918219362443314730278089041007044448006972226648866733481
-assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_same_csr_outstanding.23287517197984444320918219362443314730278089041007044448006972226648866733481
Directory /workspace/13.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_errors.32072926608328802645760489959966738220898978054028171790121471385437625340258
Short name T904
Test name
Test status
Simulation time 199170793 ps
CPU time 2.32 seconds
Started Nov 22 01:06:41 PM PST 23
Finished Nov 22 01:06:44 PM PST 23
Peak memory 199092 kb
Host smart-d624707c-035e-4453-8ee3-2294c4fd9e47
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32072926608328802645760489959966738220898978054028171790121471385437625340258 -assert nopostproc +U
VM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 13.hmac_tl_errors.32072926608328802645760489959966738220898978054028171790121471385437625340258
Directory /workspace/13.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.28901749823526289569321435077314869570964240426950506168021577175910974564388
Short name T132
Test name
Test status
Simulation time 180081660 ps
CPU time 1.81 seconds
Started Nov 22 01:06:41 PM PST 23
Finished Nov 22 01:06:45 PM PST 23
Peak memory 198740 kb
Host smart-2ddeac47-f8b7-4ffe-9648-ccb526941c4c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28901749823526289569321435077314869570964240426950506168021577175910974564388 -assert n
opostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_intg_err.28901749823526289569321435077314869570964240426950506168021577175910974564388
Directory /workspace/13.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.27610880050890054041654026204488132376777562408783556840327557329619002323543
Short name T131
Test name
Test status
Simulation time 129656135129 ps
CPU time 672.73 seconds
Started Nov 22 01:06:37 PM PST 23
Finished Nov 22 01:17:51 PM PST 23
Peak memory 216496 kb
Host smart-1da6ca6e-406f-45a0-bfc6-acea8cb3a990
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761088005089005404165402620448813237677756
2408783556840327557329619002323543 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_csr_mem_rw_with_rand_reset.276108800508900540416540
26204488132376777562408783556840327557329619002323543
Directory /workspace/14.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_rw.100335084978092274238779110661245485595353745500270433671545465808017299522011
Short name T112
Test name
Test status
Simulation time 31297136 ps
CPU time 0.68 seconds
Started Nov 22 01:06:42 PM PST 23
Finished Nov 22 01:06:46 PM PST 23
Peak memory 194440 kb
Host smart-6c74603b-e7b3-49b8-8bec-15f842ebcfb1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100335084978092274238779110661245485595353745500270433671545465808017299522011 -assert nopostpro
c +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 14.hmac_csr_rw.100335084978092274238779110661245485595353745500270433671545465808017299522011
Directory /workspace/14.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_intr_test.3910089613191760431020209421007820991911791174842317522224214513228494894303
Short name T912
Test name
Test status
Simulation time 22993631 ps
CPU time 0.61 seconds
Started Nov 22 01:06:42 PM PST 23
Finished Nov 22 01:06:47 PM PST 23
Peak memory 183840 kb
Host smart-75f5ec73-96ca-4144-8528-a50f91f9ff36
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910089613191760431020209421007820991911791174842317522224214513228494894303 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 14.hmac_intr_test.3910089613191760431020209421007820991911791174842317522224214513228494894303
Directory /workspace/14.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.47174443028499086562163416565461563619406394771897614880256143332375482177147
Short name T164
Test name
Test status
Simulation time 89028817 ps
CPU time 1.08 seconds
Started Nov 22 01:06:40 PM PST 23
Finished Nov 22 01:06:43 PM PST 23
Peak memory 197568 kb
Host smart-23fbc75d-db46-47ee-8459-93de53db400f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47174443028499086562163416565461563619406394771897614880256143332375482177147
-assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_same_csr_outstanding.47174443028499086562163416565461563619406394771897614880256143332375482177147
Directory /workspace/14.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_errors.13548760095553180856367620351997603151809822782866591031028624518262879402530
Short name T29
Test name
Test status
Simulation time 199170793 ps
CPU time 2.31 seconds
Started Nov 22 01:06:41 PM PST 23
Finished Nov 22 01:06:45 PM PST 23
Peak memory 199092 kb
Host smart-00097f5c-886e-41b4-a573-47e115d123a8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13548760095553180856367620351997603151809822782866591031028624518262879402530 -assert nopostproc +U
VM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 14.hmac_tl_errors.13548760095553180856367620351997603151809822782866591031028624518262879402530
Directory /workspace/14.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.108524331911712499576046921556647359018297131646804717596469990474711982548892
Short name T172
Test name
Test status
Simulation time 180081660 ps
CPU time 1.87 seconds
Started Nov 22 01:06:43 PM PST 23
Finished Nov 22 01:06:49 PM PST 23
Peak memory 198708 kb
Host smart-77c0ef6b-e96f-4d66-82de-d3dc5af5e961
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108524331911712499576046921556647359018297131646804717596469990474711982548892 -assert
nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_intg_err.108524331911712499576046921556647359018297131646804717596469990474711982548892
Directory /workspace/14.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.40481883276043203767807588024676102144665094546632362022459173514735629611161
Short name T151
Test name
Test status
Simulation time 129656135129 ps
CPU time 664.29 seconds
Started Nov 22 01:06:49 PM PST 23
Finished Nov 22 01:17:56 PM PST 23
Peak memory 216500 kb
Host smart-eb501af8-fba3-4404-a84e-35eb8cb93cbf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048188327604320376780758802467610214466509
4546632362022459173514735629611161 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_csr_mem_rw_with_rand_reset.404818832760432037678075
88024676102144665094546632362022459173514735629611161
Directory /workspace/15.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_rw.99946355429684851063579150822740350513084560524588447576835654448889448406295
Short name T110
Test name
Test status
Simulation time 31297136 ps
CPU time 0.67 seconds
Started Nov 22 01:06:41 PM PST 23
Finished Nov 22 01:06:44 PM PST 23
Peak memory 194928 kb
Host smart-afdf58dc-fba2-4a9b-8687-d7f41de1bb7b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99946355429684851063579150822740350513084560524588447576835654448889448406295 -assert nopostproc
+UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 15.hmac_csr_rw.99946355429684851063579150822740350513084560524588447576835654448889448406295
Directory /workspace/15.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_intr_test.40537923489459672595628400143976901075368387868630688085993620005488740088863
Short name T22
Test name
Test status
Simulation time 22993631 ps
CPU time 0.57 seconds
Started Nov 22 01:06:42 PM PST 23
Finished Nov 22 01:06:45 PM PST 23
Peak memory 184244 kb
Host smart-dfdca31a-88a2-4585-afe6-b63985d03fd3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40537923489459672595628400143976901075368387868630688085993620005488740088863 -assert nopostproc +U
VM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 15.hmac_intr_test.40537923489459672595628400143976901075368387868630688085993620005488740088863
Directory /workspace/15.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.8575094448883141711748470550108641026532606311234903903978247530380801609655
Short name T93
Test name
Test status
Simulation time 89028817 ps
CPU time 1.07 seconds
Started Nov 22 01:06:46 PM PST 23
Finished Nov 22 01:06:51 PM PST 23
Peak memory 197564 kb
Host smart-4a7579fa-1ba4-477f-add3-57c02fa0ab00
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8575094448883141711748470550108641026532606311234903903978247530380801609655 -
assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_same_csr_outstanding.8575094448883141711748470550108641026532606311234903903978247530380801609655
Directory /workspace/15.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_errors.65448728426426786903129063835885492950199340738891139611499717447260950712711
Short name T113
Test name
Test status
Simulation time 199170793 ps
CPU time 2.3 seconds
Started Nov 22 01:06:42 PM PST 23
Finished Nov 22 01:06:48 PM PST 23
Peak memory 199104 kb
Host smart-b34e6d0a-665f-4ccc-9d92-8bc8adc19a75
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65448728426426786903129063835885492950199340738891139611499717447260950712711 -assert nopostproc +U
VM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 15.hmac_tl_errors.65448728426426786903129063835885492950199340738891139611499717447260950712711
Directory /workspace/15.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.55305911732695706973990004171090937956668603760320846594929500371748187622816
Short name T135
Test name
Test status
Simulation time 180081660 ps
CPU time 1.77 seconds
Started Nov 22 01:06:42 PM PST 23
Finished Nov 22 01:06:46 PM PST 23
Peak memory 198740 kb
Host smart-4c4f6798-c1df-4523-a24f-792347de2848
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55305911732695706973990004171090937956668603760320846594929500371748187622816 -assert n
opostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_intg_err.55305911732695706973990004171090937956668603760320846594929500371748187622816
Directory /workspace/15.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.109534006337744714916444574403365695501637615256798078651365224550960869189865
Short name T895
Test name
Test status
Simulation time 129656135129 ps
CPU time 659.64 seconds
Started Nov 22 01:06:43 PM PST 23
Finished Nov 22 01:17:47 PM PST 23
Peak memory 216500 kb
Host smart-3cbab9b9-41fc-4106-8d71-f2bf92f1c519
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095340063377447149164445744033656955016376
15256798078651365224550960869189865 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_csr_mem_rw_with_rand_reset.10953400633774471491644
4574403365695501637615256798078651365224550960869189865
Directory /workspace/16.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_rw.21161944702584882768320491883466758894860111613517817754009732916613740464703
Short name T116
Test name
Test status
Simulation time 31297136 ps
CPU time 0.67 seconds
Started Nov 22 01:06:58 PM PST 23
Finished Nov 22 01:07:00 PM PST 23
Peak memory 194900 kb
Host smart-7669e636-97ad-4c85-8750-0f48183188b2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21161944702584882768320491883466758894860111613517817754009732916613740464703 -assert nopostproc
+UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 16.hmac_csr_rw.21161944702584882768320491883466758894860111613517817754009732916613740464703
Directory /workspace/16.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_intr_test.91755659324527142307787714103056499981116159193851816703234091374581280935767
Short name T154
Test name
Test status
Simulation time 22993631 ps
CPU time 0.6 seconds
Started Nov 22 01:06:55 PM PST 23
Finished Nov 22 01:06:57 PM PST 23
Peak memory 183916 kb
Host smart-0918c1a0-989d-4726-ade4-f2c5cfef6591
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91755659324527142307787714103056499981116159193851816703234091374581280935767 -assert nopostproc +U
VM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 16.hmac_intr_test.91755659324527142307787714103056499981116159193851816703234091374581280935767
Directory /workspace/16.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.113498546378611276174327894126153020958740409844563976141455772213942689854915
Short name T94
Test name
Test status
Simulation time 89028817 ps
CPU time 1.11 seconds
Started Nov 22 01:06:58 PM PST 23
Finished Nov 22 01:07:00 PM PST 23
Peak memory 197548 kb
Host smart-5ca86b5a-934c-4d27-b172-09ed6c96752a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113498546378611276174327894126153020958740409844563976141455772213942689854915
-assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_same_csr_outstanding.1134985463786112761743278941261530209587404098445639761414557722
13942689854915
Directory /workspace/16.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_errors.63986638103061272423628253304125161449452973576893988081334802047699479795759
Short name T885
Test name
Test status
Simulation time 199170793 ps
CPU time 2.39 seconds
Started Nov 22 01:06:50 PM PST 23
Finished Nov 22 01:06:54 PM PST 23
Peak memory 199112 kb
Host smart-9f02e27b-019c-4535-93ec-49d7057cf25b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63986638103061272423628253304125161449452973576893988081334802047699479795759 -assert nopostproc +U
VM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 16.hmac_tl_errors.63986638103061272423628253304125161449452973576893988081334802047699479795759
Directory /workspace/16.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.63557483601611810368112555170954885662754827530195198487484544553497586389734
Short name T99
Test name
Test status
Simulation time 180081660 ps
CPU time 1.79 seconds
Started Nov 22 01:06:41 PM PST 23
Finished Nov 22 01:06:45 PM PST 23
Peak memory 198712 kb
Host smart-91fcbae3-254e-4086-acf1-b475cfa238ec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63557483601611810368112555170954885662754827530195198487484544553497586389734 -assert n
opostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_intg_err.63557483601611810368112555170954885662754827530195198487484544553497586389734
Directory /workspace/16.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.21239614965266668912457518355531445911201708877264513071347355437025570291995
Short name T911
Test name
Test status
Simulation time 129656135129 ps
CPU time 681.25 seconds
Started Nov 22 01:06:58 PM PST 23
Finished Nov 22 01:18:20 PM PST 23
Peak memory 216476 kb
Host smart-2d1fdd04-eea0-4a2f-814d-53568b78134b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123961496526666891245751835553144591120170
8877264513071347355437025570291995 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_csr_mem_rw_with_rand_reset.212396149652666689124575
18355531445911201708877264513071347355437025570291995
Directory /workspace/17.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_rw.18988652545367393329786271264028103006196201115092075167928309439810126798437
Short name T914
Test name
Test status
Simulation time 31297136 ps
CPU time 0.66 seconds
Started Nov 22 01:06:50 PM PST 23
Finished Nov 22 01:06:52 PM PST 23
Peak memory 194924 kb
Host smart-0960ded2-be4f-44e6-bb36-c566ce56a0f0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18988652545367393329786271264028103006196201115092075167928309439810126798437 -assert nopostproc
+UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 17.hmac_csr_rw.18988652545367393329786271264028103006196201115092075167928309439810126798437
Directory /workspace/17.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_intr_test.84413456789662227847026004912010631807600057022462362944075393376320038471996
Short name T157
Test name
Test status
Simulation time 22993631 ps
CPU time 0.56 seconds
Started Nov 22 01:06:35 PM PST 23
Finished Nov 22 01:06:37 PM PST 23
Peak memory 184212 kb
Host smart-6570062a-fc6e-4e03-bffd-182263093c64
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84413456789662227847026004912010631807600057022462362944075393376320038471996 -assert nopostproc +U
VM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 17.hmac_intr_test.84413456789662227847026004912010631807600057022462362944075393376320038471996
Directory /workspace/17.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.11833040375516702010314075432040228137357796672566361472830877755710805647731
Short name T907
Test name
Test status
Simulation time 89028817 ps
CPU time 1.12 seconds
Started Nov 22 01:06:42 PM PST 23
Finished Nov 22 01:06:48 PM PST 23
Peak memory 197508 kb
Host smart-e2d00b0c-d919-4be3-800f-7f073d95fca8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11833040375516702010314075432040228137357796672566361472830877755710805647731
-assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_same_csr_outstanding.11833040375516702010314075432040228137357796672566361472830877755710805647731
Directory /workspace/17.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_errors.62853808191635073952250422869880615396548131859047660937687151051115038775062
Short name T126
Test name
Test status
Simulation time 199170793 ps
CPU time 2.38 seconds
Started Nov 22 01:06:55 PM PST 23
Finished Nov 22 01:06:59 PM PST 23
Peak memory 198952 kb
Host smart-ec750d24-d6a4-48c5-984f-87095ceb9a4b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62853808191635073952250422869880615396548131859047660937687151051115038775062 -assert nopostproc +U
VM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 17.hmac_tl_errors.62853808191635073952250422869880615396548131859047660937687151051115038775062
Directory /workspace/17.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.12875678757631204897718996303418777052631525454426968764640115436120508773828
Short name T74
Test name
Test status
Simulation time 180081660 ps
CPU time 1.83 seconds
Started Nov 22 01:06:58 PM PST 23
Finished Nov 22 01:07:01 PM PST 23
Peak memory 198724 kb
Host smart-065dad8c-7a28-4f15-a956-c223fba19a17
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12875678757631204897718996303418777052631525454426968764640115436120508773828 -assert n
opostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_intg_err.12875678757631204897718996303418777052631525454426968764640115436120508773828
Directory /workspace/17.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.54343117031482638873858551326053437550404978492252907834480977991533363872269
Short name T115
Test name
Test status
Simulation time 129656135129 ps
CPU time 672.59 seconds
Started Nov 22 01:06:46 PM PST 23
Finished Nov 22 01:18:03 PM PST 23
Peak memory 216484 kb
Host smart-6e1b82c0-b15f-4543-b49d-bec89fcb4ffd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5434311703148263887385855132605343755040497
8492252907834480977991533363872269 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_csr_mem_rw_with_rand_reset.543431170314826388738585
51326053437550404978492252907834480977991533363872269
Directory /workspace/18.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_rw.83105904716457380720610233714569105737724192328723707571722851376561496107734
Short name T145
Test name
Test status
Simulation time 31297136 ps
CPU time 0.67 seconds
Started Nov 22 01:06:43 PM PST 23
Finished Nov 22 01:06:48 PM PST 23
Peak memory 194920 kb
Host smart-cdda4146-5f89-4b19-af27-2ad9e22e4c9e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83105904716457380720610233714569105737724192328723707571722851376561496107734 -assert nopostproc
+UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 18.hmac_csr_rw.83105904716457380720610233714569105737724192328723707571722851376561496107734
Directory /workspace/18.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_intr_test.38293231093607581866541913040224021552677772692281671152508972776413597482265
Short name T163
Test name
Test status
Simulation time 22993631 ps
CPU time 0.56 seconds
Started Nov 22 01:06:47 PM PST 23
Finished Nov 22 01:06:51 PM PST 23
Peak memory 184224 kb
Host smart-97fb0c0d-6a3b-459c-921a-8e25c4e1a548
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38293231093607581866541913040224021552677772692281671152508972776413597482265 -assert nopostproc +U
VM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 18.hmac_intr_test.38293231093607581866541913040224021552677772692281671152508972776413597482265
Directory /workspace/18.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.41043734202465201721992828192696860426034806158324202657842493717871268435506
Short name T881
Test name
Test status
Simulation time 89028817 ps
CPU time 1.1 seconds
Started Nov 22 01:06:43 PM PST 23
Finished Nov 22 01:06:49 PM PST 23
Peak memory 197552 kb
Host smart-93cfe2d8-8022-4b88-9bc3-a6530dcc5038
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41043734202465201721992828192696860426034806158324202657842493717871268435506
-assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_same_csr_outstanding.41043734202465201721992828192696860426034806158324202657842493717871268435506
Directory /workspace/18.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_errors.4505894984486564758155068980449017221114232888669639725649161564173233168596
Short name T26
Test name
Test status
Simulation time 199170793 ps
CPU time 2.34 seconds
Started Nov 22 01:06:46 PM PST 23
Finished Nov 22 01:06:52 PM PST 23
Peak memory 199076 kb
Host smart-3243549a-0d89-48ec-b1ff-79517f8591f0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4505894984486564758155068980449017221114232888669639725649161564173233168596 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 18.hmac_tl_errors.4505894984486564758155068980449017221114232888669639725649161564173233168596
Directory /workspace/18.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.581660504097190646803805270510646871206849055984831862246618240818771862198
Short name T76
Test name
Test status
Simulation time 180081660 ps
CPU time 1.87 seconds
Started Nov 22 01:06:40 PM PST 23
Finished Nov 22 01:06:43 PM PST 23
Peak memory 198724 kb
Host smart-785dbb11-d105-4915-8cac-fafbae42157f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581660504097190646803805270510646871206849055984831862246618240818771862198 -assert nop
ostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_intg_err.581660504097190646803805270510646871206849055984831862246618240818771862198
Directory /workspace/18.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.32152690651486552866211658954023560545071883365416763625487285123877299801337
Short name T890
Test name
Test status
Simulation time 129656135129 ps
CPU time 673.45 seconds
Started Nov 22 01:06:39 PM PST 23
Finished Nov 22 01:17:54 PM PST 23
Peak memory 216492 kb
Host smart-dbed8e84-a00e-489b-afcf-f796ea76cfdb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215269065148655286621165895402356054507188
3365416763625487285123877299801337 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_csr_mem_rw_with_rand_reset.321526906514865528662116
58954023560545071883365416763625487285123877299801337
Directory /workspace/19.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_rw.20530752661342750277268448170658287632617491528212077187763857155577906325832
Short name T82
Test name
Test status
Simulation time 31297136 ps
CPU time 0.71 seconds
Started Nov 22 01:06:49 PM PST 23
Finished Nov 22 01:06:52 PM PST 23
Peak memory 194924 kb
Host smart-7314e175-abae-491b-89f4-c8d31527a267
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20530752661342750277268448170658287632617491528212077187763857155577906325832 -assert nopostproc
+UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 19.hmac_csr_rw.20530752661342750277268448170658287632617491528212077187763857155577906325832
Directory /workspace/19.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_intr_test.78556303629642514284435528113631193445865216413203253069065823973369683399482
Short name T167
Test name
Test status
Simulation time 22993631 ps
CPU time 0.62 seconds
Started Nov 22 01:06:43 PM PST 23
Finished Nov 22 01:06:48 PM PST 23
Peak memory 184224 kb
Host smart-c0550d05-e955-42f8-85bb-025e2f78bc12
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78556303629642514284435528113631193445865216413203253069065823973369683399482 -assert nopostproc +U
VM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 19.hmac_intr_test.78556303629642514284435528113631193445865216413203253069065823973369683399482
Directory /workspace/19.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.12382214882284997806121175450943881612043256282312158682517299394224459824942
Short name T899
Test name
Test status
Simulation time 89028817 ps
CPU time 1.12 seconds
Started Nov 22 01:06:55 PM PST 23
Finished Nov 22 01:06:57 PM PST 23
Peak memory 197472 kb
Host smart-7a61dcae-04ac-4672-b253-b8058526bda4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12382214882284997806121175450943881612043256282312158682517299394224459824942
-assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_same_csr_outstanding.12382214882284997806121175450943881612043256282312158682517299394224459824942
Directory /workspace/19.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_errors.74127166071153333473430504250668032285485485070675878632115026208434849205430
Short name T31
Test name
Test status
Simulation time 199170793 ps
CPU time 2.37 seconds
Started Nov 22 01:06:55 PM PST 23
Finished Nov 22 01:06:59 PM PST 23
Peak memory 198872 kb
Host smart-7ecbff70-a33d-4290-96bb-9cc0a62126a7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74127166071153333473430504250668032285485485070675878632115026208434849205430 -assert nopostproc +U
VM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 19.hmac_tl_errors.74127166071153333473430504250668032285485485070675878632115026208434849205430
Directory /workspace/19.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.34448714341619221200768863348855884127922300900685856453714992462075761736313
Short name T166
Test name
Test status
Simulation time 180081660 ps
CPU time 1.8 seconds
Started Nov 22 01:06:50 PM PST 23
Finished Nov 22 01:06:54 PM PST 23
Peak memory 198748 kb
Host smart-b7d67205-a4d8-4392-865a-6c188ed5b6a7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34448714341619221200768863348855884127922300900685856453714992462075761736313 -assert n
opostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_intg_err.34448714341619221200768863348855884127922300900685856453714992462075761736313
Directory /workspace/19.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.89808704602706346209844696571183940932018438927249097902596678584645618150186
Short name T85
Test name
Test status
Simulation time 179635235 ps
CPU time 1.92 seconds
Started Nov 22 01:06:32 PM PST 23
Finished Nov 22 01:06:34 PM PST 23
Peak memory 196960 kb
Host smart-519dde91-f8e1-42d2-8873-b288f38acc76
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89808704602706346209844696571183940932018438927249097902596678584645618150186 -assert nopo
stproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover
_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_aliasing.89808704602706346209844696571183940932018438927249097902596678584645618150186
Directory /workspace/2.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.17017355986891773472968567230452852710380511208434209982366452619128953994076
Short name T79
Test name
Test status
Simulation time 1011878577 ps
CPU time 6.23 seconds
Started Nov 22 01:06:36 PM PST 23
Finished Nov 22 01:06:44 PM PST 23
Peak memory 197088 kb
Host smart-4152fa94-7466-4226-952e-1a8bc0073e19
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17017355986891773472968567230452852710380511208434209982366452619128953994076 -assert nopo
stproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover
_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_bit_bash.17017355986891773472968567230452852710380511208434209982366452619128953994076
Directory /workspace/2.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.30581085965811784085054952960314696864118308158096964871366657794216236823343
Short name T140
Test name
Test status
Simulation time 30475714 ps
CPU time 0.64 seconds
Started Nov 22 01:06:29 PM PST 23
Finished Nov 22 01:06:31 PM PST 23
Peak memory 194300 kb
Host smart-032f3a41-6d0a-4751-800c-36ca80e324ff
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30581085965811784085054952960314696864118308158096964871366657794216236823343 -assert nopo
stproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover
_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_hw_reset.30581085965811784085054952960314696864118308158096964871366657794216236823343
Directory /workspace/2.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.47162709958818837125449277027172766892106174717301487188822260338454325090291
Short name T910
Test name
Test status
Simulation time 129656135129 ps
CPU time 656.2 seconds
Started Nov 22 01:06:26 PM PST 23
Finished Nov 22 01:17:24 PM PST 23
Peak memory 216412 kb
Host smart-ae5a1b0b-d21b-488b-9fb3-28d2c92719bf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4716270995881883712544927702717276689210617
4717301487188822260338454325090291 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_mem_rw_with_rand_reset.4716270995881883712544927
7027172766892106174717301487188822260338454325090291
Directory /workspace/2.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_rw.83864831326373488969992581051813039995678624328355177472188133768447415476159
Short name T81
Test name
Test status
Simulation time 31297136 ps
CPU time 0.65 seconds
Started Nov 22 01:06:28 PM PST 23
Finished Nov 22 01:06:30 PM PST 23
Peak memory 194932 kb
Host smart-1c44c395-bd4c-4a37-aaa9-0383cd0fd2ce
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83864831326373488969992581051813039995678624328355177472188133768447415476159 -assert nopostproc
+UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 2.hmac_csr_rw.83864831326373488969992581051813039995678624328355177472188133768447415476159
Directory /workspace/2.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_intr_test.32472157335663882202506620541043277570325103670801798632885544126555544566465
Short name T920
Test name
Test status
Simulation time 22993631 ps
CPU time 0.59 seconds
Started Nov 22 01:06:33 PM PST 23
Finished Nov 22 01:06:34 PM PST 23
Peak memory 184076 kb
Host smart-1a344aa7-8c8e-442e-9a0d-ffd2afc86872
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32472157335663882202506620541043277570325103670801798632885544126555544566465 -assert nopostproc +U
VM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 2.hmac_intr_test.32472157335663882202506620541043277570325103670801798632885544126555544566465
Directory /workspace/2.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.84424713292672529413196878521813886012858172755189631264715617085425240246892
Short name T88
Test name
Test status
Simulation time 89028817 ps
CPU time 1.09 seconds
Started Nov 22 01:06:21 PM PST 23
Finished Nov 22 01:06:23 PM PST 23
Peak memory 197544 kb
Host smart-025a9cdf-94c4-40f6-9cda-ad2ca47a6054
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84424713292672529413196878521813886012858172755189631264715617085425240246892
-assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_same_csr_outstanding.84424713292672529413196878521813886012858172755189631264715617085425240246892
Directory /workspace/2.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_errors.69114806898031137120510992005215155774175123229103235871294892178916457549212
Short name T915
Test name
Test status
Simulation time 199170793 ps
CPU time 2.35 seconds
Started Nov 22 01:06:31 PM PST 23
Finished Nov 22 01:06:35 PM PST 23
Peak memory 199040 kb
Host smart-743b5867-a361-4479-b6a5-be8559e357bc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69114806898031137120510992005215155774175123229103235871294892178916457549212 -assert nopostproc +U
VM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 2.hmac_tl_errors.69114806898031137120510992005215155774175123229103235871294892178916457549212
Directory /workspace/2.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.99767160183919688201653005671313220096941583178253824786474551585402419155425
Short name T133
Test name
Test status
Simulation time 180081660 ps
CPU time 1.8 seconds
Started Nov 22 01:06:20 PM PST 23
Finished Nov 22 01:06:23 PM PST 23
Peak memory 198684 kb
Host smart-97dba31e-946a-4b51-b01e-b25981ee0a4a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99767160183919688201653005671313220096941583178253824786474551585402419155425 -assert n
opostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_intg_err.99767160183919688201653005671313220096941583178253824786474551585402419155425
Directory /workspace/2.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.hmac_intr_test.87464415344060716390248587405001711424328013497325189083566639998829290340423
Short name T102
Test name
Test status
Simulation time 22993631 ps
CPU time 0.57 seconds
Started Nov 22 01:06:38 PM PST 23
Finished Nov 22 01:06:41 PM PST 23
Peak memory 184228 kb
Host smart-cc346a91-515a-4bcd-8240-4a778d8840c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87464415344060716390248587405001711424328013497325189083566639998829290340423 -assert nopostproc +U
VM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 20.hmac_intr_test.87464415344060716390248587405001711424328013497325189083566639998829290340423
Directory /workspace/20.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.hmac_intr_test.44807618878180178850648844788069161960014903539004416388285197730753236367283
Short name T900
Test name
Test status
Simulation time 22993631 ps
CPU time 0.57 seconds
Started Nov 22 01:06:58 PM PST 23
Finished Nov 22 01:07:00 PM PST 23
Peak memory 184228 kb
Host smart-5274cba6-1b5f-4ee5-8067-e8eee258bb9e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44807618878180178850648844788069161960014903539004416388285197730753236367283 -assert nopostproc +U
VM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 21.hmac_intr_test.44807618878180178850648844788069161960014903539004416388285197730753236367283
Directory /workspace/21.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.hmac_intr_test.81717930575903690284770462188287801590860856658852094822847432435673919029174
Short name T147
Test name
Test status
Simulation time 22993631 ps
CPU time 0.56 seconds
Started Nov 22 01:06:35 PM PST 23
Finished Nov 22 01:06:36 PM PST 23
Peak memory 184212 kb
Host smart-b9444433-55f7-49c3-a91f-d846b432592d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81717930575903690284770462188287801590860856658852094822847432435673919029174 -assert nopostproc +U
VM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 22.hmac_intr_test.81717930575903690284770462188287801590860856658852094822847432435673919029174
Directory /workspace/22.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.hmac_intr_test.102755931660159191108866666244282354636211544265974990651916355406378623948439
Short name T916
Test name
Test status
Simulation time 22993631 ps
CPU time 0.58 seconds
Started Nov 22 01:06:43 PM PST 23
Finished Nov 22 01:06:48 PM PST 23
Peak memory 184232 kb
Host smart-911c3b03-02b0-4afc-8644-d1c709fd6474
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102755931660159191108866666244282354636211544265974990651916355406378623948439 -assert nopostproc +
UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 23.hmac_intr_test.102755931660159191108866666244282354636211544265974990651916355406378623948439
Directory /workspace/23.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.hmac_intr_test.96693795500402805279583244628212523287770735913101873224967817369355493809403
Short name T156
Test name
Test status
Simulation time 22993631 ps
CPU time 0.57 seconds
Started Nov 22 01:06:42 PM PST 23
Finished Nov 22 01:06:47 PM PST 23
Peak memory 184232 kb
Host smart-cffb0955-2278-4747-88b1-47855f2189a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96693795500402805279583244628212523287770735913101873224967817369355493809403 -assert nopostproc +U
VM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 24.hmac_intr_test.96693795500402805279583244628212523287770735913101873224967817369355493809403
Directory /workspace/24.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.hmac_intr_test.46386794056434096085277977195083114896771241010873639401005150745601055626057
Short name T109
Test name
Test status
Simulation time 22993631 ps
CPU time 0.58 seconds
Started Nov 22 01:06:42 PM PST 23
Finished Nov 22 01:06:46 PM PST 23
Peak memory 184224 kb
Host smart-b448c184-cfa9-4e50-add4-3c4315fed363
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46386794056434096085277977195083114896771241010873639401005150745601055626057 -assert nopostproc +U
VM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 25.hmac_intr_test.46386794056434096085277977195083114896771241010873639401005150745601055626057
Directory /workspace/25.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.hmac_intr_test.17013352821696429655026163866633664839403336627626798495287769977905890464428
Short name T883
Test name
Test status
Simulation time 22993631 ps
CPU time 0.57 seconds
Started Nov 22 01:06:49 PM PST 23
Finished Nov 22 01:06:52 PM PST 23
Peak memory 184252 kb
Host smart-dec7efc3-6ead-4727-8414-8ab0dc81fa87
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17013352821696429655026163866633664839403336627626798495287769977905890464428 -assert nopostproc +U
VM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 26.hmac_intr_test.17013352821696429655026163866633664839403336627626798495287769977905890464428
Directory /workspace/26.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.hmac_intr_test.4920424663731858451489967598374762835055743447560496232739433277125054722099
Short name T917
Test name
Test status
Simulation time 22993631 ps
CPU time 0.64 seconds
Started Nov 22 01:06:58 PM PST 23
Finished Nov 22 01:07:00 PM PST 23
Peak memory 183860 kb
Host smart-54a589f2-e1b9-4b76-ac65-dc54cb8cb8e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4920424663731858451489967598374762835055743447560496232739433277125054722099 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 27.hmac_intr_test.4920424663731858451489967598374762835055743447560496232739433277125054722099
Directory /workspace/27.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.hmac_intr_test.86844600097882575029090849270384061652279732730912370417205265885842904717058
Short name T170
Test name
Test status
Simulation time 22993631 ps
CPU time 0.57 seconds
Started Nov 22 01:06:55 PM PST 23
Finished Nov 22 01:06:57 PM PST 23
Peak memory 184136 kb
Host smart-e9cf8575-426d-4f63-ac6d-e523d45ae78c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86844600097882575029090849270384061652279732730912370417205265885842904717058 -assert nopostproc +U
VM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 28.hmac_intr_test.86844600097882575029090849270384061652279732730912370417205265885842904717058
Directory /workspace/28.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.hmac_intr_test.73823800018664197289098116072370697952556679255857377714195214027101191510909
Short name T24
Test name
Test status
Simulation time 22993631 ps
CPU time 0.55 seconds
Started Nov 22 01:06:48 PM PST 23
Finished Nov 22 01:06:52 PM PST 23
Peak memory 184252 kb
Host smart-9de72695-a22d-4980-8568-184b989fd1b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73823800018664197289098116072370697952556679255857377714195214027101191510909 -assert nopostproc +U
VM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 29.hmac_intr_test.73823800018664197289098116072370697952556679255857377714195214027101191510909
Directory /workspace/29.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.78837175227878547048422945022936905569363543098786998400667031662385297531804
Short name T78
Test name
Test status
Simulation time 179635235 ps
CPU time 1.87 seconds
Started Nov 22 01:06:30 PM PST 23
Finished Nov 22 01:06:33 PM PST 23
Peak memory 196948 kb
Host smart-f42eac09-65d5-4d2d-938c-0aad23fd660d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78837175227878547048422945022936905569363543098786998400667031662385297531804 -assert nopo
stproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover
_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_aliasing.78837175227878547048422945022936905569363543098786998400667031662385297531804
Directory /workspace/3.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.6113098200838362250190509673578634329156872229113644391265288951371843516609
Short name T105
Test name
Test status
Simulation time 30475714 ps
CPU time 0.64 seconds
Started Nov 22 01:06:27 PM PST 23
Finished Nov 22 01:06:29 PM PST 23
Peak memory 194196 kb
Host smart-7642f033-9d55-48b4-b187-082bda65ccd0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6113098200838362250190509673578634329156872229113644391265288951371843516609 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_hw_reset.6113098200838362250190509673578634329156872229113644391265288951371843516609
Directory /workspace/3.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.24898436190713502121777643079420186093840073249472737513481537627707875615102
Short name T901
Test name
Test status
Simulation time 129656135129 ps
CPU time 651.36 seconds
Started Nov 22 01:06:24 PM PST 23
Finished Nov 22 01:17:16 PM PST 23
Peak memory 216468 kb
Host smart-c0ae0f7e-ac65-44b1-bab7-cf9c4b705ccf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489843619071350212177764307942018609384007
3249472737513481537627707875615102 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_mem_rw_with_rand_reset.2489843619071350212177764
3079420186093840073249472737513481537627707875615102
Directory /workspace/3.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_rw.41397559468463320675917716137449926841936442304132958089481577723355398317482
Short name T84
Test name
Test status
Simulation time 31297136 ps
CPU time 0.66 seconds
Started Nov 22 01:06:30 PM PST 23
Finished Nov 22 01:06:32 PM PST 23
Peak memory 194900 kb
Host smart-2024ada4-9e35-4238-8d9e-03185b3b60b7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41397559468463320675917716137449926841936442304132958089481577723355398317482 -assert nopostproc
+UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 3.hmac_csr_rw.41397559468463320675917716137449926841936442304132958089481577723355398317482
Directory /workspace/3.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_intr_test.55561582072620436045940390845748204169990013408256899883178789681423075450960
Short name T908
Test name
Test status
Simulation time 22993631 ps
CPU time 0.62 seconds
Started Nov 22 01:06:33 PM PST 23
Finished Nov 22 01:06:34 PM PST 23
Peak memory 184228 kb
Host smart-2c99346d-0059-4606-9b2d-a89778f1a6c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55561582072620436045940390845748204169990013408256899883178789681423075450960 -assert nopostproc +U
VM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 3.hmac_intr_test.55561582072620436045940390845748204169990013408256899883178789681423075450960
Directory /workspace/3.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.55817141269984375213221907095157861611704814565992955706405425537282771627328
Short name T86
Test name
Test status
Simulation time 89028817 ps
CPU time 1.05 seconds
Started Nov 22 01:06:30 PM PST 23
Finished Nov 22 01:06:32 PM PST 23
Peak memory 197544 kb
Host smart-60d7d5d3-047c-4918-868e-6f2ade54be71
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55817141269984375213221907095157861611704814565992955706405425537282771627328
-assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_same_csr_outstanding.55817141269984375213221907095157861611704814565992955706405425537282771627328
Directory /workspace/3.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_errors.115457360726958552570616821333368316740605944976810989909120772474183490384804
Short name T18
Test name
Test status
Simulation time 199170793 ps
CPU time 2.29 seconds
Started Nov 22 01:06:24 PM PST 23
Finished Nov 22 01:06:27 PM PST 23
Peak memory 198948 kb
Host smart-534c86f3-9c88-4d38-8892-083441c6a23e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115457360726958552570616821333368316740605944976810989909120772474183490384804 -assert nopostproc +
UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.hmac_tl_errors.115457360726958552570616821333368316740605944976810989909120772474183490384804
Directory /workspace/3.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.4833163901072796803959723543368034060288244216259143579482046182354071926179
Short name T146
Test name
Test status
Simulation time 180081660 ps
CPU time 1.8 seconds
Started Nov 22 01:06:24 PM PST 23
Finished Nov 22 01:06:26 PM PST 23
Peak memory 198700 kb
Host smart-b5f257f4-c26e-481e-874e-00cd9cd45dd2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4833163901072796803959723543368034060288244216259143579482046182354071926179 -assert no
postproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_intg_err.4833163901072796803959723543368034060288244216259143579482046182354071926179
Directory /workspace/3.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.hmac_intr_test.10400263992799033764921854762607298596732079578131159500432485978206219407317
Short name T148
Test name
Test status
Simulation time 22993631 ps
CPU time 0.58 seconds
Started Nov 22 01:06:58 PM PST 23
Finished Nov 22 01:07:00 PM PST 23
Peak memory 184228 kb
Host smart-ec144195-7820-4e70-a915-abd5f6c165ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10400263992799033764921854762607298596732079578131159500432485978206219407317 -assert nopostproc +U
VM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 30.hmac_intr_test.10400263992799033764921854762607298596732079578131159500432485978206219407317
Directory /workspace/30.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.hmac_intr_test.32475122038178172635556639427223766021067844683839706274009358743620484541603
Short name T906
Test name
Test status
Simulation time 22993631 ps
CPU time 0.55 seconds
Started Nov 22 01:06:47 PM PST 23
Finished Nov 22 01:06:51 PM PST 23
Peak memory 184224 kb
Host smart-bd30e54f-9fd6-40f7-b19e-338a7e13540a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32475122038178172635556639427223766021067844683839706274009358743620484541603 -assert nopostproc +U
VM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 31.hmac_intr_test.32475122038178172635556639427223766021067844683839706274009358743620484541603
Directory /workspace/31.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.hmac_intr_test.78265541163376163701008754244647614859168071314648691155777183145057205023912
Short name T152
Test name
Test status
Simulation time 22993631 ps
CPU time 0.57 seconds
Started Nov 22 01:06:55 PM PST 23
Finished Nov 22 01:06:56 PM PST 23
Peak memory 184136 kb
Host smart-1a3f47aa-95af-41ac-a69e-82b6fa4282bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78265541163376163701008754244647614859168071314648691155777183145057205023912 -assert nopostproc +U
VM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 32.hmac_intr_test.78265541163376163701008754244647614859168071314648691155777183145057205023912
Directory /workspace/32.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.hmac_intr_test.61966480491780168278358661242002438362425926616202727646187250139369404994378
Short name T138
Test name
Test status
Simulation time 22993631 ps
CPU time 0.56 seconds
Started Nov 22 01:06:55 PM PST 23
Finished Nov 22 01:06:56 PM PST 23
Peak memory 184136 kb
Host smart-cd3a7a9f-963e-4871-a336-396b8a139112
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61966480491780168278358661242002438362425926616202727646187250139369404994378 -assert nopostproc +U
VM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 33.hmac_intr_test.61966480491780168278358661242002438362425926616202727646187250139369404994378
Directory /workspace/33.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.hmac_intr_test.61095235772738813745725409067649527736703520764462339488731833529414742331443
Short name T165
Test name
Test status
Simulation time 22993631 ps
CPU time 0.64 seconds
Started Nov 22 01:06:58 PM PST 23
Finished Nov 22 01:07:00 PM PST 23
Peak memory 183800 kb
Host smart-e1f5661a-d5f7-42a8-91ad-77b300e0a9f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61095235772738813745725409067649527736703520764462339488731833529414742331443 -assert nopostproc +U
VM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 34.hmac_intr_test.61095235772738813745725409067649527736703520764462339488731833529414742331443
Directory /workspace/34.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.hmac_intr_test.51955662355113237793412118261745437059377675702903386129826320148659322626512
Short name T879
Test name
Test status
Simulation time 22993631 ps
CPU time 0.6 seconds
Started Nov 22 01:06:46 PM PST 23
Finished Nov 22 01:06:51 PM PST 23
Peak memory 184224 kb
Host smart-13cea8cd-350c-40a1-a40f-ee49f6a53b13
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51955662355113237793412118261745437059377675702903386129826320148659322626512 -assert nopostproc +U
VM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 35.hmac_intr_test.51955662355113237793412118261745437059377675702903386129826320148659322626512
Directory /workspace/35.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.hmac_intr_test.105373550734081361564803896744987721909248822361492108923111487684970996606909
Short name T919
Test name
Test status
Simulation time 22993631 ps
CPU time 0.56 seconds
Started Nov 22 01:06:46 PM PST 23
Finished Nov 22 01:06:50 PM PST 23
Peak memory 184232 kb
Host smart-064498cf-531e-4a9b-89c9-65c4f6084935
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105373550734081361564803896744987721909248822361492108923111487684970996606909 -assert nopostproc +
UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 36.hmac_intr_test.105373550734081361564803896744987721909248822361492108923111487684970996606909
Directory /workspace/36.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.hmac_intr_test.91776536764174432437800811685682144950890414502312084142965504871895134648751
Short name T104
Test name
Test status
Simulation time 22993631 ps
CPU time 0.57 seconds
Started Nov 22 01:06:36 PM PST 23
Finished Nov 22 01:06:38 PM PST 23
Peak memory 184228 kb
Host smart-4355fb38-ff95-47a9-a715-e0b7a87d25e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91776536764174432437800811685682144950890414502312084142965504871895134648751 -assert nopostproc +U
VM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 37.hmac_intr_test.91776536764174432437800811685682144950890414502312084142965504871895134648751
Directory /workspace/37.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.hmac_intr_test.58683621912723564365930045130989564564812771378544582171447602281200291167088
Short name T130
Test name
Test status
Simulation time 22993631 ps
CPU time 0.59 seconds
Started Nov 22 01:06:39 PM PST 23
Finished Nov 22 01:06:41 PM PST 23
Peak memory 184108 kb
Host smart-91766cb5-baa8-4fe0-95d9-9862501014bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58683621912723564365930045130989564564812771378544582171447602281200291167088 -assert nopostproc +U
VM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 38.hmac_intr_test.58683621912723564365930045130989564564812771378544582171447602281200291167088
Directory /workspace/38.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.hmac_intr_test.4076554295805034570138443313848293384965190481366675538232689440484550101415
Short name T103
Test name
Test status
Simulation time 22993631 ps
CPU time 0.57 seconds
Started Nov 22 01:06:50 PM PST 23
Finished Nov 22 01:06:53 PM PST 23
Peak memory 184252 kb
Host smart-d01af200-1901-4579-8695-693377acf77a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076554295805034570138443313848293384965190481366675538232689440484550101415 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 39.hmac_intr_test.4076554295805034570138443313848293384965190481366675538232689440484550101415
Directory /workspace/39.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.37086170603258210063105700876018483988333653710620673597472897725867019203513
Short name T892
Test name
Test status
Simulation time 179635235 ps
CPU time 1.92 seconds
Started Nov 22 01:06:39 PM PST 23
Finished Nov 22 01:06:43 PM PST 23
Peak memory 197000 kb
Host smart-7de456a2-9d44-4e08-8b1e-2fe262a31680
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37086170603258210063105700876018483988333653710620673597472897725867019203513 -assert nopo
stproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover
_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_aliasing.37086170603258210063105700876018483988333653710620673597472897725867019203513
Directory /workspace/4.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.31983765050479704457105947290596920270433794920187916965642845579974301564955
Short name T111
Test name
Test status
Simulation time 1011878577 ps
CPU time 6.39 seconds
Started Nov 22 01:06:36 PM PST 23
Finished Nov 22 01:06:44 PM PST 23
Peak memory 197168 kb
Host smart-6cb9e844-b472-44be-a7a7-9517ebaf272b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31983765050479704457105947290596920270433794920187916965642845579974301564955 -assert nopo
stproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover
_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_bit_bash.31983765050479704457105947290596920270433794920187916965642845579974301564955
Directory /workspace/4.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.81661343574666248618400073118230060435123171220685142523681130923941402464321
Short name T58
Test name
Test status
Simulation time 30475714 ps
CPU time 0.65 seconds
Started Nov 22 01:06:36 PM PST 23
Finished Nov 22 01:06:38 PM PST 23
Peak memory 194208 kb
Host smart-69b7f413-a311-46f8-bc9f-0bdd4a1dec9e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81661343574666248618400073118230060435123171220685142523681130923941402464321 -assert nopo
stproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover
_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_hw_reset.81661343574666248618400073118230060435123171220685142523681130923941402464321
Directory /workspace/4.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.94949567933642286948781882808488666167577100574265866207458775779331401221450
Short name T30
Test name
Test status
Simulation time 129656135129 ps
CPU time 676.74 seconds
Started Nov 22 01:06:36 PM PST 23
Finished Nov 22 01:17:54 PM PST 23
Peak memory 216364 kb
Host smart-a260a9ec-0698-46a3-a9cd-68fbd05ccee9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9494956793364228694878188280848866616757710
0574265866207458775779331401221450 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_mem_rw_with_rand_reset.9494956793364228694878188
2808488666167577100574265866207458775779331401221450
Directory /workspace/4.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_rw.74649690456746400841373595993231088079757262729194269601431322360543991610164
Short name T123
Test name
Test status
Simulation time 31297136 ps
CPU time 0.65 seconds
Started Nov 22 01:06:25 PM PST 23
Finished Nov 22 01:06:26 PM PST 23
Peak memory 194928 kb
Host smart-d8d25567-b01f-4fe4-bb57-c72845aba6e8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74649690456746400841373595993231088079757262729194269601431322360543991610164 -assert nopostproc
+UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 4.hmac_csr_rw.74649690456746400841373595993231088079757262729194269601431322360543991610164
Directory /workspace/4.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_intr_test.2056608756971980460291852747393728081111660470437306070921056948377429785440
Short name T121
Test name
Test status
Simulation time 22993631 ps
CPU time 0.58 seconds
Started Nov 22 01:06:36 PM PST 23
Finished Nov 22 01:06:38 PM PST 23
Peak memory 184104 kb
Host smart-8a584980-cadd-4b5b-87fb-e0e7345f5575
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056608756971980460291852747393728081111660470437306070921056948377429785440 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 4.hmac_intr_test.2056608756971980460291852747393728081111660470437306070921056948377429785440
Directory /workspace/4.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.42247592380764312763106575323868495441724348252403677428573225602938229838555
Short name T32
Test name
Test status
Simulation time 89028817 ps
CPU time 1.12 seconds
Started Nov 22 01:06:33 PM PST 23
Finished Nov 22 01:06:35 PM PST 23
Peak memory 197272 kb
Host smart-d82408d8-45ef-4555-a55a-37fbf859c692
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42247592380764312763106575323868495441724348252403677428573225602938229838555
-assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_same_csr_outstanding.42247592380764312763106575323868495441724348252403677428573225602938229838555
Directory /workspace/4.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_errors.101164883666480819990108380049734800416112152188888050010044477164747955249594
Short name T25
Test name
Test status
Simulation time 199170793 ps
CPU time 2.27 seconds
Started Nov 22 01:06:27 PM PST 23
Finished Nov 22 01:06:31 PM PST 23
Peak memory 199020 kb
Host smart-221cd7c5-fdca-4c80-9307-961ac2094ea7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101164883666480819990108380049734800416112152188888050010044477164747955249594 -assert nopostproc +
UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.hmac_tl_errors.101164883666480819990108380049734800416112152188888050010044477164747955249594
Directory /workspace/4.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.63728540622092525375774468823327796106613434626449922268667356488279202346102
Short name T77
Test name
Test status
Simulation time 180081660 ps
CPU time 1.8 seconds
Started Nov 22 01:06:26 PM PST 23
Finished Nov 22 01:06:29 PM PST 23
Peak memory 198728 kb
Host smart-abbf8100-7d23-4c78-835f-2238ac2cdfe8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63728540622092525375774468823327796106613434626449922268667356488279202346102 -assert n
opostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_intg_err.63728540622092525375774468823327796106613434626449922268667356488279202346102
Directory /workspace/4.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.hmac_intr_test.60542412604526157230019533446840093258958043227479040413975083029020000203507
Short name T142
Test name
Test status
Simulation time 22993631 ps
CPU time 0.63 seconds
Started Nov 22 01:06:55 PM PST 23
Finished Nov 22 01:06:57 PM PST 23
Peak memory 184136 kb
Host smart-8a61c1b9-0c7f-4eb2-a4eb-7788fad80631
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60542412604526157230019533446840093258958043227479040413975083029020000203507 -assert nopostproc +U
VM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 40.hmac_intr_test.60542412604526157230019533446840093258958043227479040413975083029020000203507
Directory /workspace/40.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.hmac_intr_test.92002941142613435280819065178313029946758943466752367437413864130438054797775
Short name T139
Test name
Test status
Simulation time 22993631 ps
CPU time 0.58 seconds
Started Nov 22 01:06:38 PM PST 23
Finished Nov 22 01:06:40 PM PST 23
Peak memory 184108 kb
Host smart-485fb4e7-aa4b-444f-a9fc-2869effb8bf9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92002941142613435280819065178313029946758943466752367437413864130438054797775 -assert nopostproc +U
VM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 41.hmac_intr_test.92002941142613435280819065178313029946758943466752367437413864130438054797775
Directory /workspace/41.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.hmac_intr_test.82459572842326485839158301534030982660218420472615175916190540601111446878159
Short name T15
Test name
Test status
Simulation time 22993631 ps
CPU time 0.58 seconds
Started Nov 22 01:06:49 PM PST 23
Finished Nov 22 01:06:52 PM PST 23
Peak memory 184252 kb
Host smart-f0bde61c-b08f-4b57-842d-34de81dbb3ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82459572842326485839158301534030982660218420472615175916190540601111446878159 -assert nopostproc +U
VM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 42.hmac_intr_test.82459572842326485839158301534030982660218420472615175916190540601111446878159
Directory /workspace/42.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.hmac_intr_test.94243674389214674526815610706520934072689243069632317053902069340021929623791
Short name T128
Test name
Test status
Simulation time 22993631 ps
CPU time 0.59 seconds
Started Nov 22 01:06:50 PM PST 23
Finished Nov 22 01:06:53 PM PST 23
Peak memory 184252 kb
Host smart-d2267e8e-2635-4afd-915b-d38767f89364
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94243674389214674526815610706520934072689243069632317053902069340021929623791 -assert nopostproc +U
VM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 43.hmac_intr_test.94243674389214674526815610706520934072689243069632317053902069340021929623791
Directory /workspace/43.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.hmac_intr_test.6002722408578114329265211328875684722328543493174516654319766713221829022544
Short name T19
Test name
Test status
Simulation time 22993631 ps
CPU time 0.56 seconds
Started Nov 22 01:06:39 PM PST 23
Finished Nov 22 01:06:41 PM PST 23
Peak memory 184180 kb
Host smart-db75fc0d-a046-4996-958b-8311492490c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6002722408578114329265211328875684722328543493174516654319766713221829022544 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 44.hmac_intr_test.6002722408578114329265211328875684722328543493174516654319766713221829022544
Directory /workspace/44.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.hmac_intr_test.63981981762967011209372011797311851234249757037764104531112571001121100800328
Short name T137
Test name
Test status
Simulation time 22993631 ps
CPU time 0.58 seconds
Started Nov 22 01:06:38 PM PST 23
Finished Nov 22 01:06:40 PM PST 23
Peak memory 184224 kb
Host smart-b7e12c83-4822-4054-b323-ed1a31ffa0df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63981981762967011209372011797311851234249757037764104531112571001121100800328 -assert nopostproc +U
VM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 45.hmac_intr_test.63981981762967011209372011797311851234249757037764104531112571001121100800328
Directory /workspace/45.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.hmac_intr_test.82043400459084873176114517703114086977799858094805862200028099571982774739323
Short name T134
Test name
Test status
Simulation time 22993631 ps
CPU time 0.58 seconds
Started Nov 22 01:06:48 PM PST 23
Finished Nov 22 01:06:51 PM PST 23
Peak memory 184224 kb
Host smart-a16cb4b9-40e6-4e50-868c-b7ce5a1589ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82043400459084873176114517703114086977799858094805862200028099571982774739323 -assert nopostproc +U
VM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 46.hmac_intr_test.82043400459084873176114517703114086977799858094805862200028099571982774739323
Directory /workspace/46.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.hmac_intr_test.40492095379316846890863511470024259165076719374498379476385289464032176284220
Short name T101
Test name
Test status
Simulation time 22993631 ps
CPU time 0.55 seconds
Started Nov 22 01:06:59 PM PST 23
Finished Nov 22 01:07:01 PM PST 23
Peak memory 183988 kb
Host smart-f3b55d30-2614-4539-917b-d45951617110
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40492095379316846890863511470024259165076719374498379476385289464032176284220 -assert nopostproc +U
VM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 47.hmac_intr_test.40492095379316846890863511470024259165076719374498379476385289464032176284220
Directory /workspace/47.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.hmac_intr_test.36150321135917597687376678690609994009214335244889942692675097633492297736397
Short name T21
Test name
Test status
Simulation time 22993631 ps
CPU time 0.57 seconds
Started Nov 22 01:06:46 PM PST 23
Finished Nov 22 01:06:50 PM PST 23
Peak memory 184204 kb
Host smart-625cdb7a-0446-44eb-b11a-1d44530707ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36150321135917597687376678690609994009214335244889942692675097633492297736397 -assert nopostproc +U
VM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 48.hmac_intr_test.36150321135917597687376678690609994009214335244889942692675097633492297736397
Directory /workspace/48.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.hmac_intr_test.45913155633574800436475277714002854744586032262163261697773816959726998178196
Short name T141
Test name
Test status
Simulation time 22993631 ps
CPU time 0.57 seconds
Started Nov 22 01:06:44 PM PST 23
Finished Nov 22 01:06:48 PM PST 23
Peak memory 184164 kb
Host smart-9a0fedf4-d081-43a4-8d08-bf8ff0b6a7ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45913155633574800436475277714002854744586032262163261697773816959726998178196 -assert nopostproc +U
VM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 49.hmac_intr_test.45913155633574800436475277714002854744586032262163261697773816959726998178196
Directory /workspace/49.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.23554572190949335432714747129093369365225267711087409958534765297114404492008
Short name T886
Test name
Test status
Simulation time 129656135129 ps
CPU time 679.28 seconds
Started Nov 22 01:06:33 PM PST 23
Finished Nov 22 01:17:53 PM PST 23
Peak memory 216224 kb
Host smart-076e8dbc-e578-473d-a865-f273f887fb56
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355457219094933543271474712909336936522526
7711087409958534765297114404492008 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_csr_mem_rw_with_rand_reset.2355457219094933543271474
7129093369365225267711087409958534765297114404492008
Directory /workspace/5.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_rw.16567697679742889683023525971549070216630338227597660268302466824001097259587
Short name T114
Test name
Test status
Simulation time 31297136 ps
CPU time 0.67 seconds
Started Nov 22 01:06:27 PM PST 23
Finished Nov 22 01:06:29 PM PST 23
Peak memory 194920 kb
Host smart-f7377f29-91ca-4232-bcd0-9931567a9526
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16567697679742889683023525971549070216630338227597660268302466824001097259587 -assert nopostproc
+UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 5.hmac_csr_rw.16567697679742889683023525971549070216630338227597660268302466824001097259587
Directory /workspace/5.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_intr_test.101144809695792469813593794660767803044229632091410049433357210194176578858726
Short name T896
Test name
Test status
Simulation time 22993631 ps
CPU time 0.55 seconds
Started Nov 22 01:06:22 PM PST 23
Finished Nov 22 01:06:24 PM PST 23
Peak memory 184204 kb
Host smart-48d0627c-e45f-4a01-aae4-44b7c8cbcd01
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101144809695792469813593794660767803044229632091410049433357210194176578858726 -assert nopostproc +
UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.hmac_intr_test.101144809695792469813593794660767803044229632091410049433357210194176578858726
Directory /workspace/5.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.63576154689052050713258852383549456683215452736440570307121335312704509280857
Short name T92
Test name
Test status
Simulation time 89028817 ps
CPU time 1.06 seconds
Started Nov 22 01:06:30 PM PST 23
Finished Nov 22 01:06:32 PM PST 23
Peak memory 197500 kb
Host smart-da07915c-7d31-4893-8f75-844576de76df
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63576154689052050713258852383549456683215452736440570307121335312704509280857
-assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_same_csr_outstanding.63576154689052050713258852383549456683215452736440570307121335312704509280857
Directory /workspace/5.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_errors.112117199054192911479671229771381466782027004019731296180832213759890508452567
Short name T124
Test name
Test status
Simulation time 199170793 ps
CPU time 2.32 seconds
Started Nov 22 01:06:29 PM PST 23
Finished Nov 22 01:06:33 PM PST 23
Peak memory 199064 kb
Host smart-2f2fdb8c-9b82-47b8-9cbf-fe8d35772bfe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112117199054192911479671229771381466782027004019731296180832213759890508452567 -assert nopostproc +
UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.hmac_tl_errors.112117199054192911479671229771381466782027004019731296180832213759890508452567
Directory /workspace/5.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.7979413314858040974456772523651269019775669973729621873923564597866664308453
Short name T144
Test name
Test status
Simulation time 180081660 ps
CPU time 1.85 seconds
Started Nov 22 01:06:26 PM PST 23
Finished Nov 22 01:06:30 PM PST 23
Peak memory 198720 kb
Host smart-2a34ffbb-e61b-4c5d-9b3a-872c2e5b41eb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7979413314858040974456772523651269019775669973729621873923564597866664308453 -assert no
postproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_intg_err.7979413314858040974456772523651269019775669973729621873923564597866664308453
Directory /workspace/5.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.32555691673864619192209999430746053347629148357218608769013378492495653700561
Short name T150
Test name
Test status
Simulation time 129656135129 ps
CPU time 668 seconds
Started Nov 22 01:06:34 PM PST 23
Finished Nov 22 01:17:43 PM PST 23
Peak memory 216520 kb
Host smart-ab2bb313-9163-44a4-aa86-71cc4fcb0615
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255569167386461919220999943074605334762914
8357218608769013378492495653700561 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_csr_mem_rw_with_rand_reset.3255569167386461919220999
9430746053347629148357218608769013378492495653700561
Directory /workspace/6.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_rw.35676586577274253117515766674494224947212342230417939415922181970297322927139
Short name T119
Test name
Test status
Simulation time 31297136 ps
CPU time 0.66 seconds
Started Nov 22 01:06:39 PM PST 23
Finished Nov 22 01:06:41 PM PST 23
Peak memory 194904 kb
Host smart-47ffe322-eb9f-442a-a038-9ec24bc81e6c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35676586577274253117515766674494224947212342230417939415922181970297322927139 -assert nopostproc
+UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 6.hmac_csr_rw.35676586577274253117515766674494224947212342230417939415922181970297322927139
Directory /workspace/6.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_intr_test.35305996906886365619454260888581231267255804054476320085389602373399587582348
Short name T100
Test name
Test status
Simulation time 22993631 ps
CPU time 0.63 seconds
Started Nov 22 01:06:40 PM PST 23
Finished Nov 22 01:06:42 PM PST 23
Peak memory 184144 kb
Host smart-6bd0c356-1a8a-40be-ac83-961210b3da84
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35305996906886365619454260888581231267255804054476320085389602373399587582348 -assert nopostproc +U
VM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 6.hmac_intr_test.35305996906886365619454260888581231267255804054476320085389602373399587582348
Directory /workspace/6.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.12538181902369989836159486065876495987376619428530060957818162851984275270550
Short name T87
Test name
Test status
Simulation time 89028817 ps
CPU time 1.12 seconds
Started Nov 22 01:06:36 PM PST 23
Finished Nov 22 01:06:39 PM PST 23
Peak memory 197532 kb
Host smart-cce5cd88-a603-46a1-993e-e07a52cf24f1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12538181902369989836159486065876495987376619428530060957818162851984275270550
-assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_same_csr_outstanding.12538181902369989836159486065876495987376619428530060957818162851984275270550
Directory /workspace/6.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_errors.106254903484672662243435526326688214505385562644131554525632162309639816536008
Short name T23
Test name
Test status
Simulation time 199170793 ps
CPU time 2.29 seconds
Started Nov 22 01:06:27 PM PST 23
Finished Nov 22 01:06:31 PM PST 23
Peak memory 199092 kb
Host smart-3b56dd7e-a326-4c84-b255-cfc97ae6f30f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106254903484672662243435526326688214505385562644131554525632162309639816536008 -assert nopostproc +
UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.hmac_tl_errors.106254903484672662243435526326688214505385562644131554525632162309639816536008
Directory /workspace/6.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.30561545625034785979072659625797478081016896446077164372006127000813966930778
Short name T106
Test name
Test status
Simulation time 180081660 ps
CPU time 1.8 seconds
Started Nov 22 01:06:30 PM PST 23
Finished Nov 22 01:06:33 PM PST 23
Peak memory 198712 kb
Host smart-d6f34487-3900-48a8-914e-b261eb4cc0f4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30561545625034785979072659625797478081016896446077164372006127000813966930778 -assert n
opostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_intg_err.30561545625034785979072659625797478081016896446077164372006127000813966930778
Directory /workspace/6.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.81582856979197896871550565149898993443249540476463346672009131231174829782564
Short name T129
Test name
Test status
Simulation time 129656135129 ps
CPU time 666.84 seconds
Started Nov 22 01:06:30 PM PST 23
Finished Nov 22 01:17:38 PM PST 23
Peak memory 216428 kb
Host smart-2480eaf9-eb39-4680-acc9-37a38b4cc2b0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8158285697919789687155056514989899344324954
0476463346672009131231174829782564 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_csr_mem_rw_with_rand_reset.8158285697919789687155056
5149898993443249540476463346672009131231174829782564
Directory /workspace/7.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_rw.62627462711161021370553388721459742833746281279821897866926426360868112809936
Short name T149
Test name
Test status
Simulation time 31297136 ps
CPU time 0.67 seconds
Started Nov 22 01:06:27 PM PST 23
Finished Nov 22 01:06:29 PM PST 23
Peak memory 194896 kb
Host smart-ace84df9-2f5d-47ad-829c-5fbda3bbafa1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62627462711161021370553388721459742833746281279821897866926426360868112809936 -assert nopostproc
+UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 7.hmac_csr_rw.62627462711161021370553388721459742833746281279821897866926426360868112809936
Directory /workspace/7.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_intr_test.97094480006521771537666957390750299384732359623009721060239676171220925358582
Short name T122
Test name
Test status
Simulation time 22993631 ps
CPU time 0.63 seconds
Started Nov 22 01:06:28 PM PST 23
Finished Nov 22 01:06:30 PM PST 23
Peak memory 184224 kb
Host smart-5ed19d45-396a-488d-8f62-5006c6d34c82
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97094480006521771537666957390750299384732359623009721060239676171220925358582 -assert nopostproc +U
VM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 7.hmac_intr_test.97094480006521771537666957390750299384732359623009721060239676171220925358582
Directory /workspace/7.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.59908528462296136204147730157499214703467277199887251399032871916592632049890
Short name T160
Test name
Test status
Simulation time 89028817 ps
CPU time 1.16 seconds
Started Nov 22 01:06:40 PM PST 23
Finished Nov 22 01:06:42 PM PST 23
Peak memory 197548 kb
Host smart-2a33e3fb-ccb2-4753-a632-1eb4e65b0bef
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59908528462296136204147730157499214703467277199887251399032871916592632049890
-assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_same_csr_outstanding.59908528462296136204147730157499214703467277199887251399032871916592632049890
Directory /workspace/7.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_errors.13103779409574486687291450996223120526224035476289679506995218074261387538265
Short name T891
Test name
Test status
Simulation time 199170793 ps
CPU time 2.29 seconds
Started Nov 22 01:06:37 PM PST 23
Finished Nov 22 01:06:40 PM PST 23
Peak memory 199060 kb
Host smart-9ea3b5bf-ea2c-4e07-a1dc-23489961f2f4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13103779409574486687291450996223120526224035476289679506995218074261387538265 -assert nopostproc +U
VM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 7.hmac_tl_errors.13103779409574486687291450996223120526224035476289679506995218074261387538265
Directory /workspace/7.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.78123181162223298484394489502881969625787156241420344123693592797033443079426
Short name T73
Test name
Test status
Simulation time 180081660 ps
CPU time 1.77 seconds
Started Nov 22 01:06:33 PM PST 23
Finished Nov 22 01:06:36 PM PST 23
Peak memory 198756 kb
Host smart-3d6f1bbf-77fa-43f4-b105-614a1e8413fe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78123181162223298484394489502881969625787156241420344123693592797033443079426 -assert n
opostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_intg_err.78123181162223298484394489502881969625787156241420344123693592797033443079426
Directory /workspace/7.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.98664225299002389305272683863731737866865549497644753470860285727377987696550
Short name T27
Test name
Test status
Simulation time 129656135129 ps
CPU time 665.95 seconds
Started Nov 22 01:06:40 PM PST 23
Finished Nov 22 01:17:48 PM PST 23
Peak memory 216424 kb
Host smart-a3c2130f-7f07-4f13-94eb-1bd98b9c3aec
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9866422529900238930527268386373173786686554
9497644753470860285727377987696550 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_csr_mem_rw_with_rand_reset.9866422529900238930527268
3863731737866865549497644753470860285727377987696550
Directory /workspace/8.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_rw.19383097170854366244085955171376631680154248990910034536376111460916343923603
Short name T155
Test name
Test status
Simulation time 31297136 ps
CPU time 0.68 seconds
Started Nov 22 01:06:41 PM PST 23
Finished Nov 22 01:06:43 PM PST 23
Peak memory 194860 kb
Host smart-e35fc351-8781-45ea-a6ad-2f4e5f97b499
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19383097170854366244085955171376631680154248990910034536376111460916343923603 -assert nopostproc
+UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 8.hmac_csr_rw.19383097170854366244085955171376631680154248990910034536376111460916343923603
Directory /workspace/8.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_intr_test.92889851021535615666263403921695664527091764722304854155855258311165009411983
Short name T897
Test name
Test status
Simulation time 22993631 ps
CPU time 0.56 seconds
Started Nov 22 01:06:42 PM PST 23
Finished Nov 22 01:06:46 PM PST 23
Peak memory 184172 kb
Host smart-edf75707-e4c8-4107-a99c-814c5f98963e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92889851021535615666263403921695664527091764722304854155855258311165009411983 -assert nopostproc +U
VM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 8.hmac_intr_test.92889851021535615666263403921695664527091764722304854155855258311165009411983
Directory /workspace/8.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.41132549074742787254806498556174906250031685179167611995357489007470914314154
Short name T91
Test name
Test status
Simulation time 89028817 ps
CPU time 1.11 seconds
Started Nov 22 01:06:40 PM PST 23
Finished Nov 22 01:06:43 PM PST 23
Peak memory 197504 kb
Host smart-3fee25cb-aef2-407e-a95b-fa09ba0115b0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41132549074742787254806498556174906250031685179167611995357489007470914314154
-assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_same_csr_outstanding.41132549074742787254806498556174906250031685179167611995357489007470914314154
Directory /workspace/8.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_errors.78143708979823372352297973399505999552587174834779747868274168412716204501271
Short name T158
Test name
Test status
Simulation time 199170793 ps
CPU time 2.24 seconds
Started Nov 22 01:06:33 PM PST 23
Finished Nov 22 01:06:36 PM PST 23
Peak memory 199100 kb
Host smart-d681df34-c4f8-40f9-b438-45f134f82e41
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78143708979823372352297973399505999552587174834779747868274168412716204501271 -assert nopostproc +U
VM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 8.hmac_tl_errors.78143708979823372352297973399505999552587174834779747868274168412716204501271
Directory /workspace/8.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.75060704352913979794328764702776657251810607320288505760452168219668831854957
Short name T902
Test name
Test status
Simulation time 180081660 ps
CPU time 1.84 seconds
Started Nov 22 01:06:34 PM PST 23
Finished Nov 22 01:06:37 PM PST 23
Peak memory 198756 kb
Host smart-f14ce8d1-a98b-41d7-937b-2ba97954f64c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75060704352913979794328764702776657251810607320288505760452168219668831854957 -assert n
opostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_intg_err.75060704352913979794328764702776657251810607320288505760452168219668831854957
Directory /workspace/8.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_rw.83113417884650319135477380425107613444193766161753700979664084088726345624365
Short name T882
Test name
Test status
Simulation time 31297136 ps
CPU time 0.67 seconds
Started Nov 22 01:06:42 PM PST 23
Finished Nov 22 01:06:47 PM PST 23
Peak memory 194860 kb
Host smart-a03b1dd6-8e84-46f3-8f5d-b9b5d18ab8e3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83113417884650319135477380425107613444193766161753700979664084088726345624365 -assert nopostproc
+UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 9.hmac_csr_rw.83113417884650319135477380425107613444193766161753700979664084088726345624365
Directory /workspace/9.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_intr_test.51897240959019843057508052574172040337519912612204553375908921819731541526015
Short name T98
Test name
Test status
Simulation time 22993631 ps
CPU time 0.57 seconds
Started Nov 22 01:06:33 PM PST 23
Finished Nov 22 01:06:35 PM PST 23
Peak memory 184240 kb
Host smart-43a534db-8f91-4ead-9449-d106f12b547a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51897240959019843057508052574172040337519912612204553375908921819731541526015 -assert nopostproc +U
VM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 9.hmac_intr_test.51897240959019843057508052574172040337519912612204553375908921819731541526015
Directory /workspace/9.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.69778367495777427243866932273053938175153466290896984071659917694589001797035
Short name T169
Test name
Test status
Simulation time 89028817 ps
CPU time 1.09 seconds
Started Nov 22 01:06:41 PM PST 23
Finished Nov 22 01:06:43 PM PST 23
Peak memory 197504 kb
Host smart-b90661ef-49a4-4610-a8dd-7c8f550047b3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69778367495777427243866932273053938175153466290896984071659917694589001797035
-assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_same_csr_outstanding.69778367495777427243866932273053938175153466290896984071659917694589001797035
Directory /workspace/9.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_errors.12760342923342457770005550650915191296581564370016511654789085659103600030275
Short name T28
Test name
Test status
Simulation time 199170793 ps
CPU time 2.28 seconds
Started Nov 22 01:06:39 PM PST 23
Finished Nov 22 01:06:43 PM PST 23
Peak memory 199068 kb
Host smart-1678ec19-425b-4660-afcd-bfdfec532097
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12760342923342457770005550650915191296581564370016511654789085659103600030275 -assert nopostproc +U
VM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 9.hmac_tl_errors.12760342923342457770005550650915191296581564370016511654789085659103600030275
Directory /workspace/9.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.26786730992756385936610572712772198361402502460838659347877873244350000476905
Short name T108
Test name
Test status
Simulation time 180081660 ps
CPU time 1.78 seconds
Started Nov 22 01:06:33 PM PST 23
Finished Nov 22 01:06:36 PM PST 23
Peak memory 198756 kb
Host smart-ba9d6b08-a5c1-4cc3-86be-94e4a90cb72a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26786730992756385936610572712772198361402502460838659347877873244350000476905 -assert n
opostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_intg_err.26786730992756385936610572712772198361402502460838659347877873244350000476905
Directory /workspace/9.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/0.hmac_back_pressure.64842987200263986147459568514903251020786377992881985289491433147373972452810
Short name T687
Test name
Test status
Simulation time 2592169506 ps
CPU time 45.27 seconds
Started Nov 22 01:08:55 PM PST 23
Finished Nov 22 01:09:45 PM PST 23
Peak memory 230992 kb
Host smart-15c0492f-b08c-46cc-be5f-5daa2baedb0c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=64842987200263986147459568514903251020786377992881985289491433147373972452810 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 0.hmac_back_pressure.64842987200263986147459568514903251020786377992881985289491433147373972452810
Directory /workspace/0.hmac_back_pressure/latest

Test location /workspace/coverage/default/0.hmac_burst_wr.56266412549536277905051100368645416470230970720626195616478855599974403170338
Short name T413
Test name
Test status
Simulation time 4504100639 ps
CPU time 35.91 seconds
Started Nov 22 01:08:55 PM PST 23
Finished Nov 22 01:09:36 PM PST 23
Peak memory 198376 kb
Host smart-1e4099a4-7e3e-4a0b-b672-6890249f0ee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56266412549536277905051100368645416470230970720626195616478855599974403170338 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.hmac_burst_wr.56266412549536277905051100368645416470230970720626195616478855599974403170338
Directory /workspace/0.hmac_burst_wr/latest

Test location /workspace/coverage/default/0.hmac_datapath_stress.107609261717377470059312629008694367235745522490550858083582416524695840583709
Short name T683
Test name
Test status
Simulation time 4863401336 ps
CPU time 146.85 seconds
Started Nov 22 01:08:36 PM PST 23
Finished Nov 22 01:11:15 PM PST 23
Peak memory 198592 kb
Host smart-07e29fd4-486d-49ec-993a-b76797090da7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=107609261717377470059312629008694367235745522490550858083582416524695840583709 -assert nopostproc +UVM_TE
STNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 0.hmac_datapath_stress.107609261717377470059312629008694367235745522490550858083582416524695840583709
Directory /workspace/0.hmac_datapath_stress/latest

Test location /workspace/coverage/default/0.hmac_error.48179180009739065325564503669441351527120264055508028892494236497911601394980
Short name T530
Test name
Test status
Simulation time 26556692074 ps
CPU time 185.67 seconds
Started Nov 22 01:08:51 PM PST 23
Finished Nov 22 01:12:04 PM PST 23
Peak memory 198408 kb
Host smart-5ba7cc2b-8085-4f30-aeb7-a78a3ecb90a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48179180009739065325564503669441351527120264055508028892494236497911601394980 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 0.hmac_error.48179180009739065325564503669441351527120264055508028892494236497911601394980
Directory /workspace/0.hmac_error/latest

Test location /workspace/coverage/default/0.hmac_long_msg.54062495008284246004980276079004977743630837304513160096864772030115913577450
Short name T533
Test name
Test status
Simulation time 14959266997 ps
CPU time 115.06 seconds
Started Nov 22 01:08:55 PM PST 23
Finished Nov 22 01:10:55 PM PST 23
Peak memory 198248 kb
Host smart-7796f1ba-1a8a-46a7-a0a3-9f4f55853cc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54062495008284246004980276079004977743630837304513160096864772030115913577450 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.hmac_long_msg.54062495008284246004980276079004977743630837304513160096864772030115913577450
Directory /workspace/0.hmac_long_msg/latest

Test location /workspace/coverage/default/0.hmac_smoke.72414746887461820678833181077585245368375001250299584794727925984045119360880
Short name T775
Test name
Test status
Simulation time 631560191 ps
CPU time 3.94 seconds
Started Nov 22 01:08:58 PM PST 23
Finished Nov 22 01:09:11 PM PST 23
Peak memory 198360 kb
Host smart-806bda63-7cb7-434b-8688-be26a9cb6e67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72414746887461820678833181077585245368375001250299584794727925984045119360880 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 0.hmac_smoke.72414746887461820678833181077585245368375001250299584794727925984045119360880
Directory /workspace/0.hmac_smoke/latest

Test location /workspace/coverage/default/0.hmac_stress_all.56842185931673602520609855852471908598233496723722002965472034571975917302606
Short name T601
Test name
Test status
Simulation time 146644856361 ps
CPU time 1090.43 seconds
Started Nov 22 01:08:51 PM PST 23
Finished Nov 22 01:27:09 PM PST 23
Peak memory 210656 kb
Host smart-b752c803-e9d9-4701-ae39-7da8cbe65694
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568421859316736025206098
55852471908598233496723722002965472034571975917302606 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all.568421859316736025206098
55852471908598233496723722002965472034571975917302606
Directory /workspace/0.hmac_stress_all/latest

Test location /workspace/coverage/default/0.hmac_stress_all_with_rand_reset.75085556379723211402461991207385680801901308489048922512955798848810693998335
Short name T867
Test name
Test status
Simulation time 80460760838 ps
CPU time 707.45 seconds
Started Nov 22 01:08:40 PM PST 23
Finished Nov 22 01:20:37 PM PST 23
Peak memory 210296 kb
Host smart-04de3cf3-7c33-46ca-a13f-c69334df1b44
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=75085556379723211402461991207385680801901308489048922512955798848810693998335 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 0.hmac_stress_all_with_rand_reset.75085556379723211402461991207385680801901308489048922512955798848810693998335
Directory /workspace/0.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.hmac_test_hmac_vectors.97272393288382164064240109558321028832640944615282274181816223935673522383944
Short name T780
Test name
Test status
Simulation time 76314633 ps
CPU time 0.91 seconds
Started Nov 22 01:08:36 PM PST 23
Finished Nov 22 01:08:50 PM PST 23
Peak memory 195792 kb
Host smart-c302513e-f41a-4575-94fd-ae087f94ebcd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97272393288382164064240109558321028832640944615282274
181816223935673522383944 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac_vectors.972723932883821640642401095583210288326
40944615282274181816223935673522383944
Directory /workspace/0.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha_vectors.50214819225599197069277480496795223395267262492621555821971343177080049427549
Short name T441
Test name
Test status
Simulation time 63914107498 ps
CPU time 445.91 seconds
Started Nov 22 01:08:51 PM PST 23
Finished Nov 22 01:16:24 PM PST 23
Peak memory 198424 kb
Host smart-55832cd8-989d-4374-878b-0ebab7f722e0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50214819225599197069277480496795223395267262492621555
821971343177080049427549 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha_vectors.50214819225599197069277480496795223395267
262492621555821971343177080049427549
Directory /workspace/0.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/0.hmac_wipe_secret.659404354696676300612543290036983373326166704145900111250198445944268153751
Short name T828
Test name
Test status
Simulation time 8070750677 ps
CPU time 60.02 seconds
Started Nov 22 01:08:51 PM PST 23
Finished Nov 22 01:09:58 PM PST 23
Peak memory 198380 kb
Host smart-e587d94a-2f5d-45b5-8fbd-43e384b50189
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=659404354696676300612543290036983373326166704145900111250198445944268153751 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 0.hmac_wipe_secret.659404354696676300612543290036983373326166704145900111250198445944268153751
Directory /workspace/0.hmac_wipe_secret/latest

Test location /workspace/coverage/default/1.hmac_alert_test.28152260763095402588957255264600507481180332823895303723639094608589006460924
Short name T276
Test name
Test status
Simulation time 18011528 ps
CPU time 0.53 seconds
Started Nov 22 01:08:55 PM PST 23
Finished Nov 22 01:09:00 PM PST 23
Peak memory 192688 kb
Host smart-b849c3bb-35bc-4509-8290-aa9a2a864fda
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28152260763095402588957255264600507481180332823895303723639094608589006460924 -assert nopostpr
oc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 1.hmac_alert_test.28152260763095402588957255264600507481180332823895303723639094608589006460924
Directory /workspace/1.hmac_alert_test/latest

Test location /workspace/coverage/default/1.hmac_back_pressure.82225391550181030274464042735197406508032055216152260765258313425034265948248
Short name T353
Test name
Test status
Simulation time 2592169506 ps
CPU time 45.04 seconds
Started Nov 22 01:08:50 PM PST 23
Finished Nov 22 01:09:43 PM PST 23
Peak memory 231208 kb
Host smart-15cd0af2-e851-4c75-b012-9975648a97a1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=82225391550181030274464042735197406508032055216152260765258313425034265948248 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 1.hmac_back_pressure.82225391550181030274464042735197406508032055216152260765258313425034265948248
Directory /workspace/1.hmac_back_pressure/latest

Test location /workspace/coverage/default/1.hmac_burst_wr.60794791912002089747446861938714928391373360865221095979967820313998752150252
Short name T719
Test name
Test status
Simulation time 4504100639 ps
CPU time 36.81 seconds
Started Nov 22 01:08:50 PM PST 23
Finished Nov 22 01:09:34 PM PST 23
Peak memory 198404 kb
Host smart-8cd57899-7bb3-4434-9038-a0f0e0de2180
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60794791912002089747446861938714928391373360865221095979967820313998752150252 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.hmac_burst_wr.60794791912002089747446861938714928391373360865221095979967820313998752150252
Directory /workspace/1.hmac_burst_wr/latest

Test location /workspace/coverage/default/1.hmac_error.114237495156930517447659508546217355035943472387296916765911503299272620046307
Short name T374
Test name
Test status
Simulation time 26556692074 ps
CPU time 189.58 seconds
Started Nov 22 01:08:55 PM PST 23
Finished Nov 22 01:12:09 PM PST 23
Peak memory 198456 kb
Host smart-4248b563-6e0b-44c3-9fc6-fa82c9b3ce76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114237495156930517447659508546217355035943472387296916765911503299272620046307 -assert nopostproc +UVM_TESTNAME=hmac_bas
e_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 1.hmac_error.114237495156930517447659508546217355035943472387296916765911503299272620046307
Directory /workspace/1.hmac_error/latest

Test location /workspace/coverage/default/1.hmac_long_msg.74898970792797619138176410045692566822778338948302361751486282791242127129125
Short name T597
Test name
Test status
Simulation time 14959266997 ps
CPU time 114.39 seconds
Started Nov 22 01:08:51 PM PST 23
Finished Nov 22 01:10:53 PM PST 23
Peak memory 198400 kb
Host smart-4c7ccfd0-c5b2-4d06-b849-466b67ccaedb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74898970792797619138176410045692566822778338948302361751486282791242127129125 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.hmac_long_msg.74898970792797619138176410045692566822778338948302361751486282791242127129125
Directory /workspace/1.hmac_long_msg/latest

Test location /workspace/coverage/default/1.hmac_sec_cm.105285643156528051673399787018419049642414743595060838527711878466094885201716
Short name T61
Test name
Test status
Simulation time 100939436 ps
CPU time 0.87 seconds
Started Nov 22 01:08:51 PM PST 23
Finished Nov 22 01:08:59 PM PST 23
Peak memory 215584 kb
Host smart-455c9b34-cd5b-4b0e-9075-3e7273dfc18e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105285643156528051673399787018419049642414743595060838527711878466094885201716 -assert nopostpr
oc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 1.hmac_sec_cm.105285643156528051673399787018419049642414743595060838527711878466094885201716
Directory /workspace/1.hmac_sec_cm/latest

Test location /workspace/coverage/default/1.hmac_smoke.84391153140511479543412056008529249817882957971148895242478897989408314843989
Short name T787
Test name
Test status
Simulation time 631560191 ps
CPU time 4 seconds
Started Nov 22 01:08:36 PM PST 23
Finished Nov 22 01:08:53 PM PST 23
Peak memory 198508 kb
Host smart-76c9bda4-e26b-4cba-992a-6064ce8cc632
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84391153140511479543412056008529249817882957971148895242478897989408314843989 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 1.hmac_smoke.84391153140511479543412056008529249817882957971148895242478897989408314843989
Directory /workspace/1.hmac_smoke/latest

Test location /workspace/coverage/default/1.hmac_stress_all.60681528897178530351032028887286803558404343637031477080864395532438836575194
Short name T493
Test name
Test status
Simulation time 146644856361 ps
CPU time 1090.24 seconds
Started Nov 22 01:08:52 PM PST 23
Finished Nov 22 01:27:09 PM PST 23
Peak memory 210720 kb
Host smart-65d11a32-28af-481e-946f-96dfc3a06516
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606815288971785303510320
28887286803558404343637031477080864395532438836575194 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all.606815288971785303510320
28887286803558404343637031477080864395532438836575194
Directory /workspace/1.hmac_stress_all/latest

Test location /workspace/coverage/default/1.hmac_stress_all_with_rand_reset.20517059191976513102179881782341421316084576694172260943221880749220176109647
Short name T550
Test name
Test status
Simulation time 80460760838 ps
CPU time 706.71 seconds
Started Nov 22 01:08:36 PM PST 23
Finished Nov 22 01:20:36 PM PST 23
Peak memory 210336 kb
Host smart-a8bca834-ca43-43a7-b991-ece8b7b60289
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=20517059191976513102179881782341421316084576694172260943221880749220176109647 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 1.hmac_stress_all_with_rand_reset.20517059191976513102179881782341421316084576694172260943221880749220176109647
Directory /workspace/1.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.hmac_test_hmac_vectors.28368977003860375800169404144774905580191579215137493834354715889368920520206
Short name T349
Test name
Test status
Simulation time 76314633 ps
CPU time 0.91 seconds
Started Nov 22 01:08:52 PM PST 23
Finished Nov 22 01:08:59 PM PST 23
Peak memory 195628 kb
Host smart-7703684d-f3ac-4d31-a58e-c35ebec390f1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28368977003860375800169404144774905580191579215137493
834354715889368920520206 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac_vectors.283689770038603758001694041447749055801
91579215137493834354715889368920520206
Directory /workspace/1.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha_vectors.113887878803512974821596980266247022262224514491622131690556725720040582979180
Short name T685
Test name
Test status
Simulation time 63914107498 ps
CPU time 455.56 seconds
Started Nov 22 01:08:50 PM PST 23
Finished Nov 22 01:16:33 PM PST 23
Peak memory 198544 kb
Host smart-d5c70581-44f7-49af-bfd0-a82e890e93fb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11388787880351297482159698026624702226222451449162213
1690556725720040582979180 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha_vectors.1138878788035129748215969802662470222622
24514491622131690556725720040582979180
Directory /workspace/1.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/1.hmac_wipe_secret.61037930685103351574382178344608958053154107707635266340496630128134524990360
Short name T67
Test name
Test status
Simulation time 8070750677 ps
CPU time 59.06 seconds
Started Nov 22 01:08:51 PM PST 23
Finished Nov 22 01:09:57 PM PST 23
Peak memory 198452 kb
Host smart-0330c899-dbd8-4e4d-82bc-491c1f33fb2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61037930685103351574382178344608958053154107707635266340496630128134524990360 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 1.hmac_wipe_secret.61037930685103351574382178344608958053154107707635266340496630128134524990360
Directory /workspace/1.hmac_wipe_secret/latest

Test location /workspace/coverage/default/10.hmac_alert_test.30604368075993812028329347792466101309755670728512539053187475463211990686781
Short name T421
Test name
Test status
Simulation time 18011528 ps
CPU time 0.53 seconds
Started Nov 22 01:09:21 PM PST 23
Finished Nov 22 01:09:23 PM PST 23
Peak memory 192868 kb
Host smart-73afbae4-e769-4963-a1e8-745623155bf2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30604368075993812028329347792466101309755670728512539053187475463211990686781 -assert nopostpr
oc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 10.hmac_alert_test.30604368075993812028329347792466101309755670728512539053187475463211990686781
Directory /workspace/10.hmac_alert_test/latest

Test location /workspace/coverage/default/10.hmac_back_pressure.21714980190801120086236248566784496090085946760092913127804398956191111214834
Short name T419
Test name
Test status
Simulation time 2592169506 ps
CPU time 48.8 seconds
Started Nov 22 01:09:25 PM PST 23
Finished Nov 22 01:10:15 PM PST 23
Peak memory 231316 kb
Host smart-4cf9562d-9b75-47e0-82cd-6767b2254dc5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=21714980190801120086236248566784496090085946760092913127804398956191111214834 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 10.hmac_back_pressure.21714980190801120086236248566784496090085946760092913127804398956191111214834
Directory /workspace/10.hmac_back_pressure/latest

Test location /workspace/coverage/default/10.hmac_burst_wr.104248908681058457014455431738967841291684924308190705770251965363989557350629
Short name T481
Test name
Test status
Simulation time 4504100639 ps
CPU time 38.02 seconds
Started Nov 22 01:09:19 PM PST 23
Finished Nov 22 01:09:58 PM PST 23
Peak memory 198576 kb
Host smart-c7a2b0f2-69a3-49d5-90c7-3ad960b64000
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104248908681058457014455431738967841291684924308190705770251965363989557350629 -assert nopostproc +UVM_TESTNAME=hmac_bas
e_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 10.hmac_burst_wr.104248908681058457014455431738967841291684924308190705770251965363989557350629
Directory /workspace/10.hmac_burst_wr/latest

Test location /workspace/coverage/default/10.hmac_datapath_stress.37905309225722407093226839021177263784271493814023625091126663635854611016585
Short name T814
Test name
Test status
Simulation time 4863401336 ps
CPU time 148.89 seconds
Started Nov 22 01:09:28 PM PST 23
Finished Nov 22 01:11:58 PM PST 23
Peak memory 198576 kb
Host smart-380c02f5-fd95-4aa4-9434-1cf63abcc6be
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=37905309225722407093226839021177263784271493814023625091126663635854611016585 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 10.hmac_datapath_stress.37905309225722407093226839021177263784271493814023625091126663635854611016585
Directory /workspace/10.hmac_datapath_stress/latest

Test location /workspace/coverage/default/10.hmac_error.48111679147518096250738427950676516008633220698950945959959323877110223723471
Short name T730
Test name
Test status
Simulation time 26556692074 ps
CPU time 196.72 seconds
Started Nov 22 01:09:19 PM PST 23
Finished Nov 22 01:12:38 PM PST 23
Peak memory 198596 kb
Host smart-45eae076-8db2-47db-997a-df94a4fde35a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48111679147518096250738427950676516008633220698950945959959323877110223723471 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 10.hmac_error.48111679147518096250738427950676516008633220698950945959959323877110223723471
Directory /workspace/10.hmac_error/latest

Test location /workspace/coverage/default/10.hmac_long_msg.14967835599148152990782565579594469231978051712383906997133231241881714401108
Short name T283
Test name
Test status
Simulation time 14959266997 ps
CPU time 117.49 seconds
Started Nov 22 01:09:21 PM PST 23
Finished Nov 22 01:11:21 PM PST 23
Peak memory 198476 kb
Host smart-0b808b2c-04e7-4585-b7ec-a85675fb98fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14967835599148152990782565579594469231978051712383906997133231241881714401108 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.hmac_long_msg.14967835599148152990782565579594469231978051712383906997133231241881714401108
Directory /workspace/10.hmac_long_msg/latest

Test location /workspace/coverage/default/10.hmac_smoke.23743264817703409121676246014909607004450044469477842858221831140518596543295
Short name T454
Test name
Test status
Simulation time 631560191 ps
CPU time 4.11 seconds
Started Nov 22 01:09:21 PM PST 23
Finished Nov 22 01:09:27 PM PST 23
Peak memory 198532 kb
Host smart-ddf3b28d-690d-4ea6-953f-10bfa7eb41fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23743264817703409121676246014909607004450044469477842858221831140518596543295 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 10.hmac_smoke.23743264817703409121676246014909607004450044469477842858221831140518596543295
Directory /workspace/10.hmac_smoke/latest

Test location /workspace/coverage/default/10.hmac_stress_all.102690644148279516861989729534410457709651001507061167810070530274661157219521
Short name T862
Test name
Test status
Simulation time 146644856361 ps
CPU time 1138 seconds
Started Nov 22 01:09:27 PM PST 23
Finished Nov 22 01:28:27 PM PST 23
Peak memory 210768 kb
Host smart-fe51f133-3418-499b-b59b-635d98c4e6ab
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102690644148279516861989
729534410457709651001507061167810070530274661157219521 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_stress_all.1026906441482795168619
89729534410457709651001507061167810070530274661157219521
Directory /workspace/10.hmac_stress_all/latest

Test location /workspace/coverage/default/10.hmac_stress_all_with_rand_reset.21905414876957439310717596349424699651401049289897409156444186609806462621876
Short name T395
Test name
Test status
Simulation time 80460760838 ps
CPU time 688.23 seconds
Started Nov 22 01:09:24 PM PST 23
Finished Nov 22 01:20:54 PM PST 23
Peak memory 209336 kb
Host smart-fdd4a3eb-a0db-4d45-aeb7-7d20842af8ca
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=21905414876957439310717596349424699651401049289897409156444186609806462621876 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 10.hmac_stress_all_with_rand_reset.21905414876957439310717596349424699651401049289897409156444186609806462621876
Directory /workspace/10.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.hmac_test_hmac_vectors.71817145983183888791543906275448368124276972134466869453267952741082550898523
Short name T675
Test name
Test status
Simulation time 76314633 ps
CPU time 0.89 seconds
Started Nov 22 01:09:21 PM PST 23
Finished Nov 22 01:09:24 PM PST 23
Peak memory 195708 kb
Host smart-74f083ad-b614-4a78-b736-9d48d1438519
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71817145983183888791543906275448368124276972134466869
453267952741082550898523 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_test_hmac_vectors.71817145983183888791543906275448368124
276972134466869453267952741082550898523
Directory /workspace/10.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/10.hmac_test_sha_vectors.50330003173867097213396167383847577885051283137658786541083091506262852744552
Short name T307
Test name
Test status
Simulation time 63914107498 ps
CPU time 445.63 seconds
Started Nov 22 01:09:19 PM PST 23
Finished Nov 22 01:16:47 PM PST 23
Peak memory 198608 kb
Host smart-39e98a7b-3d93-4143-8be6-816fbcc832ae
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50330003173867097213396167383847577885051283137658786
541083091506262852744552 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_test_sha_vectors.5033000317386709721339616738384757788505
1283137658786541083091506262852744552
Directory /workspace/10.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/10.hmac_wipe_secret.104950798358355280733072181435009595040296255934335666945572016855651901490712
Short name T510
Test name
Test status
Simulation time 8070750677 ps
CPU time 62.49 seconds
Started Nov 22 01:09:22 PM PST 23
Finished Nov 22 01:10:27 PM PST 23
Peak memory 198588 kb
Host smart-cebdde74-b47c-4659-bb87-1000b0a2ca60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104950798358355280733072181435009595040296255934335666945572016855651901490712 -assert nopostproc +UVM_TESTNAME=hmac_bas
e_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 10.hmac_wipe_secret.104950798358355280733072181435009595040296255934335666945572016855651901490712
Directory /workspace/10.hmac_wipe_secret/latest

Test location /workspace/coverage/default/100.hmac_stress_all_with_rand_reset.92125235119663999583895681264020051465216636595359009274608277559340641721085
Short name T350
Test name
Test status
Simulation time 80460760838 ps
CPU time 695.76 seconds
Started Nov 22 01:10:52 PM PST 23
Finished Nov 22 01:22:30 PM PST 23
Peak memory 209264 kb
Host smart-097669af-4aae-431b-b22c-c612d6c3a10a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=92125235119663999583895681264020051465216636595359009274608277559340641721085 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 100.hmac_stress_all_with_rand_reset.92125235119663999583895681264020051465216636595359009274608277559340641721085
Directory /workspace/100.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/101.hmac_stress_all_with_rand_reset.77186708136637940418783890514211998197706952246105382864540798709055071175362
Short name T483
Test name
Test status
Simulation time 80460760838 ps
CPU time 702.08 seconds
Started Nov 22 01:11:01 PM PST 23
Finished Nov 22 01:22:45 PM PST 23
Peak memory 209292 kb
Host smart-66d47074-b1e6-403a-8859-60140fec3ed8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=77186708136637940418783890514211998197706952246105382864540798709055071175362 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 101.hmac_stress_all_with_rand_reset.77186708136637940418783890514211998197706952246105382864540798709055071175362
Directory /workspace/101.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/102.hmac_stress_all_with_rand_reset.48146002141629731043900763450014136807546215633161241215524010673883175368209
Short name T622
Test name
Test status
Simulation time 80460760838 ps
CPU time 691.46 seconds
Started Nov 22 01:11:00 PM PST 23
Finished Nov 22 01:22:33 PM PST 23
Peak memory 209272 kb
Host smart-ef9c0c2d-389a-4709-91fe-ffb7e4ec4de7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=48146002141629731043900763450014136807546215633161241215524010673883175368209 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 102.hmac_stress_all_with_rand_reset.48146002141629731043900763450014136807546215633161241215524010673883175368209
Directory /workspace/102.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/103.hmac_stress_all_with_rand_reset.34685738888562003491377521099378808128005517797034128697361249930069178017388
Short name T188
Test name
Test status
Simulation time 80460760838 ps
CPU time 716.64 seconds
Started Nov 22 01:11:00 PM PST 23
Finished Nov 22 01:22:59 PM PST 23
Peak memory 209320 kb
Host smart-815a58b7-e8b5-42e9-b421-fea88b6f12da
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=34685738888562003491377521099378808128005517797034128697361249930069178017388 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 103.hmac_stress_all_with_rand_reset.34685738888562003491377521099378808128005517797034128697361249930069178017388
Directory /workspace/103.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/104.hmac_stress_all_with_rand_reset.112507515766296791528574903785031343284334845370354883901445372478342458401718
Short name T750
Test name
Test status
Simulation time 80460760838 ps
CPU time 717.59 seconds
Started Nov 22 01:11:01 PM PST 23
Finished Nov 22 01:23:00 PM PST 23
Peak memory 209364 kb
Host smart-2d5d775f-f278-4287-bbdf-79323cdd13cb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=112507515766296791528574903785031343284334845370354883901445372478342458401718 -assert nopostproc +UVM_TE
STNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 104.hmac_stress_all_with_rand_reset.112507515766296791528574903785031343284334845370354883901445372478342458401718
Directory /workspace/104.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/105.hmac_stress_all_with_rand_reset.45952202613176521565381245523540240833853103313735811167264593178964139447026
Short name T749
Test name
Test status
Simulation time 80460760838 ps
CPU time 712.16 seconds
Started Nov 22 01:11:03 PM PST 23
Finished Nov 22 01:22:56 PM PST 23
Peak memory 209340 kb
Host smart-47e29a82-08d8-418d-909c-9f464f68856e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=45952202613176521565381245523540240833853103313735811167264593178964139447026 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 105.hmac_stress_all_with_rand_reset.45952202613176521565381245523540240833853103313735811167264593178964139447026
Directory /workspace/105.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/107.hmac_stress_all_with_rand_reset.80505660557774841232848582910696226345372685167372897439528716008467254138441
Short name T592
Test name
Test status
Simulation time 80460760838 ps
CPU time 695.75 seconds
Started Nov 22 01:11:01 PM PST 23
Finished Nov 22 01:22:38 PM PST 23
Peak memory 209204 kb
Host smart-4b0489a5-d54a-4671-b719-27b7e70b1efd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=80505660557774841232848582910696226345372685167372897439528716008467254138441 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 107.hmac_stress_all_with_rand_reset.80505660557774841232848582910696226345372685167372897439528716008467254138441
Directory /workspace/107.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/108.hmac_stress_all_with_rand_reset.66483649476389802422756727685560173297170812438280837168974834221616387494351
Short name T444
Test name
Test status
Simulation time 80460760838 ps
CPU time 694.56 seconds
Started Nov 22 01:11:10 PM PST 23
Finished Nov 22 01:22:47 PM PST 23
Peak memory 209244 kb
Host smart-bd0495f6-541f-449c-a77e-bdf02a74ae40
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=66483649476389802422756727685560173297170812438280837168974834221616387494351 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 108.hmac_stress_all_with_rand_reset.66483649476389802422756727685560173297170812438280837168974834221616387494351
Directory /workspace/108.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/109.hmac_stress_all_with_rand_reset.22759624179115100951382711110781628324585603877295228783156570910607270331193
Short name T722
Test name
Test status
Simulation time 80460760838 ps
CPU time 707.32 seconds
Started Nov 22 01:11:05 PM PST 23
Finished Nov 22 01:22:54 PM PST 23
Peak memory 209308 kb
Host smart-93447d0e-cade-4761-9e97-f96945134aa7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=22759624179115100951382711110781628324585603877295228783156570910607270331193 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 109.hmac_stress_all_with_rand_reset.22759624179115100951382711110781628324585603877295228783156570910607270331193
Directory /workspace/109.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.hmac_alert_test.85725863689113797245670649250850554676430982705132096562859116887145671347894
Short name T672
Test name
Test status
Simulation time 18011528 ps
CPU time 0.54 seconds
Started Nov 22 01:09:21 PM PST 23
Finished Nov 22 01:09:23 PM PST 23
Peak memory 192884 kb
Host smart-ca85aafc-895a-48ba-abc1-d7350717aa70
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85725863689113797245670649250850554676430982705132096562859116887145671347894 -assert nopostpr
oc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 11.hmac_alert_test.85725863689113797245670649250850554676430982705132096562859116887145671347894
Directory /workspace/11.hmac_alert_test/latest

Test location /workspace/coverage/default/11.hmac_back_pressure.11968015997556759260118715898838808235295127452257826229330012401237249774864
Short name T484
Test name
Test status
Simulation time 2592169506 ps
CPU time 48.29 seconds
Started Nov 22 01:09:29 PM PST 23
Finished Nov 22 01:10:20 PM PST 23
Peak memory 231348 kb
Host smart-601779f4-48bb-491f-826b-d47e5918c22c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=11968015997556759260118715898838808235295127452257826229330012401237249774864 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 11.hmac_back_pressure.11968015997556759260118715898838808235295127452257826229330012401237249774864
Directory /workspace/11.hmac_back_pressure/latest

Test location /workspace/coverage/default/11.hmac_burst_wr.10265314528029318607785347283985880101282918847351490598948588249681717535082
Short name T822
Test name
Test status
Simulation time 4504100639 ps
CPU time 36.51 seconds
Started Nov 22 01:09:30 PM PST 23
Finished Nov 22 01:10:09 PM PST 23
Peak memory 198568 kb
Host smart-18051dae-2bae-4c82-9e94-c47b529c9a72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10265314528029318607785347283985880101282918847351490598948588249681717535082 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.hmac_burst_wr.10265314528029318607785347283985880101282918847351490598948588249681717535082
Directory /workspace/11.hmac_burst_wr/latest

Test location /workspace/coverage/default/11.hmac_datapath_stress.34077921871357563853161179459037524092299331955256769744136303194445438015394
Short name T405
Test name
Test status
Simulation time 4863401336 ps
CPU time 142.36 seconds
Started Nov 22 01:09:25 PM PST 23
Finished Nov 22 01:11:49 PM PST 23
Peak memory 198544 kb
Host smart-3524d17f-97a3-4848-8b1a-499b26fd9ef3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=34077921871357563853161179459037524092299331955256769744136303194445438015394 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 11.hmac_datapath_stress.34077921871357563853161179459037524092299331955256769744136303194445438015394
Directory /workspace/11.hmac_datapath_stress/latest

Test location /workspace/coverage/default/11.hmac_error.104967744770394213674823696623260294592630314846859956421407943684624867951986
Short name T745
Test name
Test status
Simulation time 26556692074 ps
CPU time 200.05 seconds
Started Nov 22 01:09:30 PM PST 23
Finished Nov 22 01:12:53 PM PST 23
Peak memory 198528 kb
Host smart-0e2ef200-6b2f-4eab-8ae9-a5df9dd9753c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104967744770394213674823696623260294592630314846859956421407943684624867951986 -assert nopostproc +UVM_TESTNAME=hmac_bas
e_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 11.hmac_error.104967744770394213674823696623260294592630314846859956421407943684624867951986
Directory /workspace/11.hmac_error/latest

Test location /workspace/coverage/default/11.hmac_long_msg.106027228788837654066914960312416203174824966336436303822935827431592398968568
Short name T385
Test name
Test status
Simulation time 14959266997 ps
CPU time 120.79 seconds
Started Nov 22 01:09:20 PM PST 23
Finished Nov 22 01:11:23 PM PST 23
Peak memory 198592 kb
Host smart-6f6076af-8140-4287-8947-88d9e7cf2c79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106027228788837654066914960312416203174824966336436303822935827431592398968568 -assert nopostproc +UVM_TESTNAME=hmac_bas
e_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 11.hmac_long_msg.106027228788837654066914960312416203174824966336436303822935827431592398968568
Directory /workspace/11.hmac_long_msg/latest

Test location /workspace/coverage/default/11.hmac_smoke.103933992631618870749390124945941138492925407832373800137569933373084193051247
Short name T710
Test name
Test status
Simulation time 631560191 ps
CPU time 4.27 seconds
Started Nov 22 01:09:19 PM PST 23
Finished Nov 22 01:09:25 PM PST 23
Peak memory 198548 kb
Host smart-cadb8460-cf57-45ab-955a-5ac6e26b94aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103933992631618870749390124945941138492925407832373800137569933373084193051247 -assert nopostproc +UVM_TESTNAME=hmac_bas
e_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 11.hmac_smoke.103933992631618870749390124945941138492925407832373800137569933373084193051247
Directory /workspace/11.hmac_smoke/latest

Test location /workspace/coverage/default/11.hmac_stress_all.17071435406742440291895189766200484236217147840845297530310251697899655704809
Short name T456
Test name
Test status
Simulation time 146644856361 ps
CPU time 1099.28 seconds
Started Nov 22 01:09:23 PM PST 23
Finished Nov 22 01:27:44 PM PST 23
Peak memory 210860 kb
Host smart-ff4f542c-f0fc-4014-8a82-02b2b7ce23a1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170714354067424402918951
89766200484236217147840845297530310251697899655704809 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_stress_all.17071435406742440291895
189766200484236217147840845297530310251697899655704809
Directory /workspace/11.hmac_stress_all/latest

Test location /workspace/coverage/default/11.hmac_stress_all_with_rand_reset.114845142511156206758440460912379665263735074499371272983544654786012525664547
Short name T325
Test name
Test status
Simulation time 80460760838 ps
CPU time 718.91 seconds
Started Nov 22 01:09:18 PM PST 23
Finished Nov 22 01:21:18 PM PST 23
Peak memory 209316 kb
Host smart-9784673a-8229-4f4f-b107-e205a424bcfd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=114845142511156206758440460912379665263735074499371272983544654786012525664547 -assert nopostproc +UVM_TE
STNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 11.hmac_stress_all_with_rand_reset.114845142511156206758440460912379665263735074499371272983544654786012525664547
Directory /workspace/11.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.hmac_test_hmac_vectors.44328931190772717910096351388352987048850814139782303210379226609072998368164
Short name T181
Test name
Test status
Simulation time 76314633 ps
CPU time 0.9 seconds
Started Nov 22 01:09:30 PM PST 23
Finished Nov 22 01:09:33 PM PST 23
Peak memory 195776 kb
Host smart-745ac68c-902a-4ed6-92b9-1b7c78b96b65
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44328931190772717910096351388352987048850814139782303
210379226609072998368164 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_test_hmac_vectors.44328931190772717910096351388352987048
850814139782303210379226609072998368164
Directory /workspace/11.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/11.hmac_test_sha_vectors.71686496713069040306843959502598792596234767761959598712976682543511991935362
Short name T843
Test name
Test status
Simulation time 63914107498 ps
CPU time 469.23 seconds
Started Nov 22 01:09:24 PM PST 23
Finished Nov 22 01:17:15 PM PST 23
Peak memory 198456 kb
Host smart-a56c1c56-6d7b-4d1f-867e-ca7d4d7af762
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71686496713069040306843959502598792596234767761959598
712976682543511991935362 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_test_sha_vectors.7168649671306904030684395950259879259623
4767761959598712976682543511991935362
Directory /workspace/11.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/11.hmac_wipe_secret.70203017584238592860477524479983837368827680361962193037779868823714671840127
Short name T210
Test name
Test status
Simulation time 8070750677 ps
CPU time 62.98 seconds
Started Nov 22 01:09:19 PM PST 23
Finished Nov 22 01:10:23 PM PST 23
Peak memory 198584 kb
Host smart-6e48afed-0076-4f10-ad12-4572d5140159
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70203017584238592860477524479983837368827680361962193037779868823714671840127 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 11.hmac_wipe_secret.70203017584238592860477524479983837368827680361962193037779868823714671840127
Directory /workspace/11.hmac_wipe_secret/latest

Test location /workspace/coverage/default/110.hmac_stress_all_with_rand_reset.8374104381472460354867930195238101398228882741141421070358294865189492462996
Short name T475
Test name
Test status
Simulation time 80460760838 ps
CPU time 691.51 seconds
Started Nov 22 01:11:03 PM PST 23
Finished Nov 22 01:22:36 PM PST 23
Peak memory 210308 kb
Host smart-128d39b5-4bdf-414d-9099-544c7c8283fc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=8374104381472460354867930195238101398228882741141421070358294865189492462996 -assert nopostproc +UVM_TEST
NAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 110.hmac_stress_all_with_rand_reset.8374104381472460354867930195238101398228882741141421070358294865189492462996
Directory /workspace/110.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/111.hmac_stress_all_with_rand_reset.110797619609584115350710344891032782634831140990717384870586146197823104805128
Short name T428
Test name
Test status
Simulation time 80460760838 ps
CPU time 712.3 seconds
Started Nov 22 01:11:06 PM PST 23
Finished Nov 22 01:23:00 PM PST 23
Peak memory 209320 kb
Host smart-a7b3c9a9-5ed4-4347-a766-0844035ae6db
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=110797619609584115350710344891032782634831140990717384870586146197823104805128 -assert nopostproc +UVM_TE
STNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 111.hmac_stress_all_with_rand_reset.110797619609584115350710344891032782634831140990717384870586146197823104805128
Directory /workspace/111.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/112.hmac_stress_all_with_rand_reset.66128767296416014202975052150243093974255132395660174772080547296289682982453
Short name T184
Test name
Test status
Simulation time 80460760838 ps
CPU time 705.29 seconds
Started Nov 22 01:11:09 PM PST 23
Finished Nov 22 01:22:56 PM PST 23
Peak memory 209272 kb
Host smart-fa1c8fd8-c41b-4f8a-994a-20dd430743d6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=66128767296416014202975052150243093974255132395660174772080547296289682982453 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 112.hmac_stress_all_with_rand_reset.66128767296416014202975052150243093974255132395660174772080547296289682982453
Directory /workspace/112.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/113.hmac_stress_all_with_rand_reset.7538692814281602257721064293809813130057188225525669417940183999054149608346
Short name T187
Test name
Test status
Simulation time 80460760838 ps
CPU time 716.94 seconds
Started Nov 22 01:11:01 PM PST 23
Finished Nov 22 01:23:00 PM PST 23
Peak memory 210372 kb
Host smart-ab1d3fc6-4661-41e6-a37e-be687620897b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=7538692814281602257721064293809813130057188225525669417940183999054149608346 -assert nopostproc +UVM_TEST
NAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 113.hmac_stress_all_with_rand_reset.7538692814281602257721064293809813130057188225525669417940183999054149608346
Directory /workspace/113.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/114.hmac_stress_all_with_rand_reset.94483366499141598183237222005426219143213613018443788485471900971643576309555
Short name T195
Test name
Test status
Simulation time 80460760838 ps
CPU time 687.47 seconds
Started Nov 22 01:11:05 PM PST 23
Finished Nov 22 01:22:34 PM PST 23
Peak memory 209312 kb
Host smart-d12b69dc-eb23-4ac1-9dde-aeed4551f085
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=94483366499141598183237222005426219143213613018443788485471900971643576309555 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 114.hmac_stress_all_with_rand_reset.94483366499141598183237222005426219143213613018443788485471900971643576309555
Directory /workspace/114.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/115.hmac_stress_all_with_rand_reset.28651764262629612385795594827143931725905455649855197580367084653277393304312
Short name T733
Test name
Test status
Simulation time 80460760838 ps
CPU time 709.12 seconds
Started Nov 22 01:11:08 PM PST 23
Finished Nov 22 01:22:59 PM PST 23
Peak memory 209328 kb
Host smart-03d40dc4-250b-4d8b-918d-253d980dcff0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=28651764262629612385795594827143931725905455649855197580367084653277393304312 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 115.hmac_stress_all_with_rand_reset.28651764262629612385795594827143931725905455649855197580367084653277393304312
Directory /workspace/115.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/116.hmac_stress_all_with_rand_reset.64905657441912895665518366262327815948265665820308838914133763893872867900125
Short name T694
Test name
Test status
Simulation time 80460760838 ps
CPU time 715.32 seconds
Started Nov 22 01:11:08 PM PST 23
Finished Nov 22 01:23:05 PM PST 23
Peak memory 209328 kb
Host smart-ae32ffb6-d3c6-4971-8af6-c7d2249ad42a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=64905657441912895665518366262327815948265665820308838914133763893872867900125 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 116.hmac_stress_all_with_rand_reset.64905657441912895665518366262327815948265665820308838914133763893872867900125
Directory /workspace/116.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/117.hmac_stress_all_with_rand_reset.66807100628617938743986549293133386639728024108439953639423481893871150154197
Short name T228
Test name
Test status
Simulation time 80460760838 ps
CPU time 691.45 seconds
Started Nov 22 01:10:51 PM PST 23
Finished Nov 22 01:22:24 PM PST 23
Peak memory 209316 kb
Host smart-a89e40c9-8d28-4e88-bbf0-284e4cb8bee2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=66807100628617938743986549293133386639728024108439953639423481893871150154197 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 117.hmac_stress_all_with_rand_reset.66807100628617938743986549293133386639728024108439953639423481893871150154197
Directory /workspace/117.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/118.hmac_stress_all_with_rand_reset.48185489391794793339271058183731531413677883458325876127445623947860928266457
Short name T701
Test name
Test status
Simulation time 80460760838 ps
CPU time 694.04 seconds
Started Nov 22 01:11:08 PM PST 23
Finished Nov 22 01:22:43 PM PST 23
Peak memory 209328 kb
Host smart-33493a97-d455-48d5-bffe-440b4b12cbb4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=48185489391794793339271058183731531413677883458325876127445623947860928266457 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 118.hmac_stress_all_with_rand_reset.48185489391794793339271058183731531413677883458325876127445623947860928266457
Directory /workspace/118.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/119.hmac_stress_all_with_rand_reset.7072784103259491869076615775210451427801394441717990008612101142129485381387
Short name T812
Test name
Test status
Simulation time 80460760838 ps
CPU time 687.25 seconds
Started Nov 22 01:11:01 PM PST 23
Finished Nov 22 01:22:30 PM PST 23
Peak memory 210240 kb
Host smart-1be62f50-3a6f-4cf3-9d26-b1a3107f39f9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=7072784103259491869076615775210451427801394441717990008612101142129485381387 -assert nopostproc +UVM_TEST
NAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 119.hmac_stress_all_with_rand_reset.7072784103259491869076615775210451427801394441717990008612101142129485381387
Directory /workspace/119.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.hmac_alert_test.34001662806366750698164799174515614196776042965351253799520066973139118293410
Short name T852
Test name
Test status
Simulation time 18011528 ps
CPU time 0.56 seconds
Started Nov 22 01:09:25 PM PST 23
Finished Nov 22 01:09:27 PM PST 23
Peak memory 192828 kb
Host smart-47f9871e-38af-4c5e-9f9a-629a23f77658
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34001662806366750698164799174515614196776042965351253799520066973139118293410 -assert nopostpr
oc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 12.hmac_alert_test.34001662806366750698164799174515614196776042965351253799520066973139118293410
Directory /workspace/12.hmac_alert_test/latest

Test location /workspace/coverage/default/12.hmac_back_pressure.99426138321156381932690667777958793636982406172726955305155918649813323135707
Short name T747
Test name
Test status
Simulation time 2592169506 ps
CPU time 49.61 seconds
Started Nov 22 01:09:21 PM PST 23
Finished Nov 22 01:10:13 PM PST 23
Peak memory 231368 kb
Host smart-54b220b3-2b79-4283-a974-4a47a5efae6b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=99426138321156381932690667777958793636982406172726955305155918649813323135707 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 12.hmac_back_pressure.99426138321156381932690667777958793636982406172726955305155918649813323135707
Directory /workspace/12.hmac_back_pressure/latest

Test location /workspace/coverage/default/12.hmac_burst_wr.51474529519950433737105461508456236076926428751964611764812825425536205229621
Short name T637
Test name
Test status
Simulation time 4504100639 ps
CPU time 37.19 seconds
Started Nov 22 01:09:21 PM PST 23
Finished Nov 22 01:10:00 PM PST 23
Peak memory 198480 kb
Host smart-291bed9b-849d-4b74-8e6b-7a7b9e71d625
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51474529519950433737105461508456236076926428751964611764812825425536205229621 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.hmac_burst_wr.51474529519950433737105461508456236076926428751964611764812825425536205229621
Directory /workspace/12.hmac_burst_wr/latest

Test location /workspace/coverage/default/12.hmac_datapath_stress.25818208657856991933149278314520409542046804107956527285664465994312792409605
Short name T805
Test name
Test status
Simulation time 4863401336 ps
CPU time 146.78 seconds
Started Nov 22 01:09:29 PM PST 23
Finished Nov 22 01:11:57 PM PST 23
Peak memory 198576 kb
Host smart-3caec42c-8c26-45ad-8517-4d7a828c874f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=25818208657856991933149278314520409542046804107956527285664465994312792409605 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 12.hmac_datapath_stress.25818208657856991933149278314520409542046804107956527285664465994312792409605
Directory /workspace/12.hmac_datapath_stress/latest

Test location /workspace/coverage/default/12.hmac_error.44210358592758602479356557792965477587432313961524069404099113473791147661893
Short name T376
Test name
Test status
Simulation time 26556692074 ps
CPU time 190.14 seconds
Started Nov 22 01:09:18 PM PST 23
Finished Nov 22 01:12:30 PM PST 23
Peak memory 198492 kb
Host smart-e2a6418a-63e6-4958-968d-ab6cfd13fdfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44210358592758602479356557792965477587432313961524069404099113473791147661893 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 12.hmac_error.44210358592758602479356557792965477587432313961524069404099113473791147661893
Directory /workspace/12.hmac_error/latest

Test location /workspace/coverage/default/12.hmac_long_msg.115597797129371236146529168178605596036982901636272090149242688832447774761999
Short name T308
Test name
Test status
Simulation time 14959266997 ps
CPU time 120 seconds
Started Nov 22 01:09:19 PM PST 23
Finished Nov 22 01:11:20 PM PST 23
Peak memory 198564 kb
Host smart-b8ce26c3-d9d4-4101-ae65-3f06ce4d9f61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115597797129371236146529168178605596036982901636272090149242688832447774761999 -assert nopostproc +UVM_TESTNAME=hmac_bas
e_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 12.hmac_long_msg.115597797129371236146529168178605596036982901636272090149242688832447774761999
Directory /workspace/12.hmac_long_msg/latest

Test location /workspace/coverage/default/12.hmac_smoke.1353572839683301165988588020668273847504666291580526927377097035153757318527
Short name T800
Test name
Test status
Simulation time 631560191 ps
CPU time 3.97 seconds
Started Nov 22 01:09:27 PM PST 23
Finished Nov 22 01:09:33 PM PST 23
Peak memory 198560 kb
Host smart-a6e6672d-25d9-4bc5-bfa0-0603105d7f10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1353572839683301165988588020668273847504666291580526927377097035153757318527 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 12.hmac_smoke.1353572839683301165988588020668273847504666291580526927377097035153757318527
Directory /workspace/12.hmac_smoke/latest

Test location /workspace/coverage/default/12.hmac_stress_all.104866088301304188850811645371816041484318292368474339379872360313066630720574
Short name T740
Test name
Test status
Simulation time 146644856361 ps
CPU time 1140.68 seconds
Started Nov 22 01:09:21 PM PST 23
Finished Nov 22 01:28:24 PM PST 23
Peak memory 210852 kb
Host smart-770d9b38-b563-4431-8066-d9986e69a657
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104866088301304188850811
645371816041484318292368474339379872360313066630720574 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_stress_all.1048660883013041888508
11645371816041484318292368474339379872360313066630720574
Directory /workspace/12.hmac_stress_all/latest

Test location /workspace/coverage/default/12.hmac_stress_all_with_rand_reset.21204555091509497125702341822360227348772075280800341920819356877471163277425
Short name T320
Test name
Test status
Simulation time 80460760838 ps
CPU time 707.82 seconds
Started Nov 22 01:09:19 PM PST 23
Finished Nov 22 01:21:09 PM PST 23
Peak memory 209364 kb
Host smart-ae03614b-2c64-4f9a-aed1-633fd2dd68f8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=21204555091509497125702341822360227348772075280800341920819356877471163277425 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 12.hmac_stress_all_with_rand_reset.21204555091509497125702341822360227348772075280800341920819356877471163277425
Directory /workspace/12.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.hmac_test_hmac_vectors.15387289016172572866731238058894816635958337958878070049520797768351250879556
Short name T335
Test name
Test status
Simulation time 76314633 ps
CPU time 0.91 seconds
Started Nov 22 01:09:29 PM PST 23
Finished Nov 22 01:09:32 PM PST 23
Peak memory 195788 kb
Host smart-ad2086f6-7dcc-45c3-9a58-68a4c64124a5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15387289016172572866731238058894816635958337958878070
049520797768351250879556 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_test_hmac_vectors.15387289016172572866731238058894816635
958337958878070049520797768351250879556
Directory /workspace/12.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/12.hmac_test_sha_vectors.33129880031899853174024793056477806834023985934934800199605823577670572224654
Short name T439
Test name
Test status
Simulation time 63914107498 ps
CPU time 448.42 seconds
Started Nov 22 01:09:21 PM PST 23
Finished Nov 22 01:16:51 PM PST 23
Peak memory 198520 kb
Host smart-125a95ea-b1ff-4e3c-93b2-3e5adf136ac6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33129880031899853174024793056477806834023985934934800
199605823577670572224654 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_test_sha_vectors.3312988003189985317402479305647780683402
3985934934800199605823577670572224654
Directory /workspace/12.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/12.hmac_wipe_secret.35563127022921236661296737519703529772727818221259415881562734844322389100452
Short name T557
Test name
Test status
Simulation time 8070750677 ps
CPU time 64.58 seconds
Started Nov 22 01:09:20 PM PST 23
Finished Nov 22 01:10:26 PM PST 23
Peak memory 198604 kb
Host smart-9eef2f63-9542-4bd6-b835-de96e82ed258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35563127022921236661296737519703529772727818221259415881562734844322389100452 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 12.hmac_wipe_secret.35563127022921236661296737519703529772727818221259415881562734844322389100452
Directory /workspace/12.hmac_wipe_secret/latest

Test location /workspace/coverage/default/120.hmac_stress_all_with_rand_reset.38376286622186254586221549874413879373574907530695558910458335936259489798954
Short name T223
Test name
Test status
Simulation time 80460760838 ps
CPU time 707.8 seconds
Started Nov 22 01:11:06 PM PST 23
Finished Nov 22 01:22:56 PM PST 23
Peak memory 209340 kb
Host smart-61b26bc7-4272-467f-ad39-dd309f3f5302
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=38376286622186254586221549874413879373574907530695558910458335936259489798954 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 120.hmac_stress_all_with_rand_reset.38376286622186254586221549874413879373574907530695558910458335936259489798954
Directory /workspace/120.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/121.hmac_stress_all_with_rand_reset.1653035751328373701224045788260034142903951161959160647133423679868626494305
Short name T284
Test name
Test status
Simulation time 80460760838 ps
CPU time 703.95 seconds
Started Nov 22 01:11:02 PM PST 23
Finished Nov 22 01:22:47 PM PST 23
Peak memory 210300 kb
Host smart-f7a1ef82-4064-4a45-9f5d-63a0b30d7963
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1653035751328373701224045788260034142903951161959160647133423679868626494305 -assert nopostproc +UVM_TEST
NAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 121.hmac_stress_all_with_rand_reset.1653035751328373701224045788260034142903951161959160647133423679868626494305
Directory /workspace/121.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/122.hmac_stress_all_with_rand_reset.8468558530320010116314732798970556322347341366132594663555002585913584776768
Short name T615
Test name
Test status
Simulation time 80460760838 ps
CPU time 673.03 seconds
Started Nov 22 01:11:08 PM PST 23
Finished Nov 22 01:22:22 PM PST 23
Peak memory 210192 kb
Host smart-d03aad0b-bf3f-44bb-a8a6-a5d511a32871
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=8468558530320010116314732798970556322347341366132594663555002585913584776768 -assert nopostproc +UVM_TEST
NAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 122.hmac_stress_all_with_rand_reset.8468558530320010116314732798970556322347341366132594663555002585913584776768
Directory /workspace/122.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/123.hmac_stress_all_with_rand_reset.102590549922966257737701121597283261587812231869426748817198947611264902287393
Short name T798
Test name
Test status
Simulation time 80460760838 ps
CPU time 697.41 seconds
Started Nov 22 01:11:05 PM PST 23
Finished Nov 22 01:22:44 PM PST 23
Peak memory 209236 kb
Host smart-bbb5f678-517f-46cf-8bb3-c2a736d03ab1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=102590549922966257737701121597283261587812231869426748817198947611264902287393 -assert nopostproc +UVM_TE
STNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 123.hmac_stress_all_with_rand_reset.102590549922966257737701121597283261587812231869426748817198947611264902287393
Directory /workspace/123.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/124.hmac_stress_all_with_rand_reset.15835848902064490078105697846178038735444543983656186453449141290710487616035
Short name T280
Test name
Test status
Simulation time 80460760838 ps
CPU time 731.03 seconds
Started Nov 22 01:10:54 PM PST 23
Finished Nov 22 01:23:08 PM PST 23
Peak memory 209312 kb
Host smart-9e3bf866-7a0c-433f-a840-f1c120f39f07
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=15835848902064490078105697846178038735444543983656186453449141290710487616035 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 124.hmac_stress_all_with_rand_reset.15835848902064490078105697846178038735444543983656186453449141290710487616035
Directory /workspace/124.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/125.hmac_stress_all_with_rand_reset.48004020841086152856660497456433117838262068437090469528979681043814199939198
Short name T494
Test name
Test status
Simulation time 80460760838 ps
CPU time 688.78 seconds
Started Nov 22 01:11:04 PM PST 23
Finished Nov 22 01:22:35 PM PST 23
Peak memory 209312 kb
Host smart-47de1cd2-3f5b-44d0-8199-2f309771afd5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=48004020841086152856660497456433117838262068437090469528979681043814199939198 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 125.hmac_stress_all_with_rand_reset.48004020841086152856660497456433117838262068437090469528979681043814199939198
Directory /workspace/125.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/126.hmac_stress_all_with_rand_reset.112331177722660680372331641777271033931665453303153001669744284043124625899975
Short name T404
Test name
Test status
Simulation time 80460760838 ps
CPU time 701.85 seconds
Started Nov 22 01:11:05 PM PST 23
Finished Nov 22 01:22:49 PM PST 23
Peak memory 209348 kb
Host smart-28a55e2e-ef8b-47b8-94aa-1bb5f53b5f2a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=112331177722660680372331641777271033931665453303153001669744284043124625899975 -assert nopostproc +UVM_TE
STNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 126.hmac_stress_all_with_rand_reset.112331177722660680372331641777271033931665453303153001669744284043124625899975
Directory /workspace/126.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/127.hmac_stress_all_with_rand_reset.36221064625715261721338155714197528807533191035592666407920048139313746791848
Short name T424
Test name
Test status
Simulation time 80460760838 ps
CPU time 730.07 seconds
Started Nov 22 01:11:03 PM PST 23
Finished Nov 22 01:23:15 PM PST 23
Peak memory 209288 kb
Host smart-771fba90-e617-463f-b0d0-8430b0fe9b0e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=36221064625715261721338155714197528807533191035592666407920048139313746791848 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 127.hmac_stress_all_with_rand_reset.36221064625715261721338155714197528807533191035592666407920048139313746791848
Directory /workspace/127.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/128.hmac_stress_all_with_rand_reset.100064270545057055901735254845140753694990645706625574145710468219612228382998
Short name T233
Test name
Test status
Simulation time 80460760838 ps
CPU time 706.35 seconds
Started Nov 22 01:11:06 PM PST 23
Finished Nov 22 01:22:55 PM PST 23
Peak memory 209340 kb
Host smart-05a48bd6-0072-487d-ad83-6ab705bb771f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=100064270545057055901735254845140753694990645706625574145710468219612228382998 -assert nopostproc +UVM_TE
STNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 128.hmac_stress_all_with_rand_reset.100064270545057055901735254845140753694990645706625574145710468219612228382998
Directory /workspace/128.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/129.hmac_stress_all_with_rand_reset.13066889819729301370002444402459470699714749722702893771462602982867217183853
Short name T278
Test name
Test status
Simulation time 80460760838 ps
CPU time 696.94 seconds
Started Nov 22 01:11:04 PM PST 23
Finished Nov 22 01:22:42 PM PST 23
Peak memory 209168 kb
Host smart-728cfe03-c911-4c2a-8d0d-f5fcf140f0c0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=13066889819729301370002444402459470699714749722702893771462602982867217183853 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 129.hmac_stress_all_with_rand_reset.13066889819729301370002444402459470699714749722702893771462602982867217183853
Directory /workspace/129.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.hmac_alert_test.75906308292552899334234284830982334253329010578881330176907124155859130974339
Short name T833
Test name
Test status
Simulation time 18011528 ps
CPU time 0.54 seconds
Started Nov 22 01:09:29 PM PST 23
Finished Nov 22 01:09:30 PM PST 23
Peak memory 192852 kb
Host smart-754c9fa5-04ed-45a6-945d-46249b5189d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75906308292552899334234284830982334253329010578881330176907124155859130974339 -assert nopostpr
oc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 13.hmac_alert_test.75906308292552899334234284830982334253329010578881330176907124155859130974339
Directory /workspace/13.hmac_alert_test/latest

Test location /workspace/coverage/default/13.hmac_burst_wr.45462541665561184655781759180334611057905457173379615206027391960315973751490
Short name T656
Test name
Test status
Simulation time 4504100639 ps
CPU time 37.31 seconds
Started Nov 22 01:09:29 PM PST 23
Finished Nov 22 01:10:07 PM PST 23
Peak memory 198564 kb
Host smart-18c643a8-5737-42f4-ad7c-21f8e496ab70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45462541665561184655781759180334611057905457173379615206027391960315973751490 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.hmac_burst_wr.45462541665561184655781759180334611057905457173379615206027391960315973751490
Directory /workspace/13.hmac_burst_wr/latest

Test location /workspace/coverage/default/13.hmac_datapath_stress.86289224469977078437745726713192756781927812227660281912402912612526799992819
Short name T504
Test name
Test status
Simulation time 4863401336 ps
CPU time 143.72 seconds
Started Nov 22 01:09:20 PM PST 23
Finished Nov 22 01:11:45 PM PST 23
Peak memory 198608 kb
Host smart-5ea4f54c-af35-4520-82fa-088671d123a0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=86289224469977078437745726713192756781927812227660281912402912612526799992819 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 13.hmac_datapath_stress.86289224469977078437745726713192756781927812227660281912402912612526799992819
Directory /workspace/13.hmac_datapath_stress/latest

Test location /workspace/coverage/default/13.hmac_error.51570435746740482348069717562610948261041281838974332810886529367891911923795
Short name T437
Test name
Test status
Simulation time 26556692074 ps
CPU time 189.19 seconds
Started Nov 22 01:09:28 PM PST 23
Finished Nov 22 01:12:38 PM PST 23
Peak memory 198584 kb
Host smart-f4386f48-fb56-4d35-ab26-797f44e7f874
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51570435746740482348069717562610948261041281838974332810886529367891911923795 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 13.hmac_error.51570435746740482348069717562610948261041281838974332810886529367891911923795
Directory /workspace/13.hmac_error/latest

Test location /workspace/coverage/default/13.hmac_long_msg.102085009128140228272223186526512299176664385939033718769531101828478029162125
Short name T442
Test name
Test status
Simulation time 14959266997 ps
CPU time 119.58 seconds
Started Nov 22 01:09:28 PM PST 23
Finished Nov 22 01:11:28 PM PST 23
Peak memory 198536 kb
Host smart-fd2dc7ae-1f57-46b4-a1aa-23d503eb1530
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102085009128140228272223186526512299176664385939033718769531101828478029162125 -assert nopostproc +UVM_TESTNAME=hmac_bas
e_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 13.hmac_long_msg.102085009128140228272223186526512299176664385939033718769531101828478029162125
Directory /workspace/13.hmac_long_msg/latest

Test location /workspace/coverage/default/13.hmac_smoke.39997722140928374623803313663621976441673339075701655615492318333202501403488
Short name T635
Test name
Test status
Simulation time 631560191 ps
CPU time 4.08 seconds
Started Nov 22 01:09:27 PM PST 23
Finished Nov 22 01:09:32 PM PST 23
Peak memory 198560 kb
Host smart-f1e2d599-1b55-4e0e-88b6-e14df29a9a80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39997722140928374623803313663621976441673339075701655615492318333202501403488 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 13.hmac_smoke.39997722140928374623803313663621976441673339075701655615492318333202501403488
Directory /workspace/13.hmac_smoke/latest

Test location /workspace/coverage/default/13.hmac_stress_all.102018532095704025316842806644898137532503964400658844156118909388466258169256
Short name T872
Test name
Test status
Simulation time 146644856361 ps
CPU time 1162.13 seconds
Started Nov 22 01:09:31 PM PST 23
Finished Nov 22 01:28:56 PM PST 23
Peak memory 210820 kb
Host smart-47d252ef-5a26-4ac7-9337-a85d1aada17c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102018532095704025316842
806644898137532503964400658844156118909388466258169256 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_stress_all.1020185320957040253168
42806644898137532503964400658844156118909388466258169256
Directory /workspace/13.hmac_stress_all/latest

Test location /workspace/coverage/default/13.hmac_stress_all_with_rand_reset.6951666156141912917871724809193461887207335359635779315335070486873720067378
Short name T6
Test name
Test status
Simulation time 80460760838 ps
CPU time 721.66 seconds
Started Nov 22 01:09:21 PM PST 23
Finished Nov 22 01:21:25 PM PST 23
Peak memory 210260 kb
Host smart-dd8a1328-c229-4e41-8eb3-9605e02f1912
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=6951666156141912917871724809193461887207335359635779315335070486873720067378 -assert nopostproc +UVM_TEST
NAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 13.hmac_stress_all_with_rand_reset.6951666156141912917871724809193461887207335359635779315335070486873720067378
Directory /workspace/13.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.hmac_test_hmac_vectors.36793374376801561832441542019093233404373707609698573960583059330101214535929
Short name T446
Test name
Test status
Simulation time 76314633 ps
CPU time 0.9 seconds
Started Nov 22 01:09:30 PM PST 23
Finished Nov 22 01:09:34 PM PST 23
Peak memory 195776 kb
Host smart-408dff10-6ae5-4367-a111-119f8dacda30
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36793374376801561832441542019093233404373707609698573
960583059330101214535929 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_test_hmac_vectors.36793374376801561832441542019093233404
373707609698573960583059330101214535929
Directory /workspace/13.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/13.hmac_test_sha_vectors.80948429587913452740817999271318027712637436277120677768838390813208723211290
Short name T507
Test name
Test status
Simulation time 63914107498 ps
CPU time 448.54 seconds
Started Nov 22 01:09:29 PM PST 23
Finished Nov 22 01:17:00 PM PST 23
Peak memory 198556 kb
Host smart-22a2416e-2e09-4a55-bf65-71e85873def4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80948429587913452740817999271318027712637436277120677
768838390813208723211290 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_test_sha_vectors.8094842958791345274081799927131802771263
7436277120677768838390813208723211290
Directory /workspace/13.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/13.hmac_wipe_secret.88232294437472459740175587788648457659868848832771526887565625727908483062102
Short name T626
Test name
Test status
Simulation time 8070750677 ps
CPU time 64.3 seconds
Started Nov 22 01:09:31 PM PST 23
Finished Nov 22 01:10:38 PM PST 23
Peak memory 198604 kb
Host smart-e9a5095b-0adb-428e-8f84-2fd8771d7ea3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88232294437472459740175587788648457659868848832771526887565625727908483062102 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 13.hmac_wipe_secret.88232294437472459740175587788648457659868848832771526887565625727908483062102
Directory /workspace/13.hmac_wipe_secret/latest

Test location /workspace/coverage/default/130.hmac_stress_all_with_rand_reset.11658108127672485575041372405035253938052668003578493982061962901376793281291
Short name T179
Test name
Test status
Simulation time 80460760838 ps
CPU time 701.84 seconds
Started Nov 22 01:11:04 PM PST 23
Finished Nov 22 01:22:47 PM PST 23
Peak memory 209320 kb
Host smart-3299a0e5-5686-47a4-8932-1e2ed93958c5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=11658108127672485575041372405035253938052668003578493982061962901376793281291 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 130.hmac_stress_all_with_rand_reset.11658108127672485575041372405035253938052668003578493982061962901376793281291
Directory /workspace/130.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/131.hmac_stress_all_with_rand_reset.26565344020905010968104015529892113825254712375628266082425717393980949058336
Short name T241
Test name
Test status
Simulation time 80460760838 ps
CPU time 737 seconds
Started Nov 22 01:11:11 PM PST 23
Finished Nov 22 01:23:31 PM PST 23
Peak memory 209340 kb
Host smart-957c5733-a1bc-40af-b12b-7282529b66b6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=26565344020905010968104015529892113825254712375628266082425717393980949058336 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 131.hmac_stress_all_with_rand_reset.26565344020905010968104015529892113825254712375628266082425717393980949058336
Directory /workspace/131.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/132.hmac_stress_all_with_rand_reset.97302324210465604280143641483614295956306215340467611560350862082852544802826
Short name T52
Test name
Test status
Simulation time 80460760838 ps
CPU time 730.31 seconds
Started Nov 22 01:11:11 PM PST 23
Finished Nov 22 01:23:24 PM PST 23
Peak memory 209340 kb
Host smart-3ac03573-54cd-4bba-a72c-c1fc02e8068c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=97302324210465604280143641483614295956306215340467611560350862082852544802826 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 132.hmac_stress_all_with_rand_reset.97302324210465604280143641483614295956306215340467611560350862082852544802826
Directory /workspace/132.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/133.hmac_stress_all_with_rand_reset.108503910190844831334282210832110009462149900083264276641451114708627243329387
Short name T49
Test name
Test status
Simulation time 80460760838 ps
CPU time 720.61 seconds
Started Nov 22 01:11:06 PM PST 23
Finished Nov 22 01:23:09 PM PST 23
Peak memory 209364 kb
Host smart-09d7ecb5-01ce-46cf-ab3c-7b89f759c494
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=108503910190844831334282210832110009462149900083264276641451114708627243329387 -assert nopostproc +UVM_TE
STNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 133.hmac_stress_all_with_rand_reset.108503910190844831334282210832110009462149900083264276641451114708627243329387
Directory /workspace/133.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/134.hmac_stress_all_with_rand_reset.114551442560547536292791353809870438311507963389219223390119531453928769975938
Short name T631
Test name
Test status
Simulation time 80460760838 ps
CPU time 722.55 seconds
Started Nov 22 01:11:11 PM PST 23
Finished Nov 22 01:23:16 PM PST 23
Peak memory 209340 kb
Host smart-bb04e266-8625-4e3e-a7a0-fde0db6788cd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=114551442560547536292791353809870438311507963389219223390119531453928769975938 -assert nopostproc +UVM_TE
STNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 134.hmac_stress_all_with_rand_reset.114551442560547536292791353809870438311507963389219223390119531453928769975938
Directory /workspace/134.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/135.hmac_stress_all_with_rand_reset.92566146347289340022618869537670709719893391314998923493816461969528740751797
Short name T688
Test name
Test status
Simulation time 80460760838 ps
CPU time 707.43 seconds
Started Nov 22 01:11:11 PM PST 23
Finished Nov 22 01:23:01 PM PST 23
Peak memory 209312 kb
Host smart-f8264007-b6ef-44fc-a030-bea313453710
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=92566146347289340022618869537670709719893391314998923493816461969528740751797 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 135.hmac_stress_all_with_rand_reset.92566146347289340022618869537670709719893391314998923493816461969528740751797
Directory /workspace/135.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/136.hmac_stress_all_with_rand_reset.109245218595707176063294709979648483200560174164614386523613350465236803909527
Short name T850
Test name
Test status
Simulation time 80460760838 ps
CPU time 725.36 seconds
Started Nov 22 01:11:14 PM PST 23
Finished Nov 22 01:23:21 PM PST 23
Peak memory 209340 kb
Host smart-abf9d58c-3ee7-45df-b96c-188c0c46142a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=109245218595707176063294709979648483200560174164614386523613350465236803909527 -assert nopostproc +UVM_TE
STNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 136.hmac_stress_all_with_rand_reset.109245218595707176063294709979648483200560174164614386523613350465236803909527
Directory /workspace/136.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/137.hmac_stress_all_with_rand_reset.56863583648845268523885642308711054271758202613284992327266039558848105248959
Short name T568
Test name
Test status
Simulation time 80460760838 ps
CPU time 685.99 seconds
Started Nov 22 01:10:41 PM PST 23
Finished Nov 22 01:22:08 PM PST 23
Peak memory 209336 kb
Host smart-cbdd3708-2afc-4587-a74a-b812164a947b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=56863583648845268523885642308711054271758202613284992327266039558848105248959 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 137.hmac_stress_all_with_rand_reset.56863583648845268523885642308711054271758202613284992327266039558848105248959
Directory /workspace/137.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/138.hmac_stress_all_with_rand_reset.103534219792562422875210802551762609216037747228027888956938425372699786935648
Short name T371
Test name
Test status
Simulation time 80460760838 ps
CPU time 736.75 seconds
Started Nov 22 01:11:06 PM PST 23
Finished Nov 22 01:23:25 PM PST 23
Peak memory 209364 kb
Host smart-cb9b5b06-a7fb-45a8-bb7b-00450b467d9e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=103534219792562422875210802551762609216037747228027888956938425372699786935648 -assert nopostproc +UVM_TE
STNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 138.hmac_stress_all_with_rand_reset.103534219792562422875210802551762609216037747228027888956938425372699786935648
Directory /workspace/138.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/139.hmac_stress_all_with_rand_reset.8139238451061847083370675630401565263004310189633327938198665800872559053125
Short name T725
Test name
Test status
Simulation time 80460760838 ps
CPU time 703.5 seconds
Started Nov 22 01:11:05 PM PST 23
Finished Nov 22 01:22:51 PM PST 23
Peak memory 210344 kb
Host smart-88bcc72c-bd65-40cc-8183-3bb7489a1bba
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=8139238451061847083370675630401565263004310189633327938198665800872559053125 -assert nopostproc +UVM_TEST
NAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 139.hmac_stress_all_with_rand_reset.8139238451061847083370675630401565263004310189633327938198665800872559053125
Directory /workspace/139.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.hmac_alert_test.99086301340646442561933542242016396406915800835146072411420357128950125137006
Short name T516
Test name
Test status
Simulation time 18011528 ps
CPU time 0.55 seconds
Started Nov 22 01:09:29 PM PST 23
Finished Nov 22 01:09:32 PM PST 23
Peak memory 192856 kb
Host smart-8e132306-b089-49d8-ac0b-968d67dfbf47
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99086301340646442561933542242016396406915800835146072411420357128950125137006 -assert nopostpr
oc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 14.hmac_alert_test.99086301340646442561933542242016396406915800835146072411420357128950125137006
Directory /workspace/14.hmac_alert_test/latest

Test location /workspace/coverage/default/14.hmac_back_pressure.41281909892222649240868081662481391883331031979445771144518482124663267244276
Short name T653
Test name
Test status
Simulation time 2592169506 ps
CPU time 47.74 seconds
Started Nov 22 01:09:28 PM PST 23
Finished Nov 22 01:10:17 PM PST 23
Peak memory 231360 kb
Host smart-22e6cb6f-6bd6-4405-8965-19151a93304e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=41281909892222649240868081662481391883331031979445771144518482124663267244276 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 14.hmac_back_pressure.41281909892222649240868081662481391883331031979445771144518482124663267244276
Directory /workspace/14.hmac_back_pressure/latest

Test location /workspace/coverage/default/14.hmac_burst_wr.40036890709270681742604705040099343626309657283005528413385505867967903900940
Short name T556
Test name
Test status
Simulation time 4504100639 ps
CPU time 37.89 seconds
Started Nov 22 01:09:22 PM PST 23
Finished Nov 22 01:10:02 PM PST 23
Peak memory 198548 kb
Host smart-1d552924-c240-431b-9c9c-20c002b78ce2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40036890709270681742604705040099343626309657283005528413385505867967903900940 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.hmac_burst_wr.40036890709270681742604705040099343626309657283005528413385505867967903900940
Directory /workspace/14.hmac_burst_wr/latest

Test location /workspace/coverage/default/14.hmac_datapath_stress.11358091679260950339192035451898643826882054160565891692942180174670201757548
Short name T240
Test name
Test status
Simulation time 4863401336 ps
CPU time 143.59 seconds
Started Nov 22 01:09:30 PM PST 23
Finished Nov 22 01:11:57 PM PST 23
Peak memory 198580 kb
Host smart-af899603-3e79-40bf-90a0-2224e62ad115
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=11358091679260950339192035451898643826882054160565891692942180174670201757548 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 14.hmac_datapath_stress.11358091679260950339192035451898643826882054160565891692942180174670201757548
Directory /workspace/14.hmac_datapath_stress/latest

Test location /workspace/coverage/default/14.hmac_error.98204851899624279774957266101058368521179858902697858740929790228898275407697
Short name T737
Test name
Test status
Simulation time 26556692074 ps
CPU time 184.89 seconds
Started Nov 22 01:09:29 PM PST 23
Finished Nov 22 01:12:36 PM PST 23
Peak memory 198584 kb
Host smart-2d189abb-e761-4858-828c-965a26816335
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98204851899624279774957266101058368521179858902697858740929790228898275407697 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 14.hmac_error.98204851899624279774957266101058368521179858902697858740929790228898275407697
Directory /workspace/14.hmac_error/latest

Test location /workspace/coverage/default/14.hmac_long_msg.107788496538436070511102719927951541143364641320440605752414973246751166570223
Short name T498
Test name
Test status
Simulation time 14959266997 ps
CPU time 118.88 seconds
Started Nov 22 01:09:30 PM PST 23
Finished Nov 22 01:11:32 PM PST 23
Peak memory 198564 kb
Host smart-2479524e-c519-4d50-88f1-95f6e641dda0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107788496538436070511102719927951541143364641320440605752414973246751166570223 -assert nopostproc +UVM_TESTNAME=hmac_bas
e_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 14.hmac_long_msg.107788496538436070511102719927951541143364641320440605752414973246751166570223
Directory /workspace/14.hmac_long_msg/latest

Test location /workspace/coverage/default/14.hmac_smoke.44347017904769033177385131749930270968216758540201342197933977980771697544981
Short name T337
Test name
Test status
Simulation time 631560191 ps
CPU time 3.99 seconds
Started Nov 22 01:09:27 PM PST 23
Finished Nov 22 01:09:32 PM PST 23
Peak memory 198560 kb
Host smart-272ac305-0920-4b9e-91b2-209c5ae4c067
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44347017904769033177385131749930270968216758540201342197933977980771697544981 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 14.hmac_smoke.44347017904769033177385131749930270968216758540201342197933977980771697544981
Directory /workspace/14.hmac_smoke/latest

Test location /workspace/coverage/default/14.hmac_stress_all.46349640607441239259255510243689095529165902787217669906064256675367788030441
Short name T777
Test name
Test status
Simulation time 146644856361 ps
CPU time 1145.98 seconds
Started Nov 22 01:09:24 PM PST 23
Finished Nov 22 01:28:32 PM PST 23
Peak memory 210840 kb
Host smart-051ce005-30b4-4f11-b01a-85e2f7020edb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463496406074412392592555
10243689095529165902787217669906064256675367788030441 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_stress_all.46349640607441239259255
510243689095529165902787217669906064256675367788030441
Directory /workspace/14.hmac_stress_all/latest

Test location /workspace/coverage/default/14.hmac_stress_all_with_rand_reset.16909355127749676785996058270760151764090319463588749154920948113420407856682
Short name T326
Test name
Test status
Simulation time 80460760838 ps
CPU time 692.41 seconds
Started Nov 22 01:09:23 PM PST 23
Finished Nov 22 01:20:58 PM PST 23
Peak memory 209176 kb
Host smart-f5028d26-0c43-4a04-a7fb-763852a0a52f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=16909355127749676785996058270760151764090319463588749154920948113420407856682 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 14.hmac_stress_all_with_rand_reset.16909355127749676785996058270760151764090319463588749154920948113420407856682
Directory /workspace/14.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.hmac_test_hmac_vectors.86186902700047130533863067364349072185778403319783872541853599780018797532245
Short name T303
Test name
Test status
Simulation time 76314633 ps
CPU time 0.9 seconds
Started Nov 22 01:09:21 PM PST 23
Finished Nov 22 01:09:24 PM PST 23
Peak memory 195780 kb
Host smart-f5ead460-0238-4de5-970b-771a09f2e097
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86186902700047130533863067364349072185778403319783872
541853599780018797532245 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_test_hmac_vectors.86186902700047130533863067364349072185
778403319783872541853599780018797532245
Directory /workspace/14.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/14.hmac_test_sha_vectors.11159985847292628020859028952578776399548247356596351798427147203166865136173
Short name T423
Test name
Test status
Simulation time 63914107498 ps
CPU time 459.64 seconds
Started Nov 22 01:09:24 PM PST 23
Finished Nov 22 01:17:05 PM PST 23
Peak memory 198388 kb
Host smart-5ea1acc9-12b1-4e82-8360-a743519bc935
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11159985847292628020859028952578776399548247356596351
798427147203166865136173 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_test_sha_vectors.1115998584729262802085902895257877639954
8247356596351798427147203166865136173
Directory /workspace/14.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/14.hmac_wipe_secret.35894823568399969880663503730452880662106667347948496794743480368306121368759
Short name T314
Test name
Test status
Simulation time 8070750677 ps
CPU time 62.71 seconds
Started Nov 22 01:09:30 PM PST 23
Finished Nov 22 01:10:36 PM PST 23
Peak memory 198572 kb
Host smart-50af7148-eb03-4d6a-b96e-8643051a485e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35894823568399969880663503730452880662106667347948496794743480368306121368759 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 14.hmac_wipe_secret.35894823568399969880663503730452880662106667347948496794743480368306121368759
Directory /workspace/14.hmac_wipe_secret/latest

Test location /workspace/coverage/default/140.hmac_stress_all_with_rand_reset.88389226014706121810085725526422730626770052490929740542951868293273789648045
Short name T857
Test name
Test status
Simulation time 80460760838 ps
CPU time 726.7 seconds
Started Nov 22 01:10:44 PM PST 23
Finished Nov 22 01:22:52 PM PST 23
Peak memory 209308 kb
Host smart-c498b000-0e54-49b3-99f4-9541930613f1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=88389226014706121810085725526422730626770052490929740542951868293273789648045 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 140.hmac_stress_all_with_rand_reset.88389226014706121810085725526422730626770052490929740542951868293273789648045
Directory /workspace/140.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/141.hmac_stress_all_with_rand_reset.100406172053337651635038215044930946171842092037377832569758656195011136903698
Short name T611
Test name
Test status
Simulation time 80460760838 ps
CPU time 727.99 seconds
Started Nov 22 01:11:06 PM PST 23
Finished Nov 22 01:23:16 PM PST 23
Peak memory 209368 kb
Host smart-4c3696d2-9b79-4a5c-8f2c-bcb26ee3045b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=100406172053337651635038215044930946171842092037377832569758656195011136903698 -assert nopostproc +UVM_TE
STNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 141.hmac_stress_all_with_rand_reset.100406172053337651635038215044930946171842092037377832569758656195011136903698
Directory /workspace/141.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/142.hmac_stress_all_with_rand_reset.74237467150492611892545481902474612440788141757298788491196909324156065684370
Short name T393
Test name
Test status
Simulation time 80460760838 ps
CPU time 737.75 seconds
Started Nov 22 01:11:02 PM PST 23
Finished Nov 22 01:23:21 PM PST 23
Peak memory 209324 kb
Host smart-e8689865-a6ce-49a3-ab6d-9c934dd349fb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=74237467150492611892545481902474612440788141757298788491196909324156065684370 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 142.hmac_stress_all_with_rand_reset.74237467150492611892545481902474612440788141757298788491196909324156065684370
Directory /workspace/142.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/143.hmac_stress_all_with_rand_reset.5466957646941995126295371556842223497536995110517533430595514144213282497509
Short name T870
Test name
Test status
Simulation time 80460760838 ps
CPU time 720.8 seconds
Started Nov 22 01:10:45 PM PST 23
Finished Nov 22 01:22:48 PM PST 23
Peak memory 210348 kb
Host smart-561c22c5-f765-4d19-9ce9-479e9055fa51
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=5466957646941995126295371556842223497536995110517533430595514144213282497509 -assert nopostproc +UVM_TEST
NAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 143.hmac_stress_all_with_rand_reset.5466957646941995126295371556842223497536995110517533430595514144213282497509
Directory /workspace/143.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/144.hmac_stress_all_with_rand_reset.110077934411808769670081325483596421120586763287340145903741697974685709904583
Short name T305
Test name
Test status
Simulation time 80460760838 ps
CPU time 694.79 seconds
Started Nov 22 01:10:44 PM PST 23
Finished Nov 22 01:22:20 PM PST 23
Peak memory 209368 kb
Host smart-7b716c71-fb61-42c3-a989-cb4a0dcdd8aa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=110077934411808769670081325483596421120586763287340145903741697974685709904583 -assert nopostproc +UVM_TE
STNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 144.hmac_stress_all_with_rand_reset.110077934411808769670081325483596421120586763287340145903741697974685709904583
Directory /workspace/144.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/145.hmac_stress_all_with_rand_reset.36606253377350086481303739371691239865792798266236881427092095277398355849672
Short name T227
Test name
Test status
Simulation time 80460760838 ps
CPU time 740.81 seconds
Started Nov 22 01:10:47 PM PST 23
Finished Nov 22 01:23:09 PM PST 23
Peak memory 209308 kb
Host smart-e08efc22-66f7-4a9c-9189-2652e47ba0e4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=36606253377350086481303739371691239865792798266236881427092095277398355849672 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 145.hmac_stress_all_with_rand_reset.36606253377350086481303739371691239865792798266236881427092095277398355849672
Directory /workspace/145.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/146.hmac_stress_all_with_rand_reset.9260510841103521383286436715668725724477848260650241477760141177701946558622
Short name T323
Test name
Test status
Simulation time 80460760838 ps
CPU time 706.52 seconds
Started Nov 22 01:10:42 PM PST 23
Finished Nov 22 01:22:30 PM PST 23
Peak memory 210352 kb
Host smart-6a507187-a744-4498-aa8e-f39bd98892da
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=9260510841103521383286436715668725724477848260650241477760141177701946558622 -assert nopostproc +UVM_TEST
NAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 146.hmac_stress_all_with_rand_reset.9260510841103521383286436715668725724477848260650241477760141177701946558622
Directory /workspace/146.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/147.hmac_stress_all_with_rand_reset.101952507453985820795515005250381917619622927702540842666207689053736857912646
Short name T767
Test name
Test status
Simulation time 80460760838 ps
CPU time 704.82 seconds
Started Nov 22 01:11:09 PM PST 23
Finished Nov 22 01:22:56 PM PST 23
Peak memory 209264 kb
Host smart-e61eb978-8127-4287-bac7-6c74825cbb7b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=101952507453985820795515005250381917619622927702540842666207689053736857912646 -assert nopostproc +UVM_TE
STNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 147.hmac_stress_all_with_rand_reset.101952507453985820795515005250381917619622927702540842666207689053736857912646
Directory /workspace/147.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/148.hmac_stress_all_with_rand_reset.82175155589357674024651347955883131652124189513474138228016916308865713798011
Short name T363
Test name
Test status
Simulation time 80460760838 ps
CPU time 703.28 seconds
Started Nov 22 01:10:49 PM PST 23
Finished Nov 22 01:22:33 PM PST 23
Peak memory 209328 kb
Host smart-bc69ffff-a025-42c8-ac90-08f083abe430
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=82175155589357674024651347955883131652124189513474138228016916308865713798011 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 148.hmac_stress_all_with_rand_reset.82175155589357674024651347955883131652124189513474138228016916308865713798011
Directory /workspace/148.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/149.hmac_stress_all_with_rand_reset.6168924021673896718458669233705953357918971939941520384907790589847181571845
Short name T616
Test name
Test status
Simulation time 80460760838 ps
CPU time 706.2 seconds
Started Nov 22 01:10:51 PM PST 23
Finished Nov 22 01:22:39 PM PST 23
Peak memory 210256 kb
Host smart-2324a341-9f3c-42dc-a0ec-5cefa73575dd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=6168924021673896718458669233705953357918971939941520384907790589847181571845 -assert nopostproc +UVM_TEST
NAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 149.hmac_stress_all_with_rand_reset.6168924021673896718458669233705953357918971939941520384907790589847181571845
Directory /workspace/149.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.hmac_alert_test.66619410238565576280501017211748876898997784806055474844613234253175008733601
Short name T553
Test name
Test status
Simulation time 18011528 ps
CPU time 0.56 seconds
Started Nov 22 01:09:46 PM PST 23
Finished Nov 22 01:09:49 PM PST 23
Peak memory 192856 kb
Host smart-af44d821-19f5-4dd7-81fa-b09c68246f51
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66619410238565576280501017211748876898997784806055474844613234253175008733601 -assert nopostpr
oc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 15.hmac_alert_test.66619410238565576280501017211748876898997784806055474844613234253175008733601
Directory /workspace/15.hmac_alert_test/latest

Test location /workspace/coverage/default/15.hmac_back_pressure.13691133115281558971141359749043174106291212726711432937573206928039232813540
Short name T558
Test name
Test status
Simulation time 2592169506 ps
CPU time 46.81 seconds
Started Nov 22 01:09:23 PM PST 23
Finished Nov 22 01:10:11 PM PST 23
Peak memory 231192 kb
Host smart-88ba2d02-2ff6-4c00-b34d-af3070fdfb86
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=13691133115281558971141359749043174106291212726711432937573206928039232813540 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 15.hmac_back_pressure.13691133115281558971141359749043174106291212726711432937573206928039232813540
Directory /workspace/15.hmac_back_pressure/latest

Test location /workspace/coverage/default/15.hmac_burst_wr.113927135152888543656997587148090654974706284012966311121625715139704239655930
Short name T215
Test name
Test status
Simulation time 4504100639 ps
CPU time 37.82 seconds
Started Nov 22 01:09:54 PM PST 23
Finished Nov 22 01:10:33 PM PST 23
Peak memory 198536 kb
Host smart-16a18df1-d251-48a9-82e4-6e51a47d4359
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113927135152888543656997587148090654974706284012966311121625715139704239655930 -assert nopostproc +UVM_TESTNAME=hmac_bas
e_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 15.hmac_burst_wr.113927135152888543656997587148090654974706284012966311121625715139704239655930
Directory /workspace/15.hmac_burst_wr/latest

Test location /workspace/coverage/default/15.hmac_datapath_stress.20752835167692513561740457730783921746135374272469481963687665455255734261078
Short name T624
Test name
Test status
Simulation time 4863401336 ps
CPU time 143.3 seconds
Started Nov 22 01:09:38 PM PST 23
Finished Nov 22 01:12:03 PM PST 23
Peak memory 198568 kb
Host smart-9c81adb7-4213-4554-886c-6f870adb3aef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=20752835167692513561740457730783921746135374272469481963687665455255734261078 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 15.hmac_datapath_stress.20752835167692513561740457730783921746135374272469481963687665455255734261078
Directory /workspace/15.hmac_datapath_stress/latest

Test location /workspace/coverage/default/15.hmac_long_msg.70203237277709541068550158878890932154340805105251320074515802055768648290906
Short name T692
Test name
Test status
Simulation time 14959266997 ps
CPU time 121.31 seconds
Started Nov 22 01:09:31 PM PST 23
Finished Nov 22 01:11:36 PM PST 23
Peak memory 198428 kb
Host smart-5ea028fe-76c8-4d4e-8f22-5ad394780e77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70203237277709541068550158878890932154340805105251320074515802055768648290906 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.hmac_long_msg.70203237277709541068550158878890932154340805105251320074515802055768648290906
Directory /workspace/15.hmac_long_msg/latest

Test location /workspace/coverage/default/15.hmac_smoke.69985518805562741887230222065568524095269067172248010839031155016799517983875
Short name T845
Test name
Test status
Simulation time 631560191 ps
CPU time 4.17 seconds
Started Nov 22 01:09:22 PM PST 23
Finished Nov 22 01:09:28 PM PST 23
Peak memory 198520 kb
Host smart-9c830266-7d12-4525-890f-173d9749b02a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69985518805562741887230222065568524095269067172248010839031155016799517983875 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 15.hmac_smoke.69985518805562741887230222065568524095269067172248010839031155016799517983875
Directory /workspace/15.hmac_smoke/latest

Test location /workspace/coverage/default/15.hmac_stress_all.82360063034273481799402468621439085946696129210178858092422214034277761903706
Short name T794
Test name
Test status
Simulation time 146644856361 ps
CPU time 1151.19 seconds
Started Nov 22 01:09:58 PM PST 23
Finished Nov 22 01:29:11 PM PST 23
Peak memory 210868 kb
Host smart-846e4db4-4224-40e4-9457-27c59317a0df
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823600630342734817994024
68621439085946696129210178858092422214034277761903706 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_stress_all.82360063034273481799402
468621439085946696129210178858092422214034277761903706
Directory /workspace/15.hmac_stress_all/latest

Test location /workspace/coverage/default/15.hmac_stress_all_with_rand_reset.11024284175238988144509735599377356012338597579988351061895323237624528842674
Short name T607
Test name
Test status
Simulation time 80460760838 ps
CPU time 717.72 seconds
Started Nov 22 01:09:53 PM PST 23
Finished Nov 22 01:21:52 PM PST 23
Peak memory 209336 kb
Host smart-46d5831c-51b4-4be1-8872-4180bbfc54f0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=11024284175238988144509735599377356012338597579988351061895323237624528842674 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 15.hmac_stress_all_with_rand_reset.11024284175238988144509735599377356012338597579988351061895323237624528842674
Directory /workspace/15.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.hmac_test_hmac_vectors.19614111324020365056273987327469919561054854471319644378432103891161231355132
Short name T248
Test name
Test status
Simulation time 76314633 ps
CPU time 0.89 seconds
Started Nov 22 01:09:50 PM PST 23
Finished Nov 22 01:09:52 PM PST 23
Peak memory 195796 kb
Host smart-6cbef0d5-1db1-43e6-b957-a8a91bfeebc2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19614111324020365056273987327469919561054854471319644
378432103891161231355132 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_test_hmac_vectors.19614111324020365056273987327469919561
054854471319644378432103891161231355132
Directory /workspace/15.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/15.hmac_test_sha_vectors.89295280816835358448036513789895107328361143559425668977701494745932015196113
Short name T433
Test name
Test status
Simulation time 63914107498 ps
CPU time 466.07 seconds
Started Nov 22 01:09:42 PM PST 23
Finished Nov 22 01:17:30 PM PST 23
Peak memory 198600 kb
Host smart-ab757591-2861-4271-b734-75cafdc2257a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89295280816835358448036513789895107328361143559425668
977701494745932015196113 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_test_sha_vectors.8929528081683535844803651378989510732836
1143559425668977701494745932015196113
Directory /workspace/15.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/15.hmac_wipe_secret.47487048964836756665969893436059871424239750971629920023451240565286790312259
Short name T417
Test name
Test status
Simulation time 8070750677 ps
CPU time 61.56 seconds
Started Nov 22 01:09:44 PM PST 23
Finished Nov 22 01:10:47 PM PST 23
Peak memory 198496 kb
Host smart-ff94f74c-0ffe-421b-9a6e-a0f5bb39832d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47487048964836756665969893436059871424239750971629920023451240565286790312259 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 15.hmac_wipe_secret.47487048964836756665969893436059871424239750971629920023451240565286790312259
Directory /workspace/15.hmac_wipe_secret/latest

Test location /workspace/coverage/default/150.hmac_stress_all_with_rand_reset.82042309140510020287063409104190406209024774872739759074214230306662691883543
Short name T197
Test name
Test status
Simulation time 80460760838 ps
CPU time 714.66 seconds
Started Nov 22 01:10:58 PM PST 23
Finished Nov 22 01:22:54 PM PST 23
Peak memory 209184 kb
Host smart-46db3d12-5329-4dc0-864a-d065737e1890
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=82042309140510020287063409104190406209024774872739759074214230306662691883543 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 150.hmac_stress_all_with_rand_reset.82042309140510020287063409104190406209024774872739759074214230306662691883543
Directory /workspace/150.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/151.hmac_stress_all_with_rand_reset.48465847099545494074548039638818716736287193930112682225733663224409847227357
Short name T517
Test name
Test status
Simulation time 80460760838 ps
CPU time 672.38 seconds
Started Nov 22 01:10:44 PM PST 23
Finished Nov 22 01:21:57 PM PST 23
Peak memory 209180 kb
Host smart-2a7b2383-3de1-4878-bcc2-e3fa41f33c1b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=48465847099545494074548039638818716736287193930112682225733663224409847227357 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 151.hmac_stress_all_with_rand_reset.48465847099545494074548039638818716736287193930112682225733663224409847227357
Directory /workspace/151.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/152.hmac_stress_all_with_rand_reset.111023030715018178320535690996753924942833893012483224648721334627035550681982
Short name T682
Test name
Test status
Simulation time 80460760838 ps
CPU time 678.25 seconds
Started Nov 22 01:11:00 PM PST 23
Finished Nov 22 01:22:20 PM PST 23
Peak memory 209292 kb
Host smart-8e6b747c-b75a-4c38-a144-8f91aedee3a5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=111023030715018178320535690996753924942833893012483224648721334627035550681982 -assert nopostproc +UVM_TE
STNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 152.hmac_stress_all_with_rand_reset.111023030715018178320535690996753924942833893012483224648721334627035550681982
Directory /workspace/152.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/153.hmac_stress_all_with_rand_reset.11887085507885363738802549402992902774162625229653136296908532647158880339945
Short name T474
Test name
Test status
Simulation time 80460760838 ps
CPU time 710.95 seconds
Started Nov 22 01:10:58 PM PST 23
Finished Nov 22 01:22:50 PM PST 23
Peak memory 209364 kb
Host smart-078a2255-6c3d-4a77-9abb-3dfb6d46a616
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=11887085507885363738802549402992902774162625229653136296908532647158880339945 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 153.hmac_stress_all_with_rand_reset.11887085507885363738802549402992902774162625229653136296908532647158880339945
Directory /workspace/153.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/154.hmac_stress_all_with_rand_reset.114038816362231497593154296067251359193326023006923655750404777400947058780065
Short name T580
Test name
Test status
Simulation time 80460760838 ps
CPU time 692.41 seconds
Started Nov 22 01:10:50 PM PST 23
Finished Nov 22 01:22:23 PM PST 23
Peak memory 209152 kb
Host smart-dfb52813-a829-4961-9c67-091363795760
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=114038816362231497593154296067251359193326023006923655750404777400947058780065 -assert nopostproc +UVM_TE
STNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 154.hmac_stress_all_with_rand_reset.114038816362231497593154296067251359193326023006923655750404777400947058780065
Directory /workspace/154.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/155.hmac_stress_all_with_rand_reset.99230898893007802367707710977609089388861189480105691566645037131141061343556
Short name T355
Test name
Test status
Simulation time 80460760838 ps
CPU time 706.36 seconds
Started Nov 22 01:11:01 PM PST 23
Finished Nov 22 01:22:49 PM PST 23
Peak memory 209348 kb
Host smart-a99542c4-9576-4e5a-b151-4e3adf3c0245
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=99230898893007802367707710977609089388861189480105691566645037131141061343556 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 155.hmac_stress_all_with_rand_reset.99230898893007802367707710977609089388861189480105691566645037131141061343556
Directory /workspace/155.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/156.hmac_stress_all_with_rand_reset.66716115036301672316644582020922888254751946371284358087136920258778791122331
Short name T379
Test name
Test status
Simulation time 80460760838 ps
CPU time 720.05 seconds
Started Nov 22 01:11:03 PM PST 23
Finished Nov 22 01:23:05 PM PST 23
Peak memory 209340 kb
Host smart-b5ec2c64-a903-4f1d-a0de-618d50b18a25
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=66716115036301672316644582020922888254751946371284358087136920258778791122331 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 156.hmac_stress_all_with_rand_reset.66716115036301672316644582020922888254751946371284358087136920258778791122331
Directory /workspace/156.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/157.hmac_stress_all_with_rand_reset.79532258670832918203185187769828476362522490028887316008846078408770111948384
Short name T390
Test name
Test status
Simulation time 80460760838 ps
CPU time 708.66 seconds
Started Nov 22 01:11:09 PM PST 23
Finished Nov 22 01:23:00 PM PST 23
Peak memory 209264 kb
Host smart-559c4343-348c-41c5-8b66-033f97d32521
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=79532258670832918203185187769828476362522490028887316008846078408770111948384 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 157.hmac_stress_all_with_rand_reset.79532258670832918203185187769828476362522490028887316008846078408770111948384
Directory /workspace/157.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/158.hmac_stress_all_with_rand_reset.34383534780491959939766126664590857744066941996480262463722906866119799217586
Short name T265
Test name
Test status
Simulation time 80460760838 ps
CPU time 698.33 seconds
Started Nov 22 01:11:10 PM PST 23
Finished Nov 22 01:22:51 PM PST 23
Peak memory 209264 kb
Host smart-8a05c01a-f0b3-4bce-b5b3-a347036143e6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=34383534780491959939766126664590857744066941996480262463722906866119799217586 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 158.hmac_stress_all_with_rand_reset.34383534780491959939766126664590857744066941996480262463722906866119799217586
Directory /workspace/158.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/159.hmac_stress_all_with_rand_reset.33458661915663030387355413201608313542121846678305840522510598653459389067644
Short name T570
Test name
Test status
Simulation time 80460760838 ps
CPU time 690.08 seconds
Started Nov 22 01:11:01 PM PST 23
Finished Nov 22 01:22:33 PM PST 23
Peak memory 209328 kb
Host smart-8199c164-a7c0-40d5-9183-1be89112b22e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=33458661915663030387355413201608313542121846678305840522510598653459389067644 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 159.hmac_stress_all_with_rand_reset.33458661915663030387355413201608313542121846678305840522510598653459389067644
Directory /workspace/159.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.hmac_alert_test.24433826398651128360332349276455835092028152650521521086549719866730001616475
Short name T769
Test name
Test status
Simulation time 18011528 ps
CPU time 0.55 seconds
Started Nov 22 01:09:45 PM PST 23
Finished Nov 22 01:09:48 PM PST 23
Peak memory 192772 kb
Host smart-ba47ff41-8f0a-4943-9237-fd9c3191304d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24433826398651128360332349276455835092028152650521521086549719866730001616475 -assert nopostpr
oc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 16.hmac_alert_test.24433826398651128360332349276455835092028152650521521086549719866730001616475
Directory /workspace/16.hmac_alert_test/latest

Test location /workspace/coverage/default/16.hmac_back_pressure.87150968116954368127544747770640678976888396283495793730697464558607269150604
Short name T43
Test name
Test status
Simulation time 2592169506 ps
CPU time 49.62 seconds
Started Nov 22 01:09:42 PM PST 23
Finished Nov 22 01:10:33 PM PST 23
Peak memory 231376 kb
Host smart-2e2fcb07-6a6e-41e9-be20-676156318321
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=87150968116954368127544747770640678976888396283495793730697464558607269150604 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 16.hmac_back_pressure.87150968116954368127544747770640678976888396283495793730697464558607269150604
Directory /workspace/16.hmac_back_pressure/latest

Test location /workspace/coverage/default/16.hmac_burst_wr.56547362581896763756325133218934835070679630788127108688755119126083612274442
Short name T392
Test name
Test status
Simulation time 4504100639 ps
CPU time 38.99 seconds
Started Nov 22 01:09:50 PM PST 23
Finished Nov 22 01:10:30 PM PST 23
Peak memory 198596 kb
Host smart-e3e56df2-8cb4-4a2b-a363-80dbcffef1f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56547362581896763756325133218934835070679630788127108688755119126083612274442 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.hmac_burst_wr.56547362581896763756325133218934835070679630788127108688755119126083612274442
Directory /workspace/16.hmac_burst_wr/latest

Test location /workspace/coverage/default/16.hmac_datapath_stress.30849068594608172563918109672712631818181402041230927308086547286729225141506
Short name T491
Test name
Test status
Simulation time 4863401336 ps
CPU time 141.88 seconds
Started Nov 22 01:09:46 PM PST 23
Finished Nov 22 01:12:10 PM PST 23
Peak memory 198584 kb
Host smart-1068ab6e-a7a8-4113-b12d-a29ad6db083b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=30849068594608172563918109672712631818181402041230927308086547286729225141506 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 16.hmac_datapath_stress.30849068594608172563918109672712631818181402041230927308086547286729225141506
Directory /workspace/16.hmac_datapath_stress/latest

Test location /workspace/coverage/default/16.hmac_error.112498185805051797102983750960122054687278773117850789513912858752172890209378
Short name T802
Test name
Test status
Simulation time 26556692074 ps
CPU time 188.42 seconds
Started Nov 22 01:09:48 PM PST 23
Finished Nov 22 01:12:58 PM PST 23
Peak memory 198512 kb
Host smart-8e4b3aa9-a987-42b6-a74d-ccc380af4d80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112498185805051797102983750960122054687278773117850789513912858752172890209378 -assert nopostproc +UVM_TESTNAME=hmac_bas
e_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 16.hmac_error.112498185805051797102983750960122054687278773117850789513912858752172890209378
Directory /workspace/16.hmac_error/latest

Test location /workspace/coverage/default/16.hmac_long_msg.1158638319152012345726363720745941957608448499982825715703588417986988009450
Short name T579
Test name
Test status
Simulation time 14959266997 ps
CPU time 119.05 seconds
Started Nov 22 01:09:39 PM PST 23
Finished Nov 22 01:11:39 PM PST 23
Peak memory 198564 kb
Host smart-565a957b-cefe-499b-a6da-8bb9dc42116d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1158638319152012345726363720745941957608448499982825715703588417986988009450 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 16.hmac_long_msg.1158638319152012345726363720745941957608448499982825715703588417986988009450
Directory /workspace/16.hmac_long_msg/latest

Test location /workspace/coverage/default/16.hmac_smoke.44945520278789147997741821512239963898739075064963758101355264053293868925237
Short name T467
Test name
Test status
Simulation time 631560191 ps
CPU time 4.05 seconds
Started Nov 22 01:09:52 PM PST 23
Finished Nov 22 01:09:57 PM PST 23
Peak memory 198520 kb
Host smart-10a3eb86-4208-4d66-9465-42f2219d5443
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44945520278789147997741821512239963898739075064963758101355264053293868925237 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 16.hmac_smoke.44945520278789147997741821512239963898739075064963758101355264053293868925237
Directory /workspace/16.hmac_smoke/latest

Test location /workspace/coverage/default/16.hmac_stress_all.51588582268083008736317625183892701737700432458357407365775262294823912286083
Short name T281
Test name
Test status
Simulation time 146644856361 ps
CPU time 1147.16 seconds
Started Nov 22 01:09:39 PM PST 23
Finished Nov 22 01:28:48 PM PST 23
Peak memory 210840 kb
Host smart-cafb7409-38a3-47af-9b31-c25d87d78426
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515885822680830087363176
25183892701737700432458357407365775262294823912286083 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_stress_all.51588582268083008736317
625183892701737700432458357407365775262294823912286083
Directory /workspace/16.hmac_stress_all/latest

Test location /workspace/coverage/default/16.hmac_stress_all_with_rand_reset.5111239154921125796468389184245893294989439524873072280874233534307309708692
Short name T299
Test name
Test status
Simulation time 80460760838 ps
CPU time 709.78 seconds
Started Nov 22 01:09:39 PM PST 23
Finished Nov 22 01:21:31 PM PST 23
Peak memory 210348 kb
Host smart-82b47f54-19aa-4985-950a-94500392a777
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=5111239154921125796468389184245893294989439524873072280874233534307309708692 -assert nopostproc +UVM_TEST
NAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 16.hmac_stress_all_with_rand_reset.5111239154921125796468389184245893294989439524873072280874233534307309708692
Directory /workspace/16.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.hmac_test_hmac_vectors.81109601028295152111865027231083505398294208997949236640005192906714821462226
Short name T362
Test name
Test status
Simulation time 76314633 ps
CPU time 0.92 seconds
Started Nov 22 01:09:40 PM PST 23
Finished Nov 22 01:09:43 PM PST 23
Peak memory 195804 kb
Host smart-9baf31d8-f7c7-4237-9968-63ee12e30114
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81109601028295152111865027231083505398294208997949236
640005192906714821462226 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_test_hmac_vectors.81109601028295152111865027231083505398
294208997949236640005192906714821462226
Directory /workspace/16.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/16.hmac_test_sha_vectors.108842208060839067283363081757058058302041104165335199306207759304960021109602
Short name T614
Test name
Test status
Simulation time 63914107498 ps
CPU time 461.94 seconds
Started Nov 22 01:09:40 PM PST 23
Finished Nov 22 01:17:24 PM PST 23
Peak memory 198524 kb
Host smart-f8c21f87-bd9e-4a94-9fbd-535a6d7467c4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10884220806083906728336308175705805830204110416533519
9306207759304960021109602 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_test_sha_vectors.108842208060839067283363081757058058302
041104165335199306207759304960021109602
Directory /workspace/16.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/16.hmac_wipe_secret.77635384963453571255083280636733962073810061459405779468029027825333163087499
Short name T296
Test name
Test status
Simulation time 8070750677 ps
CPU time 60.51 seconds
Started Nov 22 01:09:53 PM PST 23
Finished Nov 22 01:10:54 PM PST 23
Peak memory 198460 kb
Host smart-53e0327e-eba6-4d37-a148-c9cab1fcf054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77635384963453571255083280636733962073810061459405779468029027825333163087499 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 16.hmac_wipe_secret.77635384963453571255083280636733962073810061459405779468029027825333163087499
Directory /workspace/16.hmac_wipe_secret/latest

Test location /workspace/coverage/default/160.hmac_stress_all_with_rand_reset.94000716866158999021984313977679661983430462575669293206089364726084822084398
Short name T203
Test name
Test status
Simulation time 80460760838 ps
CPU time 718.3 seconds
Started Nov 22 01:10:54 PM PST 23
Finished Nov 22 01:22:55 PM PST 23
Peak memory 209184 kb
Host smart-16e966ea-8c9e-477d-ad0b-1b1dea49ad26
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=94000716866158999021984313977679661983430462575669293206089364726084822084398 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 160.hmac_stress_all_with_rand_reset.94000716866158999021984313977679661983430462575669293206089364726084822084398
Directory /workspace/160.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/161.hmac_stress_all_with_rand_reset.96092034156200668817563468616877148628434133109414497738553594321547749404798
Short name T836
Test name
Test status
Simulation time 80460760838 ps
CPU time 669.19 seconds
Started Nov 22 01:11:01 PM PST 23
Finished Nov 22 01:22:12 PM PST 23
Peak memory 209264 kb
Host smart-8ff82c9c-4bdc-4a1a-969c-7802d2ab23bb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=96092034156200668817563468616877148628434133109414497738553594321547749404798 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 161.hmac_stress_all_with_rand_reset.96092034156200668817563468616877148628434133109414497738553594321547749404798
Directory /workspace/161.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/162.hmac_stress_all_with_rand_reset.10503795065988458883018395195256274748717318613669562537358711748191002942492
Short name T342
Test name
Test status
Simulation time 80460760838 ps
CPU time 720.72 seconds
Started Nov 22 01:11:03 PM PST 23
Finished Nov 22 01:23:05 PM PST 23
Peak memory 209320 kb
Host smart-8a7d15cb-2633-4ecb-addd-46047c3b36dd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=10503795065988458883018395195256274748717318613669562537358711748191002942492 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 162.hmac_stress_all_with_rand_reset.10503795065988458883018395195256274748717318613669562537358711748191002942492
Directory /workspace/162.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/163.hmac_stress_all_with_rand_reset.9528534479047788176846876856954482062386251694133014696660665019845773986834
Short name T221
Test name
Test status
Simulation time 80460760838 ps
CPU time 679.85 seconds
Started Nov 22 01:11:00 PM PST 23
Finished Nov 22 01:22:21 PM PST 23
Peak memory 210112 kb
Host smart-4073d25b-40b6-49a2-ad6c-28beadd6e133
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=9528534479047788176846876856954482062386251694133014696660665019845773986834 -assert nopostproc +UVM_TEST
NAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 163.hmac_stress_all_with_rand_reset.9528534479047788176846876856954482062386251694133014696660665019845773986834
Directory /workspace/163.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/164.hmac_stress_all_with_rand_reset.18919229735161121542067796336974115128943348365795310781528820999529675922338
Short name T667
Test name
Test status
Simulation time 80460760838 ps
CPU time 715.52 seconds
Started Nov 22 01:11:06 PM PST 23
Finished Nov 22 01:23:03 PM PST 23
Peak memory 209304 kb
Host smart-bf6075b1-465f-44ea-b682-7db4d5b53e70
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=18919229735161121542067796336974115128943348365795310781528820999529675922338 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 164.hmac_stress_all_with_rand_reset.18919229735161121542067796336974115128943348365795310781528820999529675922338
Directory /workspace/164.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/165.hmac_stress_all_with_rand_reset.89733369634911359147704293950713822056960297100345221157302342859599365964958
Short name T449
Test name
Test status
Simulation time 80460760838 ps
CPU time 706.62 seconds
Started Nov 22 01:11:01 PM PST 23
Finished Nov 22 01:22:49 PM PST 23
Peak memory 209240 kb
Host smart-ca47294f-48b3-4aeb-846d-1a5a9b1c20c5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=89733369634911359147704293950713822056960297100345221157302342859599365964958 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 165.hmac_stress_all_with_rand_reset.89733369634911359147704293950713822056960297100345221157302342859599365964958
Directory /workspace/165.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/166.hmac_stress_all_with_rand_reset.102715739905276977080593536462047511180281887544561266504783986501211116643395
Short name T71
Test name
Test status
Simulation time 80460760838 ps
CPU time 677.63 seconds
Started Nov 22 01:11:03 PM PST 23
Finished Nov 22 01:22:22 PM PST 23
Peak memory 209240 kb
Host smart-5b1f78aa-2687-43f9-bbd6-a2381e6be9f3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=102715739905276977080593536462047511180281887544561266504783986501211116643395 -assert nopostproc +UVM_TE
STNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 166.hmac_stress_all_with_rand_reset.102715739905276977080593536462047511180281887544561266504783986501211116643395
Directory /workspace/166.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/167.hmac_stress_all_with_rand_reset.44385886901755246547673101246078509406113347158069654040686651107112941304803
Short name T848
Test name
Test status
Simulation time 80460760838 ps
CPU time 714.13 seconds
Started Nov 22 01:10:59 PM PST 23
Finished Nov 22 01:22:54 PM PST 23
Peak memory 209320 kb
Host smart-e19e610a-7f2f-41b4-83a7-749404e0efeb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=44385886901755246547673101246078509406113347158069654040686651107112941304803 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 167.hmac_stress_all_with_rand_reset.44385886901755246547673101246078509406113347158069654040686651107112941304803
Directory /workspace/167.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/168.hmac_stress_all_with_rand_reset.90624403522709687974851046343710489391962761762011278456880826611189118973706
Short name T555
Test name
Test status
Simulation time 80460760838 ps
CPU time 709.49 seconds
Started Nov 22 01:10:58 PM PST 23
Finished Nov 22 01:22:48 PM PST 23
Peak memory 209148 kb
Host smart-9c693f36-e1d3-4843-b9b8-a1bc65ef53ac
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=90624403522709687974851046343710489391962761762011278456880826611189118973706 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 168.hmac_stress_all_with_rand_reset.90624403522709687974851046343710489391962761762011278456880826611189118973706
Directory /workspace/168.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/169.hmac_stress_all_with_rand_reset.54796536319769856371036069668090967435222772658276072711275712440839173467735
Short name T752
Test name
Test status
Simulation time 80460760838 ps
CPU time 683.88 seconds
Started Nov 22 01:10:52 PM PST 23
Finished Nov 22 01:22:17 PM PST 23
Peak memory 209260 kb
Host smart-15689e6f-40ec-4dc9-8d18-48c57f50a9ec
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=54796536319769856371036069668090967435222772658276072711275712440839173467735 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 169.hmac_stress_all_with_rand_reset.54796536319769856371036069668090967435222772658276072711275712440839173467735
Directory /workspace/169.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.hmac_alert_test.43323991303315897396030361422995134456794884772193907353736652295832797718158
Short name T453
Test name
Test status
Simulation time 18011528 ps
CPU time 0.56 seconds
Started Nov 22 01:09:41 PM PST 23
Finished Nov 22 01:09:43 PM PST 23
Peak memory 192824 kb
Host smart-638c5465-6e28-47c1-83d1-c6df7d2822fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43323991303315897396030361422995134456794884772193907353736652295832797718158 -assert nopostpr
oc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 17.hmac_alert_test.43323991303315897396030361422995134456794884772193907353736652295832797718158
Directory /workspace/17.hmac_alert_test/latest

Test location /workspace/coverage/default/17.hmac_back_pressure.44139794054342717072481608744485910681929124743796854745068175839364691551301
Short name T666
Test name
Test status
Simulation time 2592169506 ps
CPU time 47.56 seconds
Started Nov 22 01:09:44 PM PST 23
Finished Nov 22 01:10:34 PM PST 23
Peak memory 231256 kb
Host smart-ea8701e3-072f-41bd-8869-363088c10a42
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=44139794054342717072481608744485910681929124743796854745068175839364691551301 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 17.hmac_back_pressure.44139794054342717072481608744485910681929124743796854745068175839364691551301
Directory /workspace/17.hmac_back_pressure/latest

Test location /workspace/coverage/default/17.hmac_burst_wr.110418560174335204372011305562722196866232890177453457022452650167710464808534
Short name T254
Test name
Test status
Simulation time 4504100639 ps
CPU time 37.52 seconds
Started Nov 22 01:09:44 PM PST 23
Finished Nov 22 01:10:23 PM PST 23
Peak memory 198512 kb
Host smart-d350ff58-1f6e-4bf4-9f9b-7f4501bb90d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110418560174335204372011305562722196866232890177453457022452650167710464808534 -assert nopostproc +UVM_TESTNAME=hmac_bas
e_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 17.hmac_burst_wr.110418560174335204372011305562722196866232890177453457022452650167710464808534
Directory /workspace/17.hmac_burst_wr/latest

Test location /workspace/coverage/default/17.hmac_datapath_stress.93047631796547629274441735706799091669946141304574895065100306304336837195508
Short name T854
Test name
Test status
Simulation time 4863401336 ps
CPU time 143.48 seconds
Started Nov 22 01:09:41 PM PST 23
Finished Nov 22 01:12:06 PM PST 23
Peak memory 198604 kb
Host smart-e6072c1e-be58-4075-a760-51e03c347233
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=93047631796547629274441735706799091669946141304574895065100306304336837195508 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 17.hmac_datapath_stress.93047631796547629274441735706799091669946141304574895065100306304336837195508
Directory /workspace/17.hmac_datapath_stress/latest

Test location /workspace/coverage/default/17.hmac_error.83538681096342522517042281852119715734315086354393484264473313496513239377852
Short name T482
Test name
Test status
Simulation time 26556692074 ps
CPU time 186.65 seconds
Started Nov 22 01:09:38 PM PST 23
Finished Nov 22 01:12:46 PM PST 23
Peak memory 198460 kb
Host smart-cf69b45d-c2b3-4855-aa3a-6f39a75872e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83538681096342522517042281852119715734315086354393484264473313496513239377852 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 17.hmac_error.83538681096342522517042281852119715734315086354393484264473313496513239377852
Directory /workspace/17.hmac_error/latest

Test location /workspace/coverage/default/17.hmac_long_msg.104285316408835800787020091166090241040978357469730627574394186637422960132792
Short name T753
Test name
Test status
Simulation time 14959266997 ps
CPU time 118.42 seconds
Started Nov 22 01:09:54 PM PST 23
Finished Nov 22 01:11:54 PM PST 23
Peak memory 198432 kb
Host smart-c9b8cf23-d343-404a-aa45-5ce237c4ef93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104285316408835800787020091166090241040978357469730627574394186637422960132792 -assert nopostproc +UVM_TESTNAME=hmac_bas
e_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 17.hmac_long_msg.104285316408835800787020091166090241040978357469730627574394186637422960132792
Directory /workspace/17.hmac_long_msg/latest

Test location /workspace/coverage/default/17.hmac_smoke.5091716249487860197987304911647478651217994491416186301135710447617143223460
Short name T358
Test name
Test status
Simulation time 631560191 ps
CPU time 3.92 seconds
Started Nov 22 01:09:53 PM PST 23
Finished Nov 22 01:09:58 PM PST 23
Peak memory 198388 kb
Host smart-3d2cf44a-efa4-4169-b87f-2b639291a095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5091716249487860197987304911647478651217994491416186301135710447617143223460 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 17.hmac_smoke.5091716249487860197987304911647478651217994491416186301135710447617143223460
Directory /workspace/17.hmac_smoke/latest

Test location /workspace/coverage/default/17.hmac_stress_all.35408921512235022681794312812595356023522312059527366367596430788129610551306
Short name T840
Test name
Test status
Simulation time 146644856361 ps
CPU time 1102.36 seconds
Started Nov 22 01:09:43 PM PST 23
Finished Nov 22 01:28:08 PM PST 23
Peak memory 210772 kb
Host smart-c2bbafcd-1209-44a0-9cc9-60ec3ef53ff3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354089215122350226817943
12812595356023522312059527366367596430788129610551306 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_stress_all.35408921512235022681794
312812595356023522312059527366367596430788129610551306
Directory /workspace/17.hmac_stress_all/latest

Test location /workspace/coverage/default/17.hmac_stress_all_with_rand_reset.49536175793066927997766550109071692447988468408425342426352885603302370072354
Short name T291
Test name
Test status
Simulation time 80460760838 ps
CPU time 729.23 seconds
Started Nov 22 01:09:54 PM PST 23
Finished Nov 22 01:22:05 PM PST 23
Peak memory 209304 kb
Host smart-32d55008-036d-45fc-8c16-7cca3d3be9dc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=49536175793066927997766550109071692447988468408425342426352885603302370072354 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 17.hmac_stress_all_with_rand_reset.49536175793066927997766550109071692447988468408425342426352885603302370072354
Directory /workspace/17.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.hmac_test_hmac_vectors.107773171983384844566516318516927786914946872851848096165721476546198292672748
Short name T652
Test name
Test status
Simulation time 76314633 ps
CPU time 0.92 seconds
Started Nov 22 01:09:46 PM PST 23
Finished Nov 22 01:09:49 PM PST 23
Peak memory 195776 kb
Host smart-20d507d1-5027-4bf5-b33c-683f84d0783c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10777317198338484456651631851692778691494687285184809
6165721476546198292672748 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_test_hmac_vectors.1077731719833848445665163185169277869
14946872851848096165721476546198292672748
Directory /workspace/17.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/17.hmac_test_sha_vectors.110467878216508683751765050241222895556286512553931198487676659960560891366308
Short name T714
Test name
Test status
Simulation time 63914107498 ps
CPU time 446.44 seconds
Started Nov 22 01:09:39 PM PST 23
Finished Nov 22 01:17:08 PM PST 23
Peak memory 198568 kb
Host smart-72e470c6-9e3e-4f8e-9c7b-051dc71bb600
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11046787821650868375176505024122289555628651255393119
8487676659960560891366308 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_test_sha_vectors.110467878216508683751765050241222895556
286512553931198487676659960560891366308
Directory /workspace/17.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/17.hmac_wipe_secret.40783635132684368107962201460679132013428387162709138494675415603947761796265
Short name T315
Test name
Test status
Simulation time 8070750677 ps
CPU time 63.91 seconds
Started Nov 22 01:09:49 PM PST 23
Finished Nov 22 01:10:54 PM PST 23
Peak memory 198584 kb
Host smart-e9dead30-5fbf-4e0d-987c-475d9bb22f04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40783635132684368107962201460679132013428387162709138494675415603947761796265 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 17.hmac_wipe_secret.40783635132684368107962201460679132013428387162709138494675415603947761796265
Directory /workspace/17.hmac_wipe_secret/latest

Test location /workspace/coverage/default/170.hmac_stress_all_with_rand_reset.113089053848548424145257301649441635791369418174618196827963007387767995800047
Short name T789
Test name
Test status
Simulation time 80460760838 ps
CPU time 715.54 seconds
Started Nov 22 01:11:03 PM PST 23
Finished Nov 22 01:22:59 PM PST 23
Peak memory 209372 kb
Host smart-7e03ec4d-42df-44fa-a796-b5ae3adab81e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=113089053848548424145257301649441635791369418174618196827963007387767995800047 -assert nopostproc +UVM_TE
STNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 170.hmac_stress_all_with_rand_reset.113089053848548424145257301649441635791369418174618196827963007387767995800047
Directory /workspace/170.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/171.hmac_stress_all_with_rand_reset.113774972849968240806900848301420658102834768754955119805919846508952945901178
Short name T639
Test name
Test status
Simulation time 80460760838 ps
CPU time 677.85 seconds
Started Nov 22 01:10:57 PM PST 23
Finished Nov 22 01:22:16 PM PST 23
Peak memory 209304 kb
Host smart-236c0c21-88af-49f4-a36c-648c0036adcc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=113774972849968240806900848301420658102834768754955119805919846508952945901178 -assert nopostproc +UVM_TE
STNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 171.hmac_stress_all_with_rand_reset.113774972849968240806900848301420658102834768754955119805919846508952945901178
Directory /workspace/171.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/172.hmac_stress_all_with_rand_reset.105188039885820571225275817289252756194384668995147136825633127717736258392322
Short name T711
Test name
Test status
Simulation time 80460760838 ps
CPU time 705.4 seconds
Started Nov 22 01:11:02 PM PST 23
Finished Nov 22 01:22:49 PM PST 23
Peak memory 209320 kb
Host smart-7b6bdaea-b11d-4a4c-b830-cf9b2d5d7d09
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=105188039885820571225275817289252756194384668995147136825633127717736258392322 -assert nopostproc +UVM_TE
STNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 172.hmac_stress_all_with_rand_reset.105188039885820571225275817289252756194384668995147136825633127717736258392322
Directory /workspace/172.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/173.hmac_stress_all_with_rand_reset.93402348103387692844437960431425445417868686182663687413690567378187914703192
Short name T238
Test name
Test status
Simulation time 80460760838 ps
CPU time 697.67 seconds
Started Nov 22 01:11:05 PM PST 23
Finished Nov 22 01:22:44 PM PST 23
Peak memory 209304 kb
Host smart-188b0a54-d93c-4659-b339-0ae5f6aac379
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=93402348103387692844437960431425445417868686182663687413690567378187914703192 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 173.hmac_stress_all_with_rand_reset.93402348103387692844437960431425445417868686182663687413690567378187914703192
Directory /workspace/173.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/174.hmac_stress_all_with_rand_reset.3929254802333234328332655100236704481410489152860282377754061030337463175077
Short name T621
Test name
Test status
Simulation time 80460760838 ps
CPU time 683.77 seconds
Started Nov 22 01:11:04 PM PST 23
Finished Nov 22 01:22:29 PM PST 23
Peak memory 210192 kb
Host smart-b0fbbc0a-9477-4de5-bac0-3a453c303509
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3929254802333234328332655100236704481410489152860282377754061030337463175077 -assert nopostproc +UVM_TEST
NAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 174.hmac_stress_all_with_rand_reset.3929254802333234328332655100236704481410489152860282377754061030337463175077
Directory /workspace/174.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/175.hmac_stress_all_with_rand_reset.63071121722258313084609520214818879859355256782004453524254445181992688666849
Short name T786
Test name
Test status
Simulation time 80460760838 ps
CPU time 679.56 seconds
Started Nov 22 01:10:51 PM PST 23
Finished Nov 22 01:22:12 PM PST 23
Peak memory 209260 kb
Host smart-92913048-59e6-4323-872d-740fb4ffc82f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=63071121722258313084609520214818879859355256782004453524254445181992688666849 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 175.hmac_stress_all_with_rand_reset.63071121722258313084609520214818879859355256782004453524254445181992688666849
Directory /workspace/175.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/176.hmac_stress_all_with_rand_reset.98382786791578426191142872570577425474132513702093416161033338039902374419271
Short name T418
Test name
Test status
Simulation time 80460760838 ps
CPU time 665.86 seconds
Started Nov 22 01:10:51 PM PST 23
Finished Nov 22 01:21:58 PM PST 23
Peak memory 209260 kb
Host smart-e72bd516-b0db-47d5-96e1-94a41019be75
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=98382786791578426191142872570577425474132513702093416161033338039902374419271 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 176.hmac_stress_all_with_rand_reset.98382786791578426191142872570577425474132513702093416161033338039902374419271
Directory /workspace/176.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/177.hmac_stress_all_with_rand_reset.43294270136164941834928673216640452459068905001186637435196459927099025095140
Short name T279
Test name
Test status
Simulation time 80460760838 ps
CPU time 714.28 seconds
Started Nov 22 01:11:03 PM PST 23
Finished Nov 22 01:22:59 PM PST 23
Peak memory 209288 kb
Host smart-0b3daa54-417e-4682-bc4e-56a9d2be8f69
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=43294270136164941834928673216640452459068905001186637435196459927099025095140 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 177.hmac_stress_all_with_rand_reset.43294270136164941834928673216640452459068905001186637435196459927099025095140
Directory /workspace/177.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/178.hmac_stress_all_with_rand_reset.63406161976542684092944769109534275138946537790853913095919747211558220752781
Short name T294
Test name
Test status
Simulation time 80460760838 ps
CPU time 701.69 seconds
Started Nov 22 01:11:03 PM PST 23
Finished Nov 22 01:22:46 PM PST 23
Peak memory 209220 kb
Host smart-bfc36f88-8635-44f1-91e2-a82a3360399f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=63406161976542684092944769109534275138946537790853913095919747211558220752781 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 178.hmac_stress_all_with_rand_reset.63406161976542684092944769109534275138946537790853913095919747211558220752781
Directory /workspace/178.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/179.hmac_stress_all_with_rand_reset.17589795853003460506397834564692692868349472855624160469465762655054419063623
Short name T434
Test name
Test status
Simulation time 80460760838 ps
CPU time 719.38 seconds
Started Nov 22 01:11:08 PM PST 23
Finished Nov 22 01:23:09 PM PST 23
Peak memory 209328 kb
Host smart-ddca5d16-37f0-4ab4-85c1-a2a8e8991ab9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=17589795853003460506397834564692692868349472855624160469465762655054419063623 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 179.hmac_stress_all_with_rand_reset.17589795853003460506397834564692692868349472855624160469465762655054419063623
Directory /workspace/179.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.hmac_alert_test.21472357646026629425933563752344090680293712528682512684683160044242825852728
Short name T277
Test name
Test status
Simulation time 18011528 ps
CPU time 0.55 seconds
Started Nov 22 01:09:50 PM PST 23
Finished Nov 22 01:09:52 PM PST 23
Peak memory 192800 kb
Host smart-3a8a88f0-b851-43e2-8144-0f346a7d216e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21472357646026629425933563752344090680293712528682512684683160044242825852728 -assert nopostpr
oc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 18.hmac_alert_test.21472357646026629425933563752344090680293712528682512684683160044242825852728
Directory /workspace/18.hmac_alert_test/latest

Test location /workspace/coverage/default/18.hmac_back_pressure.20312959437623475325811840114344050783143424096568481431603694482084191841274
Short name T364
Test name
Test status
Simulation time 2592169506 ps
CPU time 49.61 seconds
Started Nov 22 01:09:50 PM PST 23
Finished Nov 22 01:10:41 PM PST 23
Peak memory 231392 kb
Host smart-411c02ca-7c6e-4053-a383-dd3d2b549592
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=20312959437623475325811840114344050783143424096568481431603694482084191841274 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 18.hmac_back_pressure.20312959437623475325811840114344050783143424096568481431603694482084191841274
Directory /workspace/18.hmac_back_pressure/latest

Test location /workspace/coverage/default/18.hmac_burst_wr.93434855828696028301287437636079680204509580340034474511287543230476452029981
Short name T263
Test name
Test status
Simulation time 4504100639 ps
CPU time 38.52 seconds
Started Nov 22 01:09:45 PM PST 23
Finished Nov 22 01:10:25 PM PST 23
Peak memory 198604 kb
Host smart-4a0573ed-c7f8-4c9e-8ff4-b1c3ed065665
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93434855828696028301287437636079680204509580340034474511287543230476452029981 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.hmac_burst_wr.93434855828696028301287437636079680204509580340034474511287543230476452029981
Directory /workspace/18.hmac_burst_wr/latest

Test location /workspace/coverage/default/18.hmac_datapath_stress.30265748443853017764157134499128449211984351866642052787271249814173790607950
Short name T225
Test name
Test status
Simulation time 4863401336 ps
CPU time 139.28 seconds
Started Nov 22 01:09:42 PM PST 23
Finished Nov 22 01:12:03 PM PST 23
Peak memory 198516 kb
Host smart-95db6409-d597-484c-b89d-0c5aa309a1d4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=30265748443853017764157134499128449211984351866642052787271249814173790607950 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 18.hmac_datapath_stress.30265748443853017764157134499128449211984351866642052787271249814173790607950
Directory /workspace/18.hmac_datapath_stress/latest

Test location /workspace/coverage/default/18.hmac_error.34631517402130594276713680611892763778260915029148601813775056940891864798847
Short name T697
Test name
Test status
Simulation time 26556692074 ps
CPU time 188.23 seconds
Started Nov 22 01:09:44 PM PST 23
Finished Nov 22 01:12:55 PM PST 23
Peak memory 198484 kb
Host smart-2092dc50-99aa-4f60-8b1a-bc69f61c4960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34631517402130594276713680611892763778260915029148601813775056940891864798847 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 18.hmac_error.34631517402130594276713680611892763778260915029148601813775056940891864798847
Directory /workspace/18.hmac_error/latest

Test location /workspace/coverage/default/18.hmac_long_msg.37668410947701026254825694364769264380596192669740259955802535467069887239206
Short name T560
Test name
Test status
Simulation time 14959266997 ps
CPU time 114.2 seconds
Started Nov 22 01:09:55 PM PST 23
Finished Nov 22 01:11:50 PM PST 23
Peak memory 198432 kb
Host smart-59f41d9f-14e7-4ad1-8c93-87e754117d33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37668410947701026254825694364769264380596192669740259955802535467069887239206 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.hmac_long_msg.37668410947701026254825694364769264380596192669740259955802535467069887239206
Directory /workspace/18.hmac_long_msg/latest

Test location /workspace/coverage/default/18.hmac_smoke.69047413720653399964465582076335521000015051476724661016298080337240701598427
Short name T499
Test name
Test status
Simulation time 631560191 ps
CPU time 4.21 seconds
Started Nov 22 01:10:13 PM PST 23
Finished Nov 22 01:10:22 PM PST 23
Peak memory 198312 kb
Host smart-99090905-9f44-43fe-bb55-8ca32807f27c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69047413720653399964465582076335521000015051476724661016298080337240701598427 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 18.hmac_smoke.69047413720653399964465582076335521000015051476724661016298080337240701598427
Directory /workspace/18.hmac_smoke/latest

Test location /workspace/coverage/default/18.hmac_stress_all.65721518176795910711004960064318618296288810486312225407016951034202530638971
Short name T471
Test name
Test status
Simulation time 146644856361 ps
CPU time 1157.36 seconds
Started Nov 22 01:09:49 PM PST 23
Finished Nov 22 01:29:08 PM PST 23
Peak memory 210860 kb
Host smart-43876c5a-ef4c-4cf0-93e1-149e0c72e6fd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657215181767959107110049
60064318618296288810486312225407016951034202530638971 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_stress_all.65721518176795910711004
960064318618296288810486312225407016951034202530638971
Directory /workspace/18.hmac_stress_all/latest

Test location /workspace/coverage/default/18.hmac_stress_all_with_rand_reset.82104551444697143584916380118450443768934296382700620490790437589517204461351
Short name T286
Test name
Test status
Simulation time 80460760838 ps
CPU time 720.46 seconds
Started Nov 22 01:09:43 PM PST 23
Finished Nov 22 01:21:46 PM PST 23
Peak memory 209364 kb
Host smart-9a550e27-ebde-43df-be5a-ce046c8f7392
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=82104551444697143584916380118450443768934296382700620490790437589517204461351 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 18.hmac_stress_all_with_rand_reset.82104551444697143584916380118450443768934296382700620490790437589517204461351
Directory /workspace/18.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.hmac_test_hmac_vectors.47719276642034324584938492697655762505904654009636195968177897768329944670327
Short name T534
Test name
Test status
Simulation time 76314633 ps
CPU time 0.92 seconds
Started Nov 22 01:09:47 PM PST 23
Finished Nov 22 01:09:50 PM PST 23
Peak memory 195728 kb
Host smart-3936dac3-ade2-4da1-9005-970e5ec6ea25
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47719276642034324584938492697655762505904654009636195
968177897768329944670327 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_test_hmac_vectors.47719276642034324584938492697655762505
904654009636195968177897768329944670327
Directory /workspace/18.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/18.hmac_test_sha_vectors.102476011304015059315009591040467114466457470351785549236441587795987621366648
Short name T746
Test name
Test status
Simulation time 63914107498 ps
CPU time 467.47 seconds
Started Nov 22 01:09:43 PM PST 23
Finished Nov 22 01:17:33 PM PST 23
Peak memory 198584 kb
Host smart-2b76025d-6a11-4fbf-9c84-045bc4eed0c0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10247601130401505931500959104046711446645747035178554
9236441587795987621366648 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_test_sha_vectors.102476011304015059315009591040467114466
457470351785549236441587795987621366648
Directory /workspace/18.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/18.hmac_wipe_secret.2185168284788833870506178938618948889342830155562946136450778410335684396910
Short name T191
Test name
Test status
Simulation time 8070750677 ps
CPU time 61.24 seconds
Started Nov 22 01:09:59 PM PST 23
Finished Nov 22 01:11:02 PM PST 23
Peak memory 198616 kb
Host smart-dcebee5a-f792-468c-a08f-e548db8b68d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2185168284788833870506178938618948889342830155562946136450778410335684396910 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 18.hmac_wipe_secret.2185168284788833870506178938618948889342830155562946136450778410335684396910
Directory /workspace/18.hmac_wipe_secret/latest

Test location /workspace/coverage/default/180.hmac_stress_all_with_rand_reset.112366333413432297578357079956348512050308760087904828077354168924347385505550
Short name T414
Test name
Test status
Simulation time 80460760838 ps
CPU time 717.67 seconds
Started Nov 22 01:11:05 PM PST 23
Finished Nov 22 01:23:05 PM PST 23
Peak memory 209324 kb
Host smart-23c9d18f-2988-4a59-9d55-aa0c5a579d1c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=112366333413432297578357079956348512050308760087904828077354168924347385505550 -assert nopostproc +UVM_TE
STNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 180.hmac_stress_all_with_rand_reset.112366333413432297578357079956348512050308760087904828077354168924347385505550
Directory /workspace/180.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/181.hmac_stress_all_with_rand_reset.37064174771212710870683566482643453294333988828112145051647786774694858844227
Short name T180
Test name
Test status
Simulation time 80460760838 ps
CPU time 700.03 seconds
Started Nov 22 01:10:55 PM PST 23
Finished Nov 22 01:22:37 PM PST 23
Peak memory 209184 kb
Host smart-d9567a6b-cae8-4f64-a293-7fe770340762
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=37064174771212710870683566482643453294333988828112145051647786774694858844227 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 181.hmac_stress_all_with_rand_reset.37064174771212710870683566482643453294333988828112145051647786774694858844227
Directory /workspace/181.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/182.hmac_stress_all_with_rand_reset.28258772035000733955803674570887913553457379764449312741258360419439599694628
Short name T799
Test name
Test status
Simulation time 80460760838 ps
CPU time 691.22 seconds
Started Nov 22 01:10:52 PM PST 23
Finished Nov 22 01:22:25 PM PST 23
Peak memory 209264 kb
Host smart-1ee292ed-a3ea-430e-91e5-2cbb74165a17
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=28258772035000733955803674570887913553457379764449312741258360419439599694628 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 182.hmac_stress_all_with_rand_reset.28258772035000733955803674570887913553457379764449312741258360419439599694628
Directory /workspace/182.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/183.hmac_stress_all_with_rand_reset.59628274480566391100638277620395160399506624908563644401854212367116531683468
Short name T807
Test name
Test status
Simulation time 80460760838 ps
CPU time 708.71 seconds
Started Nov 22 01:11:10 PM PST 23
Finished Nov 22 01:23:01 PM PST 23
Peak memory 209240 kb
Host smart-f8f3ca30-f05b-4fe2-9fd6-b2fea44a3f4d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=59628274480566391100638277620395160399506624908563644401854212367116531683468 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 183.hmac_stress_all_with_rand_reset.59628274480566391100638277620395160399506624908563644401854212367116531683468
Directory /workspace/183.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/184.hmac_stress_all_with_rand_reset.68134114420763380512601763669727309987756601205119436673054488824092198060616
Short name T256
Test name
Test status
Simulation time 80460760838 ps
CPU time 692.53 seconds
Started Nov 22 01:11:05 PM PST 23
Finished Nov 22 01:22:39 PM PST 23
Peak memory 209304 kb
Host smart-8c7c4092-2efc-4ea5-a742-b4daaa9b55ae
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=68134114420763380512601763669727309987756601205119436673054488824092198060616 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 184.hmac_stress_all_with_rand_reset.68134114420763380512601763669727309987756601205119436673054488824092198060616
Directory /workspace/184.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/185.hmac_stress_all_with_rand_reset.60163022976645337944859172193002974636803651906206074192524286404175761522856
Short name T410
Test name
Test status
Simulation time 80460760838 ps
CPU time 691.64 seconds
Started Nov 22 01:10:54 PM PST 23
Finished Nov 22 01:22:28 PM PST 23
Peak memory 209184 kb
Host smart-05f11526-8e89-47e5-a27c-64fa73a7ff13
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=60163022976645337944859172193002974636803651906206074192524286404175761522856 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 185.hmac_stress_all_with_rand_reset.60163022976645337944859172193002974636803651906206074192524286404175761522856
Directory /workspace/185.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/186.hmac_stress_all_with_rand_reset.34475986012415828825740311198013836890011358712896175634228094896238478696185
Short name T5
Test name
Test status
Simulation time 80460760838 ps
CPU time 722.76 seconds
Started Nov 22 01:11:03 PM PST 23
Finished Nov 22 01:23:08 PM PST 23
Peak memory 209324 kb
Host smart-89bac026-8e39-4e69-b876-061de65a3708
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=34475986012415828825740311198013836890011358712896175634228094896238478696185 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 186.hmac_stress_all_with_rand_reset.34475986012415828825740311198013836890011358712896175634228094896238478696185
Directory /workspace/186.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/187.hmac_stress_all_with_rand_reset.96936074126684728680021358420295836818683292424025682653021126259044239257994
Short name T48
Test name
Test status
Simulation time 80460760838 ps
CPU time 739.02 seconds
Started Nov 22 01:11:02 PM PST 23
Finished Nov 22 01:23:22 PM PST 23
Peak memory 209320 kb
Host smart-507072d4-0a89-4cd0-8c36-42209e9b7c24
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=96936074126684728680021358420295836818683292424025682653021126259044239257994 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 187.hmac_stress_all_with_rand_reset.96936074126684728680021358420295836818683292424025682653021126259044239257994
Directory /workspace/187.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/188.hmac_stress_all_with_rand_reset.35037158930994234675178611099801713005416231221953202078774794401870716477008
Short name T757
Test name
Test status
Simulation time 80460760838 ps
CPU time 695.47 seconds
Started Nov 22 01:11:02 PM PST 23
Finished Nov 22 01:22:39 PM PST 23
Peak memory 209320 kb
Host smart-0c4e23b2-9eda-4327-82ea-d744abd1233c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=35037158930994234675178611099801713005416231221953202078774794401870716477008 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 188.hmac_stress_all_with_rand_reset.35037158930994234675178611099801713005416231221953202078774794401870716477008
Directory /workspace/188.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/189.hmac_stress_all_with_rand_reset.100570520167293802320541357113058491034167880546504561301057490911815988343604
Short name T201
Test name
Test status
Simulation time 80460760838 ps
CPU time 709.91 seconds
Started Nov 22 01:11:03 PM PST 23
Finished Nov 22 01:22:54 PM PST 23
Peak memory 209344 kb
Host smart-89cded02-4b01-46f5-b716-d10d58ad766d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=100570520167293802320541357113058491034167880546504561301057490911815988343604 -assert nopostproc +UVM_TE
STNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 189.hmac_stress_all_with_rand_reset.100570520167293802320541357113058491034167880546504561301057490911815988343604
Directory /workspace/189.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.hmac_alert_test.2545832180563489001983219544483207142293392608587115963745368428239192226858
Short name T768
Test name
Test status
Simulation time 18011528 ps
CPU time 0.55 seconds
Started Nov 22 01:10:01 PM PST 23
Finished Nov 22 01:10:04 PM PST 23
Peak memory 192860 kb
Host smart-b7fac30f-fcd0-4c4f-9812-82a165df94b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545832180563489001983219544483207142293392608587115963745368428239192226858 -assert nopostpro
c +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 19.hmac_alert_test.2545832180563489001983219544483207142293392608587115963745368428239192226858
Directory /workspace/19.hmac_alert_test/latest

Test location /workspace/coverage/default/19.hmac_back_pressure.55851573308786765858182965833911812293179501205790860022735922633118147772548
Short name T44
Test name
Test status
Simulation time 2592169506 ps
CPU time 46.65 seconds
Started Nov 22 01:09:52 PM PST 23
Finished Nov 22 01:10:39 PM PST 23
Peak memory 231392 kb
Host smart-9972a7cc-55a4-48f6-96ba-b8d2b1132ce1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=55851573308786765858182965833911812293179501205790860022735922633118147772548 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 19.hmac_back_pressure.55851573308786765858182965833911812293179501205790860022735922633118147772548
Directory /workspace/19.hmac_back_pressure/latest

Test location /workspace/coverage/default/19.hmac_burst_wr.83577963881212382093843889071572629405550732467708204689459668126285413355099
Short name T10
Test name
Test status
Simulation time 4504100639 ps
CPU time 37.85 seconds
Started Nov 22 01:09:39 PM PST 23
Finished Nov 22 01:10:18 PM PST 23
Peak memory 198580 kb
Host smart-748a1f9b-c091-469d-be8b-16bb1e52473d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83577963881212382093843889071572629405550732467708204689459668126285413355099 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.hmac_burst_wr.83577963881212382093843889071572629405550732467708204689459668126285413355099
Directory /workspace/19.hmac_burst_wr/latest

Test location /workspace/coverage/default/19.hmac_datapath_stress.3258078685682265130571177757782937436106607950563319271126493888824028523312
Short name T669
Test name
Test status
Simulation time 4863401336 ps
CPU time 144.71 seconds
Started Nov 22 01:09:44 PM PST 23
Finished Nov 22 01:12:12 PM PST 23
Peak memory 198488 kb
Host smart-5d8b4728-ac8d-4da7-86a9-5e664371bed7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3258078685682265130571177757782937436106607950563319271126493888824028523312 -assert nopostproc +UVM_TEST
NAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 19.hmac_datapath_stress.3258078685682265130571177757782937436106607950563319271126493888824028523312
Directory /workspace/19.hmac_datapath_stress/latest

Test location /workspace/coverage/default/19.hmac_error.12245560813249172328931447878510847996983415248124030724994833441942377273884
Short name T487
Test name
Test status
Simulation time 26556692074 ps
CPU time 195.52 seconds
Started Nov 22 01:09:40 PM PST 23
Finished Nov 22 01:12:58 PM PST 23
Peak memory 198592 kb
Host smart-f5df4623-148a-4b9e-b9d3-d07272779915
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12245560813249172328931447878510847996983415248124030724994833441942377273884 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 19.hmac_error.12245560813249172328931447878510847996983415248124030724994833441942377273884
Directory /workspace/19.hmac_error/latest

Test location /workspace/coverage/default/19.hmac_long_msg.42393227267415006427450665524801813029939720921659323497326194488940717351559
Short name T546
Test name
Test status
Simulation time 14959266997 ps
CPU time 117.49 seconds
Started Nov 22 01:09:59 PM PST 23
Finished Nov 22 01:11:59 PM PST 23
Peak memory 198592 kb
Host smart-1df093b5-5581-4180-aa1b-f7135bea9a5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42393227267415006427450665524801813029939720921659323497326194488940717351559 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.hmac_long_msg.42393227267415006427450665524801813029939720921659323497326194488940717351559
Directory /workspace/19.hmac_long_msg/latest

Test location /workspace/coverage/default/19.hmac_smoke.26120036150642904277386390568717386862872788154109859356013251541233252151077
Short name T788
Test name
Test status
Simulation time 631560191 ps
CPU time 3.98 seconds
Started Nov 22 01:09:39 PM PST 23
Finished Nov 22 01:09:45 PM PST 23
Peak memory 198460 kb
Host smart-7785a9b2-cec7-4ca9-8a66-ae033a00b603
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26120036150642904277386390568717386862872788154109859356013251541233252151077 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 19.hmac_smoke.26120036150642904277386390568717386862872788154109859356013251541233252151077
Directory /workspace/19.hmac_smoke/latest

Test location /workspace/coverage/default/19.hmac_stress_all.72767223599292365526164892765486662887592830861024957152475592754719255293921
Short name T818
Test name
Test status
Simulation time 146644856361 ps
CPU time 1172.49 seconds
Started Nov 22 01:09:52 PM PST 23
Finished Nov 22 01:29:26 PM PST 23
Peak memory 210800 kb
Host smart-dd46dc1b-edc3-43cf-bd8d-a5546f71cdc0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727672235992923655261648
92765486662887592830861024957152475592754719255293921 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_stress_all.72767223599292365526164
892765486662887592830861024957152475592754719255293921
Directory /workspace/19.hmac_stress_all/latest

Test location /workspace/coverage/default/19.hmac_stress_all_with_rand_reset.35879734802268330467017974448135523815720939815558412234598112461133687475626
Short name T448
Test name
Test status
Simulation time 80460760838 ps
CPU time 699.1 seconds
Started Nov 22 01:10:04 PM PST 23
Finished Nov 22 01:21:48 PM PST 23
Peak memory 209328 kb
Host smart-f27bfb07-666b-426c-8297-7d09c4d4b254
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=35879734802268330467017974448135523815720939815558412234598112461133687475626 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 19.hmac_stress_all_with_rand_reset.35879734802268330467017974448135523815720939815558412234598112461133687475626
Directory /workspace/19.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.hmac_test_hmac_vectors.103775137317973432299494967682062538924582850479538423955426158652117407930730
Short name T665
Test name
Test status
Simulation time 76314633 ps
CPU time 0.95 seconds
Started Nov 22 01:09:45 PM PST 23
Finished Nov 22 01:09:48 PM PST 23
Peak memory 195712 kb
Host smart-403517b7-1ec8-4af1-bbe2-ea142b78dc57
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10377513731797343229949496768206253892458285047953842
3955426158652117407930730 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_test_hmac_vectors.1037751373179734322994949676820625389
24582850479538423955426158652117407930730
Directory /workspace/19.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/19.hmac_test_sha_vectors.43042093124483481822473925517969271664514297076111538914861294300768855992743
Short name T864
Test name
Test status
Simulation time 63914107498 ps
CPU time 454.63 seconds
Started Nov 22 01:09:40 PM PST 23
Finished Nov 22 01:17:16 PM PST 23
Peak memory 198572 kb
Host smart-fa9f01d0-e2b8-47d8-b18e-74415c36fb62
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43042093124483481822473925517969271664514297076111538
914861294300768855992743 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_test_sha_vectors.4304209312448348182247392551796927166451
4297076111538914861294300768855992743
Directory /workspace/19.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/19.hmac_wipe_secret.112500188495994465687643875514747189212925929002034486802975424049951823307189
Short name T863
Test name
Test status
Simulation time 8070750677 ps
CPU time 61.11 seconds
Started Nov 22 01:09:49 PM PST 23
Finished Nov 22 01:10:51 PM PST 23
Peak memory 198544 kb
Host smart-06fc57fb-849a-4a94-8c5c-2337699086da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112500188495994465687643875514747189212925929002034486802975424049951823307189 -assert nopostproc +UVM_TESTNAME=hmac_bas
e_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 19.hmac_wipe_secret.112500188495994465687643875514747189212925929002034486802975424049951823307189
Directory /workspace/19.hmac_wipe_secret/latest

Test location /workspace/coverage/default/190.hmac_stress_all_with_rand_reset.115110009223116885015529577337199007945174370430543689136831779866194700629301
Short name T531
Test name
Test status
Simulation time 80460760838 ps
CPU time 710.98 seconds
Started Nov 22 01:11:05 PM PST 23
Finished Nov 22 01:22:58 PM PST 23
Peak memory 209324 kb
Host smart-6ecbd886-9d68-4384-b11a-a644f43a87f1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=115110009223116885015529577337199007945174370430543689136831779866194700629301 -assert nopostproc +UVM_TE
STNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 190.hmac_stress_all_with_rand_reset.115110009223116885015529577337199007945174370430543689136831779866194700629301
Directory /workspace/190.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/191.hmac_stress_all_with_rand_reset.29706606440956261389372169627128827113737187337431002446982461079400409294781
Short name T432
Test name
Test status
Simulation time 80460760838 ps
CPU time 699.2 seconds
Started Nov 22 01:11:07 PM PST 23
Finished Nov 22 01:22:48 PM PST 23
Peak memory 209152 kb
Host smart-fb7350aa-ba7e-4e58-8475-f89d550bd7df
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=29706606440956261389372169627128827113737187337431002446982461079400409294781 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 191.hmac_stress_all_with_rand_reset.29706606440956261389372169627128827113737187337431002446982461079400409294781
Directory /workspace/191.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/192.hmac_stress_all_with_rand_reset.19664922738991516493560198011729534956290459798546111931756137373298901963831
Short name T567
Test name
Test status
Simulation time 80460760838 ps
CPU time 706.21 seconds
Started Nov 22 01:11:02 PM PST 23
Finished Nov 22 01:22:50 PM PST 23
Peak memory 209344 kb
Host smart-260dd353-9d12-48e4-9f12-bce45201acc3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=19664922738991516493560198011729534956290459798546111931756137373298901963831 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 192.hmac_stress_all_with_rand_reset.19664922738991516493560198011729534956290459798546111931756137373298901963831
Directory /workspace/192.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/193.hmac_stress_all_with_rand_reset.48702488570402935143203994971860924699403408982165110611327129271157843046174
Short name T496
Test name
Test status
Simulation time 80460760838 ps
CPU time 681.38 seconds
Started Nov 22 01:10:51 PM PST 23
Finished Nov 22 01:22:14 PM PST 23
Peak memory 209264 kb
Host smart-b22118ae-6ba5-4079-abde-dba09766ef15
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=48702488570402935143203994971860924699403408982165110611327129271157843046174 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 193.hmac_stress_all_with_rand_reset.48702488570402935143203994971860924699403408982165110611327129271157843046174
Directory /workspace/193.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/194.hmac_stress_all_with_rand_reset.61556415740403561789230015248475051319835615227335235441374298038564199812517
Short name T222
Test name
Test status
Simulation time 80460760838 ps
CPU time 716.16 seconds
Started Nov 22 01:11:05 PM PST 23
Finished Nov 22 01:23:03 PM PST 23
Peak memory 209308 kb
Host smart-135a135a-66ed-4382-8166-6828acac5bcf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=61556415740403561789230015248475051319835615227335235441374298038564199812517 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 194.hmac_stress_all_with_rand_reset.61556415740403561789230015248475051319835615227335235441374298038564199812517
Directory /workspace/194.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/195.hmac_stress_all_with_rand_reset.70440816488858134719844467579815419793638248808657318729106930681196044389876
Short name T602
Test name
Test status
Simulation time 80460760838 ps
CPU time 687.8 seconds
Started Nov 22 01:11:09 PM PST 23
Finished Nov 22 01:22:39 PM PST 23
Peak memory 209264 kb
Host smart-5a0de293-a628-4f99-83be-c5b4e3d226e6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=70440816488858134719844467579815419793638248808657318729106930681196044389876 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 195.hmac_stress_all_with_rand_reset.70440816488858134719844467579815419793638248808657318729106930681196044389876
Directory /workspace/195.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/196.hmac_stress_all_with_rand_reset.72532685289104721127819975281371754654600603820057914695992950372906108597395
Short name T260
Test name
Test status
Simulation time 80460760838 ps
CPU time 696.76 seconds
Started Nov 22 01:11:00 PM PST 23
Finished Nov 22 01:22:38 PM PST 23
Peak memory 209340 kb
Host smart-2f4ddace-d50f-4d07-9a54-bedc6cfbd837
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=72532685289104721127819975281371754654600603820057914695992950372906108597395 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 196.hmac_stress_all_with_rand_reset.72532685289104721127819975281371754654600603820057914695992950372906108597395
Directory /workspace/196.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/197.hmac_stress_all_with_rand_reset.63072593159619929705099500042543652630523353184771905784241405763040169431491
Short name T495
Test name
Test status
Simulation time 80460760838 ps
CPU time 732.72 seconds
Started Nov 22 01:11:01 PM PST 23
Finished Nov 22 01:23:16 PM PST 23
Peak memory 209292 kb
Host smart-c7e59693-036c-4eae-b0c2-a02f5e7c3732
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=63072593159619929705099500042543652630523353184771905784241405763040169431491 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 197.hmac_stress_all_with_rand_reset.63072593159619929705099500042543652630523353184771905784241405763040169431491
Directory /workspace/197.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/198.hmac_stress_all_with_rand_reset.43108838455627318018768443780559989869452888497720260144282552917105266074655
Short name T739
Test name
Test status
Simulation time 80460760838 ps
CPU time 680.37 seconds
Started Nov 22 01:11:06 PM PST 23
Finished Nov 22 01:22:28 PM PST 23
Peak memory 209308 kb
Host smart-b8fe2621-559d-4c29-8dd1-8aa7188f33c4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=43108838455627318018768443780559989869452888497720260144282552917105266074655 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 198.hmac_stress_all_with_rand_reset.43108838455627318018768443780559989869452888497720260144282552917105266074655
Directory /workspace/198.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/199.hmac_stress_all_with_rand_reset.51815360400005226742378793664499600043164110306397731243025058507025627629517
Short name T460
Test name
Test status
Simulation time 80460760838 ps
CPU time 698.38 seconds
Started Nov 22 01:11:00 PM PST 23
Finished Nov 22 01:22:40 PM PST 23
Peak memory 209272 kb
Host smart-0dd54276-0975-417e-a316-6473c5bc982f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=51815360400005226742378793664499600043164110306397731243025058507025627629517 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 199.hmac_stress_all_with_rand_reset.51815360400005226742378793664499600043164110306397731243025058507025627629517
Directory /workspace/199.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.hmac_alert_test.80558867347322764111589330237542801469444764435403044066952797065072977675447
Short name T288
Test name
Test status
Simulation time 18011528 ps
CPU time 0.54 seconds
Started Nov 22 01:08:55 PM PST 23
Finished Nov 22 01:09:00 PM PST 23
Peak memory 192736 kb
Host smart-42d8bd47-7fc1-4ef6-b57f-3cdccc208c37
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80558867347322764111589330237542801469444764435403044066952797065072977675447 -assert nopostpr
oc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 2.hmac_alert_test.80558867347322764111589330237542801469444764435403044066952797065072977675447
Directory /workspace/2.hmac_alert_test/latest

Test location /workspace/coverage/default/2.hmac_back_pressure.103907134561931879425043717947495965295166653539959999955009299963013741621368
Short name T582
Test name
Test status
Simulation time 2592169506 ps
CPU time 45.16 seconds
Started Nov 22 01:08:51 PM PST 23
Finished Nov 22 01:09:43 PM PST 23
Peak memory 231208 kb
Host smart-f9497604-0a59-456d-93bd-44b4c37f17e4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=103907134561931879425043717947495965295166653539959999955009299963013741621368 -assert nopostproc +UVM_TE
STNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.hmac_back_pressure.103907134561931879425043717947495965295166653539959999955009299963013741621368
Directory /workspace/2.hmac_back_pressure/latest

Test location /workspace/coverage/default/2.hmac_burst_wr.45319166075812316435176040187940736029671577204379318715567993457952025421377
Short name T438
Test name
Test status
Simulation time 4504100639 ps
CPU time 36.33 seconds
Started Nov 22 01:08:51 PM PST 23
Finished Nov 22 01:09:34 PM PST 23
Peak memory 198404 kb
Host smart-42c7faaf-e779-4b63-8b29-3a3184b9362d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45319166075812316435176040187940736029671577204379318715567993457952025421377 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.hmac_burst_wr.45319166075812316435176040187940736029671577204379318715567993457952025421377
Directory /workspace/2.hmac_burst_wr/latest

Test location /workspace/coverage/default/2.hmac_datapath_stress.105940430946992492913127364216761571733721399334156038920386935262725033344371
Short name T231
Test name
Test status
Simulation time 4863401336 ps
CPU time 144.64 seconds
Started Nov 22 01:08:39 PM PST 23
Finished Nov 22 01:11:14 PM PST 23
Peak memory 198560 kb
Host smart-78f742af-edcd-4bc8-bbf2-ec94736ceb2b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=105940430946992492913127364216761571733721399334156038920386935262725033344371 -assert nopostproc +UVM_TE
STNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 2.hmac_datapath_stress.105940430946992492913127364216761571733721399334156038920386935262725033344371
Directory /workspace/2.hmac_datapath_stress/latest

Test location /workspace/coverage/default/2.hmac_error.29160340375216389500401582383969836164183196061455605838934508815962230684133
Short name T55
Test name
Test status
Simulation time 26556692074 ps
CPU time 188.44 seconds
Started Nov 22 01:08:54 PM PST 23
Finished Nov 22 01:12:08 PM PST 23
Peak memory 198372 kb
Host smart-e2e7f238-1534-40e0-b17e-f722055865a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29160340375216389500401582383969836164183196061455605838934508815962230684133 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 2.hmac_error.29160340375216389500401582383969836164183196061455605838934508815962230684133
Directory /workspace/2.hmac_error/latest

Test location /workspace/coverage/default/2.hmac_long_msg.87677331053141616040744097488358942413288926881493730548061886604214269576179
Short name T72
Test name
Test status
Simulation time 14959266997 ps
CPU time 113.35 seconds
Started Nov 22 01:08:51 PM PST 23
Finished Nov 22 01:10:52 PM PST 23
Peak memory 198396 kb
Host smart-43163c7a-4703-4111-ad10-4f61c980eb31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87677331053141616040744097488358942413288926881493730548061886604214269576179 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.hmac_long_msg.87677331053141616040744097488358942413288926881493730548061886604214269576179
Directory /workspace/2.hmac_long_msg/latest

Test location /workspace/coverage/default/2.hmac_sec_cm.96946850882075950253238568130289605488187099663952815573546936731997788378989
Short name T59
Test name
Test status
Simulation time 100939436 ps
CPU time 0.91 seconds
Started Nov 22 01:08:54 PM PST 23
Finished Nov 22 01:09:00 PM PST 23
Peak memory 215612 kb
Host smart-2dc8477c-2273-4820-82a9-d860c6b5f184
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96946850882075950253238568130289605488187099663952815573546936731997788378989 -assert nopostpro
c +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 2.hmac_sec_cm.96946850882075950253238568130289605488187099663952815573546936731997788378989
Directory /workspace/2.hmac_sec_cm/latest

Test location /workspace/coverage/default/2.hmac_smoke.80133811875413371969378463505251246525092840922266994716620526854231328822815
Short name T613
Test name
Test status
Simulation time 631560191 ps
CPU time 4.19 seconds
Started Nov 22 01:08:38 PM PST 23
Finished Nov 22 01:08:53 PM PST 23
Peak memory 198520 kb
Host smart-cdd27d46-9a02-4a5e-b103-6f60ae8d393c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80133811875413371969378463505251246525092840922266994716620526854231328822815 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 2.hmac_smoke.80133811875413371969378463505251246525092840922266994716620526854231328822815
Directory /workspace/2.hmac_smoke/latest

Test location /workspace/coverage/default/2.hmac_stress_all.57838944047028290700199166857587929851447921752472655777603051335111547921490
Short name T727
Test name
Test status
Simulation time 146644856361 ps
CPU time 1148.14 seconds
Started Nov 22 01:08:58 PM PST 23
Finished Nov 22 01:28:15 PM PST 23
Peak memory 210712 kb
Host smart-39a891bc-55e3-4f86-8b8f-281781fefa26
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578389440470282907001991
66857587929851447921752472655777603051335111547921490 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all.578389440470282907001991
66857587929851447921752472655777603051335111547921490
Directory /workspace/2.hmac_stress_all/latest

Test location /workspace/coverage/default/2.hmac_stress_all_with_rand_reset.9352296417047719069391292118057253555540612616806812866747958869601210407272
Short name T347
Test name
Test status
Simulation time 80460760838 ps
CPU time 701.61 seconds
Started Nov 22 01:08:55 PM PST 23
Finished Nov 22 01:20:41 PM PST 23
Peak memory 209196 kb
Host smart-4764dc28-86ad-4469-baaf-cf1ab0c21558
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=9352296417047719069391292118057253555540612616806812866747958869601210407272 -assert nopostproc +UVM_TEST
NAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 2.hmac_stress_all_with_rand_reset.9352296417047719069391292118057253555540612616806812866747958869601210407272
Directory /workspace/2.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.hmac_test_hmac_vectors.70574440228493756597381752921324929350481181757294743128214823796096026335586
Short name T713
Test name
Test status
Simulation time 76314633 ps
CPU time 0.92 seconds
Started Nov 22 01:08:54 PM PST 23
Finished Nov 22 01:09:00 PM PST 23
Peak memory 195596 kb
Host smart-caa4d1f0-b69a-4047-ac0a-a69d1354dc6d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70574440228493756597381752921324929350481181757294743
128214823796096026335586 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac_vectors.705744402284937565973817529213249293504
81181757294743128214823796096026335586
Directory /workspace/2.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha_vectors.5263718959513031112899756507280125566781367695771805646999110818749227347359
Short name T545
Test name
Test status
Simulation time 63914107498 ps
CPU time 454.23 seconds
Started Nov 22 01:08:54 PM PST 23
Finished Nov 22 01:16:33 PM PST 23
Peak memory 198360 kb
Host smart-a94ef277-04ab-4024-9a16-751d77182f10
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52637189595130311128997565072801255667813676957718056
46999110818749227347359 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha_vectors.526371895951303111289975650728012556678136
7695771805646999110818749227347359
Directory /workspace/2.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/2.hmac_wipe_secret.101764920358933240280360574505923469249884402571340943965965237157710912737127
Short name T261
Test name
Test status
Simulation time 8070750677 ps
CPU time 61.99 seconds
Started Nov 22 01:08:54 PM PST 23
Finished Nov 22 01:10:01 PM PST 23
Peak memory 198384 kb
Host smart-79f437c4-6708-458f-8d38-b0185e192383
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101764920358933240280360574505923469249884402571340943965965237157710912737127 -assert nopostproc +UVM_TESTNAME=hmac_bas
e_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 2.hmac_wipe_secret.101764920358933240280360574505923469249884402571340943965965237157710912737127
Directory /workspace/2.hmac_wipe_secret/latest

Test location /workspace/coverage/default/20.hmac_alert_test.66626071296452619640327285519538684381138975135438907513107929279813448010827
Short name T642
Test name
Test status
Simulation time 18011528 ps
CPU time 0.55 seconds
Started Nov 22 01:10:05 PM PST 23
Finished Nov 22 01:10:10 PM PST 23
Peak memory 192856 kb
Host smart-fc51093c-b0ca-4cb4-9aac-9da5078244f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66626071296452619640327285519538684381138975135438907513107929279813448010827 -assert nopostpr
oc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 20.hmac_alert_test.66626071296452619640327285519538684381138975135438907513107929279813448010827
Directory /workspace/20.hmac_alert_test/latest

Test location /workspace/coverage/default/20.hmac_back_pressure.108383513119290566809319269259219698223259708157679371673670124885576747549665
Short name T378
Test name
Test status
Simulation time 2592169506 ps
CPU time 51.59 seconds
Started Nov 22 01:09:59 PM PST 23
Finished Nov 22 01:10:52 PM PST 23
Peak memory 231352 kb
Host smart-8c161ba8-386b-4d5b-b1c4-cfe1aa23360d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=108383513119290566809319269259219698223259708157679371673670124885576747549665 -assert nopostproc +UVM_TE
STNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 20.hmac_back_pressure.108383513119290566809319269259219698223259708157679371673670124885576747549665
Directory /workspace/20.hmac_back_pressure/latest

Test location /workspace/coverage/default/20.hmac_burst_wr.48344803263071342147693822949880855124764910069794705087480873468071051042652
Short name T250
Test name
Test status
Simulation time 4504100639 ps
CPU time 37.78 seconds
Started Nov 22 01:10:01 PM PST 23
Finished Nov 22 01:10:42 PM PST 23
Peak memory 198572 kb
Host smart-b4c427e5-729f-49fb-a8a7-7e00cc493566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48344803263071342147693822949880855124764910069794705087480873468071051042652 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 20.hmac_burst_wr.48344803263071342147693822949880855124764910069794705087480873468071051042652
Directory /workspace/20.hmac_burst_wr/latest

Test location /workspace/coverage/default/20.hmac_datapath_stress.42641857801675321572199622967049130392868496436509583149363436470868408218882
Short name T328
Test name
Test status
Simulation time 4863401336 ps
CPU time 141.43 seconds
Started Nov 22 01:09:58 PM PST 23
Finished Nov 22 01:12:21 PM PST 23
Peak memory 198596 kb
Host smart-aeb90539-c0f7-4814-afb5-7f39c4a49987
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=42641857801675321572199622967049130392868496436509583149363436470868408218882 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 20.hmac_datapath_stress.42641857801675321572199622967049130392868496436509583149363436470868408218882
Directory /workspace/20.hmac_datapath_stress/latest

Test location /workspace/coverage/default/20.hmac_error.109915993267027937041073705506109012626071744835672585302887385344264977539898
Short name T676
Test name
Test status
Simulation time 26556692074 ps
CPU time 189.75 seconds
Started Nov 22 01:10:04 PM PST 23
Finished Nov 22 01:13:19 PM PST 23
Peak memory 198540 kb
Host smart-68a02b4c-7784-45be-96f5-5eca8680a041
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109915993267027937041073705506109012626071744835672585302887385344264977539898 -assert nopostproc +UVM_TESTNAME=hmac_bas
e_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 20.hmac_error.109915993267027937041073705506109012626071744835672585302887385344264977539898
Directory /workspace/20.hmac_error/latest

Test location /workspace/coverage/default/20.hmac_long_msg.44109979340299168102612345258117124513278263379870015758702889729277182545441
Short name T728
Test name
Test status
Simulation time 14959266997 ps
CPU time 117.47 seconds
Started Nov 22 01:09:49 PM PST 23
Finished Nov 22 01:11:48 PM PST 23
Peak memory 198576 kb
Host smart-1fe5bba5-d0df-4d8e-afa9-03d5fc09f600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44109979340299168102612345258117124513278263379870015758702889729277182545441 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 20.hmac_long_msg.44109979340299168102612345258117124513278263379870015758702889729277182545441
Directory /workspace/20.hmac_long_msg/latest

Test location /workspace/coverage/default/20.hmac_smoke.41727245499162642900864861839231284078386102435165143411376254499433465921518
Short name T875
Test name
Test status
Simulation time 631560191 ps
CPU time 4.35 seconds
Started Nov 22 01:09:49 PM PST 23
Finished Nov 22 01:09:55 PM PST 23
Peak memory 198524 kb
Host smart-45da37b5-a755-44c3-8d92-5f81cdfbe7d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41727245499162642900864861839231284078386102435165143411376254499433465921518 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 20.hmac_smoke.41727245499162642900864861839231284078386102435165143411376254499433465921518
Directory /workspace/20.hmac_smoke/latest

Test location /workspace/coverage/default/20.hmac_stress_all.14187903462946901795139139249532991261365455337865253448273327158259758923519
Short name T415
Test name
Test status
Simulation time 146644856361 ps
CPU time 1122.12 seconds
Started Nov 22 01:10:20 PM PST 23
Finished Nov 22 01:29:05 PM PST 23
Peak memory 210860 kb
Host smart-f32b1aa1-96e7-4636-b42e-d22f82a9811f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141879034629469017951391
39249532991261365455337865253448273327158259758923519 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_stress_all.14187903462946901795139
139249532991261365455337865253448273327158259758923519
Directory /workspace/20.hmac_stress_all/latest

Test location /workspace/coverage/default/20.hmac_stress_all_with_rand_reset.99059900930873473175396545301395962498459752265395358747775355691692138012441
Short name T512
Test name
Test status
Simulation time 80460760838 ps
CPU time 701.59 seconds
Started Nov 22 01:10:06 PM PST 23
Finished Nov 22 01:21:52 PM PST 23
Peak memory 209324 kb
Host smart-964b8f16-2cda-4d0a-a370-fafd66689c60
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=99059900930873473175396545301395962498459752265395358747775355691692138012441 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 20.hmac_stress_all_with_rand_reset.99059900930873473175396545301395962498459752265395358747775355691692138012441
Directory /workspace/20.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.hmac_test_hmac_vectors.47531240351334139783581111534353088046485854834526445780258927001994521604698
Short name T630
Test name
Test status
Simulation time 76314633 ps
CPU time 0.9 seconds
Started Nov 22 01:10:07 PM PST 23
Finished Nov 22 01:10:12 PM PST 23
Peak memory 195652 kb
Host smart-6e832544-635d-4959-b16b-3eabba80d5c2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47531240351334139783581111534353088046485854834526445
780258927001994521604698 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_test_hmac_vectors.47531240351334139783581111534353088046
485854834526445780258927001994521604698
Directory /workspace/20.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/20.hmac_test_sha_vectors.27969355037671744228920859132344437758817947037559058652274330116872198414274
Short name T461
Test name
Test status
Simulation time 63914107498 ps
CPU time 451.09 seconds
Started Nov 22 01:09:56 PM PST 23
Finished Nov 22 01:17:28 PM PST 23
Peak memory 198588 kb
Host smart-7bfe0930-46e6-4457-8565-1e60326c57b9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27969355037671744228920859132344437758817947037559058
652274330116872198414274 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_test_sha_vectors.2796935503767174422892085913234443775881
7947037559058652274330116872198414274
Directory /workspace/20.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/20.hmac_wipe_secret.32324195006714409312186905532572478763102091056215072955627011194164631198314
Short name T645
Test name
Test status
Simulation time 8070750677 ps
CPU time 62.1 seconds
Started Nov 22 01:10:01 PM PST 23
Finished Nov 22 01:11:05 PM PST 23
Peak memory 198616 kb
Host smart-48da7a81-5ae1-4698-831d-fefd5afa3e29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32324195006714409312186905532572478763102091056215072955627011194164631198314 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 20.hmac_wipe_secret.32324195006714409312186905532572478763102091056215072955627011194164631198314
Directory /workspace/20.hmac_wipe_secret/latest

Test location /workspace/coverage/default/21.hmac_alert_test.71844036161862913770883420287520708359746517383009926927045583602393387226499
Short name T200
Test name
Test status
Simulation time 18011528 ps
CPU time 0.55 seconds
Started Nov 22 01:10:02 PM PST 23
Finished Nov 22 01:10:05 PM PST 23
Peak memory 192884 kb
Host smart-559d686b-697d-47b9-8180-fc078c779f03
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71844036161862913770883420287520708359746517383009926927045583602393387226499 -assert nopostpr
oc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 21.hmac_alert_test.71844036161862913770883420287520708359746517383009926927045583602393387226499
Directory /workspace/21.hmac_alert_test/latest

Test location /workspace/coverage/default/21.hmac_back_pressure.104173298505499304552503297928682162651894132380312279134804991732931529577496
Short name T551
Test name
Test status
Simulation time 2592169506 ps
CPU time 46.14 seconds
Started Nov 22 01:10:20 PM PST 23
Finished Nov 22 01:11:10 PM PST 23
Peak memory 231372 kb
Host smart-b74eff3f-7ccb-41d9-a6d9-6ef3ce519df7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=104173298505499304552503297928682162651894132380312279134804991732931529577496 -assert nopostproc +UVM_TE
STNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 21.hmac_back_pressure.104173298505499304552503297928682162651894132380312279134804991732931529577496
Directory /workspace/21.hmac_back_pressure/latest

Test location /workspace/coverage/default/21.hmac_burst_wr.58696601320989395877857457411046035397206499462266098849056246452918028918325
Short name T782
Test name
Test status
Simulation time 4504100639 ps
CPU time 37.08 seconds
Started Nov 22 01:10:18 PM PST 23
Finished Nov 22 01:10:58 PM PST 23
Peak memory 198460 kb
Host smart-fe1876c1-c7a1-46b4-ad2e-5b84cf686c32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58696601320989395877857457411046035397206499462266098849056246452918028918325 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 21.hmac_burst_wr.58696601320989395877857457411046035397206499462266098849056246452918028918325
Directory /workspace/21.hmac_burst_wr/latest

Test location /workspace/coverage/default/21.hmac_datapath_stress.39698659671921688061442475584290408550572510679706622392008149641907639907961
Short name T295
Test name
Test status
Simulation time 4863401336 ps
CPU time 135.33 seconds
Started Nov 22 01:10:14 PM PST 23
Finished Nov 22 01:12:33 PM PST 23
Peak memory 198368 kb
Host smart-f07bdb13-74ae-44e7-8672-fcff713cb693
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=39698659671921688061442475584290408550572510679706622392008149641907639907961 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 21.hmac_datapath_stress.39698659671921688061442475584290408550572510679706622392008149641907639907961
Directory /workspace/21.hmac_datapath_stress/latest

Test location /workspace/coverage/default/21.hmac_error.100117347208048674412594520802670883063073424740965305572881717213054587575388
Short name T465
Test name
Test status
Simulation time 26556692074 ps
CPU time 192.54 seconds
Started Nov 22 01:10:02 PM PST 23
Finished Nov 22 01:13:18 PM PST 23
Peak memory 198604 kb
Host smart-b15ac8b6-57af-42c6-b37f-ee28ac2b48f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100117347208048674412594520802670883063073424740965305572881717213054587575388 -assert nopostproc +UVM_TESTNAME=hmac_bas
e_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 21.hmac_error.100117347208048674412594520802670883063073424740965305572881717213054587575388
Directory /workspace/21.hmac_error/latest

Test location /workspace/coverage/default/21.hmac_long_msg.35970369722201134885368171433804823051662038389448745586192232006004582907125
Short name T297
Test name
Test status
Simulation time 14959266997 ps
CPU time 118.94 seconds
Started Nov 22 01:10:03 PM PST 23
Finished Nov 22 01:12:07 PM PST 23
Peak memory 198556 kb
Host smart-c3abb54b-20b3-4730-93e0-769ca80b9be9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35970369722201134885368171433804823051662038389448745586192232006004582907125 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 21.hmac_long_msg.35970369722201134885368171433804823051662038389448745586192232006004582907125
Directory /workspace/21.hmac_long_msg/latest

Test location /workspace/coverage/default/21.hmac_smoke.40929465092007661186436136599315029171344269900622600060251870993620369159761
Short name T612
Test name
Test status
Simulation time 631560191 ps
CPU time 4.07 seconds
Started Nov 22 01:10:13 PM PST 23
Finished Nov 22 01:10:22 PM PST 23
Peak memory 198492 kb
Host smart-8c40efb4-29d4-46b6-9b29-21f38e1e3d6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40929465092007661186436136599315029171344269900622600060251870993620369159761 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 21.hmac_smoke.40929465092007661186436136599315029171344269900622600060251870993620369159761
Directory /workspace/21.hmac_smoke/latest

Test location /workspace/coverage/default/21.hmac_stress_all.73687033334215258293883165887358816474087033729942571444962126275503129365802
Short name T751
Test name
Test status
Simulation time 146644856361 ps
CPU time 1139.03 seconds
Started Nov 22 01:10:17 PM PST 23
Finished Nov 22 01:29:19 PM PST 23
Peak memory 210884 kb
Host smart-90b06f64-0e04-4564-8208-f18ce01f8e81
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736870333342152582938831
65887358816474087033729942571444962126275503129365802 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_stress_all.73687033334215258293883
165887358816474087033729942571444962126275503129365802
Directory /workspace/21.hmac_stress_all/latest

Test location /workspace/coverage/default/21.hmac_stress_all_with_rand_reset.37835447420960834459010870128966091151174280584336058926524702358109433439157
Short name T629
Test name
Test status
Simulation time 80460760838 ps
CPU time 697.24 seconds
Started Nov 22 01:10:24 PM PST 23
Finished Nov 22 01:22:05 PM PST 23
Peak memory 209176 kb
Host smart-70dc207b-5671-48ff-9a65-39494295e070
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=37835447420960834459010870128966091151174280584336058926524702358109433439157 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 21.hmac_stress_all_with_rand_reset.37835447420960834459010870128966091151174280584336058926524702358109433439157
Directory /workspace/21.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.hmac_test_hmac_vectors.19269604862032626034980569723001260131380659370712183595552790152598707010874
Short name T330
Test name
Test status
Simulation time 76314633 ps
CPU time 0.87 seconds
Started Nov 22 01:10:13 PM PST 23
Finished Nov 22 01:10:18 PM PST 23
Peak memory 195820 kb
Host smart-83cb2609-2814-4f90-9ca6-5bcae3e505e2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19269604862032626034980569723001260131380659370712183
595552790152598707010874 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_test_hmac_vectors.19269604862032626034980569723001260131
380659370712183595552790152598707010874
Directory /workspace/21.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/21.hmac_test_sha_vectors.14557405887872118397778520316832398957595161730811354194708647848744888022141
Short name T509
Test name
Test status
Simulation time 63914107498 ps
CPU time 465.33 seconds
Started Nov 22 01:10:24 PM PST 23
Finished Nov 22 01:18:13 PM PST 23
Peak memory 198388 kb
Host smart-a86cf3a3-d8de-4a13-ae02-92f48500fe59
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14557405887872118397778520316832398957595161730811354
194708647848744888022141 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_test_sha_vectors.1455740588787211839777852031683239895759
5161730811354194708647848744888022141
Directory /workspace/21.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/21.hmac_wipe_secret.106660264307181343759367480108845354422796171551002030969441520092701242204367
Short name T463
Test name
Test status
Simulation time 8070750677 ps
CPU time 63.49 seconds
Started Nov 22 01:10:12 PM PST 23
Finished Nov 22 01:11:20 PM PST 23
Peak memory 198604 kb
Host smart-8b5045b0-915c-4bf2-9f13-92936ada13ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106660264307181343759367480108845354422796171551002030969441520092701242204367 -assert nopostproc +UVM_TESTNAME=hmac_bas
e_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 21.hmac_wipe_secret.106660264307181343759367480108845354422796171551002030969441520092701242204367
Directory /workspace/21.hmac_wipe_secret/latest

Test location /workspace/coverage/default/22.hmac_alert_test.7105129094342034838368538808389702586342210651289220748070086946200949443835
Short name T68
Test name
Test status
Simulation time 18011528 ps
CPU time 0.55 seconds
Started Nov 22 01:10:21 PM PST 23
Finished Nov 22 01:10:27 PM PST 23
Peak memory 192836 kb
Host smart-683313b6-24ae-4fb4-b4ed-b3d298286995
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7105129094342034838368538808389702586342210651289220748070086946200949443835 -assert nopostpro
c +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 22.hmac_alert_test.7105129094342034838368538808389702586342210651289220748070086946200949443835
Directory /workspace/22.hmac_alert_test/latest

Test location /workspace/coverage/default/22.hmac_back_pressure.48808098428770540402360681791746028195957779825983400348661533013552631443688
Short name T345
Test name
Test status
Simulation time 2592169506 ps
CPU time 47.17 seconds
Started Nov 22 01:10:10 PM PST 23
Finished Nov 22 01:11:02 PM PST 23
Peak memory 231376 kb
Host smart-b4607139-a610-44b1-a4ad-454f49864638
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=48808098428770540402360681791746028195957779825983400348661533013552631443688 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 22.hmac_back_pressure.48808098428770540402360681791746028195957779825983400348661533013552631443688
Directory /workspace/22.hmac_back_pressure/latest

Test location /workspace/coverage/default/22.hmac_burst_wr.73751284488016168187674663797511827959581526287038995841364791167499901006337
Short name T528
Test name
Test status
Simulation time 4504100639 ps
CPU time 36.31 seconds
Started Nov 22 01:11:04 PM PST 23
Finished Nov 22 01:11:41 PM PST 23
Peak memory 198372 kb
Host smart-f3364f1c-e29c-45b6-93a6-daee57d80f03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73751284488016168187674663797511827959581526287038995841364791167499901006337 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 22.hmac_burst_wr.73751284488016168187674663797511827959581526287038995841364791167499901006337
Directory /workspace/22.hmac_burst_wr/latest

Test location /workspace/coverage/default/22.hmac_datapath_stress.38572123903152824040039393639745754962786506997427756780899817593609510585799
Short name T856
Test name
Test status
Simulation time 4863401336 ps
CPU time 142.68 seconds
Started Nov 22 01:10:16 PM PST 23
Finished Nov 22 01:12:42 PM PST 23
Peak memory 198588 kb
Host smart-c99ca43f-c733-4484-b964-8043dc985013
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=38572123903152824040039393639745754962786506997427756780899817593609510585799 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 22.hmac_datapath_stress.38572123903152824040039393639745754962786506997427756780899817593609510585799
Directory /workspace/22.hmac_datapath_stress/latest

Test location /workspace/coverage/default/22.hmac_error.48491310595243807704474290654552569393721332985205670080882036475715004657416
Short name T874
Test name
Test status
Simulation time 26556692074 ps
CPU time 182.4 seconds
Started Nov 22 01:10:19 PM PST 23
Finished Nov 22 01:13:24 PM PST 23
Peak memory 198456 kb
Host smart-b9dba772-4270-4b65-9ba8-edbd1b05e64c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48491310595243807704474290654552569393721332985205670080882036475715004657416 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 22.hmac_error.48491310595243807704474290654552569393721332985205670080882036475715004657416
Directory /workspace/22.hmac_error/latest

Test location /workspace/coverage/default/22.hmac_long_msg.31129783853125318338530633689807252162991753255821927517997210070540603335605
Short name T443
Test name
Test status
Simulation time 14959266997 ps
CPU time 118.49 seconds
Started Nov 22 01:10:18 PM PST 23
Finished Nov 22 01:12:19 PM PST 23
Peak memory 197488 kb
Host smart-844311b6-1da8-47b7-8c32-d009462c9d81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31129783853125318338530633689807252162991753255821927517997210070540603335605 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 22.hmac_long_msg.31129783853125318338530633689807252162991753255821927517997210070540603335605
Directory /workspace/22.hmac_long_msg/latest

Test location /workspace/coverage/default/22.hmac_smoke.65305770278023125094736175127683803196347457797696540828200933710369403431921
Short name T868
Test name
Test status
Simulation time 631560191 ps
CPU time 4.06 seconds
Started Nov 22 01:10:24 PM PST 23
Finished Nov 22 01:10:32 PM PST 23
Peak memory 198348 kb
Host smart-65c393ba-5227-4dae-836e-e629fc2eeb94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65305770278023125094736175127683803196347457797696540828200933710369403431921 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 22.hmac_smoke.65305770278023125094736175127683803196347457797696540828200933710369403431921
Directory /workspace/22.hmac_smoke/latest

Test location /workspace/coverage/default/22.hmac_stress_all.22601320348771063495158005846754015748912314409753187706518943788941855159663
Short name T377
Test name
Test status
Simulation time 146644856361 ps
CPU time 1140.15 seconds
Started Nov 22 01:10:20 PM PST 23
Finished Nov 22 01:29:23 PM PST 23
Peak memory 210732 kb
Host smart-081e7d10-aeef-4b33-a791-2a982cec4d9a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226013203487710634951580
05846754015748912314409753187706518943788941855159663 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_stress_all.22601320348771063495158
005846754015748912314409753187706518943788941855159663
Directory /workspace/22.hmac_stress_all/latest

Test location /workspace/coverage/default/22.hmac_stress_all_with_rand_reset.48537595660090677380355807639816607397646158095307734876837505950485474038797
Short name T765
Test name
Test status
Simulation time 80460760838 ps
CPU time 708.9 seconds
Started Nov 22 01:09:39 PM PST 23
Finished Nov 22 01:21:30 PM PST 23
Peak memory 209180 kb
Host smart-d2d78179-1b67-4ac0-a9d0-b3c218e1ab58
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=48537595660090677380355807639816607397646158095307734876837505950485474038797 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 22.hmac_stress_all_with_rand_reset.48537595660090677380355807639816607397646158095307734876837505950485474038797
Directory /workspace/22.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.hmac_test_hmac_vectors.28075653923006372815736449540367841051117892203375565487757512967070453763675
Short name T759
Test name
Test status
Simulation time 76314633 ps
CPU time 0.86 seconds
Started Nov 22 01:10:19 PM PST 23
Finished Nov 22 01:10:23 PM PST 23
Peak memory 195648 kb
Host smart-eed30f18-3891-4aad-8d8e-5c0edb33bdf3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28075653923006372815736449540367841051117892203375565
487757512967070453763675 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_test_hmac_vectors.28075653923006372815736449540367841051
117892203375565487757512967070453763675
Directory /workspace/22.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/22.hmac_test_sha_vectors.81634430652687797767517799378440126256266066061782577129595074967321645643976
Short name T853
Test name
Test status
Simulation time 63914107498 ps
CPU time 460.9 seconds
Started Nov 22 01:10:11 PM PST 23
Finished Nov 22 01:17:56 PM PST 23
Peak memory 198608 kb
Host smart-9ab7084b-e136-42ce-b098-58772b42ff7e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81634430652687797767517799378440126256266066061782577
129595074967321645643976 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_test_sha_vectors.8163443065268779776751779937844012625626
6066061782577129595074967321645643976
Directory /workspace/22.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/22.hmac_wipe_secret.86627763008060770391332739325156886633753717372442896641072776398556250840112
Short name T343
Test name
Test status
Simulation time 8070750677 ps
CPU time 61.06 seconds
Started Nov 22 01:10:48 PM PST 23
Finished Nov 22 01:11:51 PM PST 23
Peak memory 198264 kb
Host smart-0aa62dcb-76d2-4706-a922-1bc0b0dcaa7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86627763008060770391332739325156886633753717372442896641072776398556250840112 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 22.hmac_wipe_secret.86627763008060770391332739325156886633753717372442896641072776398556250840112
Directory /workspace/22.hmac_wipe_secret/latest

Test location /workspace/coverage/default/23.hmac_alert_test.64899126203474889492623857597997659678782372366256618293292047631834414426086
Short name T269
Test name
Test status
Simulation time 18011528 ps
CPU time 0.57 seconds
Started Nov 22 01:10:04 PM PST 23
Finished Nov 22 01:10:10 PM PST 23
Peak memory 192404 kb
Host smart-6b0c88c7-5450-41db-8cf1-cede8cbe2f38
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64899126203474889492623857597997659678782372366256618293292047631834414426086 -assert nopostpr
oc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 23.hmac_alert_test.64899126203474889492623857597997659678782372366256618293292047631834414426086
Directory /workspace/23.hmac_alert_test/latest

Test location /workspace/coverage/default/23.hmac_back_pressure.19318723173767203315570937861979152038075967176778127481671047282070050807884
Short name T643
Test name
Test status
Simulation time 2592169506 ps
CPU time 49.83 seconds
Started Nov 22 01:10:18 PM PST 23
Finished Nov 22 01:11:10 PM PST 23
Peak memory 231268 kb
Host smart-7adbc0b2-7f38-45a4-bf53-8a5ae6146b2f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=19318723173767203315570937861979152038075967176778127481671047282070050807884 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 23.hmac_back_pressure.19318723173767203315570937861979152038075967176778127481671047282070050807884
Directory /workspace/23.hmac_back_pressure/latest

Test location /workspace/coverage/default/23.hmac_burst_wr.81162117993946744426753855753886204903783981497013609491307265440684498637860
Short name T549
Test name
Test status
Simulation time 4504100639 ps
CPU time 37.89 seconds
Started Nov 22 01:10:20 PM PST 23
Finished Nov 22 01:11:01 PM PST 23
Peak memory 198568 kb
Host smart-68d857b1-09da-4cc4-9936-e58bb697204f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81162117993946744426753855753886204903783981497013609491307265440684498637860 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 23.hmac_burst_wr.81162117993946744426753855753886204903783981497013609491307265440684498637860
Directory /workspace/23.hmac_burst_wr/latest

Test location /workspace/coverage/default/23.hmac_datapath_stress.92206536991944002152802878356308305504437060435706620823811672186729420040704
Short name T39
Test name
Test status
Simulation time 4863401336 ps
CPU time 141.02 seconds
Started Nov 22 01:10:19 PM PST 23
Finished Nov 22 01:12:42 PM PST 23
Peak memory 198604 kb
Host smart-4b658d12-2930-400a-9de3-d4e6dff1d6ad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=92206536991944002152802878356308305504437060435706620823811672186729420040704 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 23.hmac_datapath_stress.92206536991944002152802878356308305504437060435706620823811672186729420040704
Directory /workspace/23.hmac_datapath_stress/latest

Test location /workspace/coverage/default/23.hmac_error.37945880285191897393330548573238226926253392227348804125163397338343278952684
Short name T729
Test name
Test status
Simulation time 26556692074 ps
CPU time 193.34 seconds
Started Nov 22 01:09:43 PM PST 23
Finished Nov 22 01:12:59 PM PST 23
Peak memory 198484 kb
Host smart-a2b1ffbf-bfad-4225-b3fa-912e4410bc03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37945880285191897393330548573238226926253392227348804125163397338343278952684 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 23.hmac_error.37945880285191897393330548573238226926253392227348804125163397338343278952684
Directory /workspace/23.hmac_error/latest

Test location /workspace/coverage/default/23.hmac_long_msg.70759531892766930535030768816038067911547492898409028949053851750872512107490
Short name T762
Test name
Test status
Simulation time 14959266997 ps
CPU time 117.04 seconds
Started Nov 22 01:09:39 PM PST 23
Finished Nov 22 01:11:37 PM PST 23
Peak memory 198576 kb
Host smart-47c186df-a244-4f7b-afe2-8c515f4f2339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70759531892766930535030768816038067911547492898409028949053851750872512107490 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 23.hmac_long_msg.70759531892766930535030768816038067911547492898409028949053851750872512107490
Directory /workspace/23.hmac_long_msg/latest

Test location /workspace/coverage/default/23.hmac_smoke.9354750787992203475878836331465082793780186085727067836027867204076193578431
Short name T306
Test name
Test status
Simulation time 631560191 ps
CPU time 4.17 seconds
Started Nov 22 01:10:20 PM PST 23
Finished Nov 22 01:10:27 PM PST 23
Peak memory 198516 kb
Host smart-738a20d4-282a-4a52-9eaf-62c167463339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9354750787992203475878836331465082793780186085727067836027867204076193578431 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 23.hmac_smoke.9354750787992203475878836331465082793780186085727067836027867204076193578431
Directory /workspace/23.hmac_smoke/latest

Test location /workspace/coverage/default/23.hmac_stress_all.68397609294421146558479875870315148939913443328464941569067660173132410784419
Short name T387
Test name
Test status
Simulation time 146644856361 ps
CPU time 1135.68 seconds
Started Nov 22 01:09:42 PM PST 23
Finished Nov 22 01:28:39 PM PST 23
Peak memory 210832 kb
Host smart-2b82048d-9c0d-44fa-bc30-9467f177a6f3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683976092944211465584798
75870315148939913443328464941569067660173132410784419 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_stress_all.68397609294421146558479
875870315148939913443328464941569067660173132410784419
Directory /workspace/23.hmac_stress_all/latest

Test location /workspace/coverage/default/23.hmac_stress_all_with_rand_reset.41251900141190432178167809290848447691523836821009381232413914327310480598650
Short name T425
Test name
Test status
Simulation time 80460760838 ps
CPU time 695.9 seconds
Started Nov 22 01:09:44 PM PST 23
Finished Nov 22 01:21:23 PM PST 23
Peak memory 209232 kb
Host smart-825bcc77-7c2d-4637-8992-f7f1b66b6d83
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=41251900141190432178167809290848447691523836821009381232413914327310480598650 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 23.hmac_stress_all_with_rand_reset.41251900141190432178167809290848447691523836821009381232413914327310480598650
Directory /workspace/23.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.hmac_test_hmac_vectors.42355187034253213682089003641467371379658238943895237259313473620656987154585
Short name T522
Test name
Test status
Simulation time 76314633 ps
CPU time 0.87 seconds
Started Nov 22 01:09:39 PM PST 23
Finished Nov 22 01:09:42 PM PST 23
Peak memory 195612 kb
Host smart-afbe30fb-3438-4fb7-acc3-0ad91b11f6cd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42355187034253213682089003641467371379658238943895237
259313473620656987154585 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_test_hmac_vectors.42355187034253213682089003641467371379
658238943895237259313473620656987154585
Directory /workspace/23.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/23.hmac_test_sha_vectors.100452126815313459304522684348283169329826710500573794048534521330861252709516
Short name T234
Test name
Test status
Simulation time 63914107498 ps
CPU time 483.53 seconds
Started Nov 22 01:09:52 PM PST 23
Finished Nov 22 01:17:57 PM PST 23
Peak memory 198500 kb
Host smart-ce74e745-7fd6-425b-bb2c-6eda2f42257b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10045212681531345930452268434828316932982671050057379
4048534521330861252709516 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_test_sha_vectors.100452126815313459304522684348283169329
826710500573794048534521330861252709516
Directory /workspace/23.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/23.hmac_wipe_secret.31572032336638277340192239131730332470487774193047205652799855062466113678455
Short name T266
Test name
Test status
Simulation time 8070750677 ps
CPU time 61.14 seconds
Started Nov 22 01:09:49 PM PST 23
Finished Nov 22 01:10:51 PM PST 23
Peak memory 198604 kb
Host smart-fd214d4e-80a8-4326-8d34-790cb8affa97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31572032336638277340192239131730332470487774193047205652799855062466113678455 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 23.hmac_wipe_secret.31572032336638277340192239131730332470487774193047205652799855062466113678455
Directory /workspace/23.hmac_wipe_secret/latest

Test location /workspace/coverage/default/24.hmac_alert_test.95864591638874705211348136952006386421073634594665422104384258515831896126129
Short name T742
Test name
Test status
Simulation time 18011528 ps
CPU time 0.53 seconds
Started Nov 22 01:10:04 PM PST 23
Finished Nov 22 01:10:09 PM PST 23
Peak memory 192840 kb
Host smart-b8a2002c-57f4-45f5-a223-8efad7594500
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95864591638874705211348136952006386421073634594665422104384258515831896126129 -assert nopostpr
oc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 24.hmac_alert_test.95864591638874705211348136952006386421073634594665422104384258515831896126129
Directory /workspace/24.hmac_alert_test/latest

Test location /workspace/coverage/default/24.hmac_back_pressure.36778232382669062790518155562776289622563150642280334245550614450606979199420
Short name T457
Test name
Test status
Simulation time 2592169506 ps
CPU time 46.57 seconds
Started Nov 22 01:10:04 PM PST 23
Finished Nov 22 01:10:56 PM PST 23
Peak memory 230960 kb
Host smart-1f276403-466e-40a1-bd83-d1ca0bb6ad2e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=36778232382669062790518155562776289622563150642280334245550614450606979199420 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 24.hmac_back_pressure.36778232382669062790518155562776289622563150642280334245550614450606979199420
Directory /workspace/24.hmac_back_pressure/latest

Test location /workspace/coverage/default/24.hmac_burst_wr.8970644404798966335901905509099053018339692976005328352080525292149973209190
Short name T194
Test name
Test status
Simulation time 4504100639 ps
CPU time 37.07 seconds
Started Nov 22 01:10:10 PM PST 23
Finished Nov 22 01:10:52 PM PST 23
Peak memory 198476 kb
Host smart-8e6a1351-40b5-4edd-97eb-b61c250a36a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8970644404798966335901905509099053018339692976005328352080525292149973209190 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 24.hmac_burst_wr.8970644404798966335901905509099053018339692976005328352080525292149973209190
Directory /workspace/24.hmac_burst_wr/latest

Test location /workspace/coverage/default/24.hmac_datapath_stress.15194389245242236183507626794103287662244732857542647960708028793766372531785
Short name T842
Test name
Test status
Simulation time 4863401336 ps
CPU time 143.06 seconds
Started Nov 22 01:09:52 PM PST 23
Finished Nov 22 01:12:16 PM PST 23
Peak memory 198524 kb
Host smart-5055d948-0f18-46a8-8d90-0436376a20d9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=15194389245242236183507626794103287662244732857542647960708028793766372531785 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 24.hmac_datapath_stress.15194389245242236183507626794103287662244732857542647960708028793766372531785
Directory /workspace/24.hmac_datapath_stress/latest

Test location /workspace/coverage/default/24.hmac_error.92495784405730011128505095217521970770328663335337592464888537306679028375462
Short name T544
Test name
Test status
Simulation time 26556692074 ps
CPU time 183.55 seconds
Started Nov 22 01:10:02 PM PST 23
Finished Nov 22 01:13:08 PM PST 23
Peak memory 198484 kb
Host smart-2fb338cb-e3a6-433d-8ee2-7605896c5de7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92495784405730011128505095217521970770328663335337592464888537306679028375462 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 24.hmac_error.92495784405730011128505095217521970770328663335337592464888537306679028375462
Directory /workspace/24.hmac_error/latest

Test location /workspace/coverage/default/24.hmac_long_msg.93817761070094850546951368871250570801452227039830524054863789247769114505482
Short name T754
Test name
Test status
Simulation time 14959266997 ps
CPU time 114.95 seconds
Started Nov 22 01:09:50 PM PST 23
Finished Nov 22 01:11:46 PM PST 23
Peak memory 198576 kb
Host smart-c98d9a6b-b746-45aa-94ca-de63d80931aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93817761070094850546951368871250570801452227039830524054863789247769114505482 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.hmac_long_msg.93817761070094850546951368871250570801452227039830524054863789247769114505482
Directory /workspace/24.hmac_long_msg/latest

Test location /workspace/coverage/default/24.hmac_smoke.76696237547880704419915430105713416289279865145014763534272772861634096402257
Short name T502
Test name
Test status
Simulation time 631560191 ps
CPU time 4.22 seconds
Started Nov 22 01:09:44 PM PST 23
Finished Nov 22 01:09:50 PM PST 23
Peak memory 198436 kb
Host smart-06b68d03-1e10-434b-b134-f27d46b1f5d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76696237547880704419915430105713416289279865145014763534272772861634096402257 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 24.hmac_smoke.76696237547880704419915430105713416289279865145014763534272772861634096402257
Directory /workspace/24.hmac_smoke/latest

Test location /workspace/coverage/default/24.hmac_stress_all.92928669751734351717992693797859719724201049466669796534633353558712907105964
Short name T190
Test name
Test status
Simulation time 146644856361 ps
CPU time 1112.07 seconds
Started Nov 22 01:09:58 PM PST 23
Finished Nov 22 01:28:31 PM PST 23
Peak memory 210868 kb
Host smart-981f162b-e5e6-4527-8681-28baf1cf1a71
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929286697517343517179926
93797859719724201049466669796534633353558712907105964 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_stress_all.92928669751734351717992
693797859719724201049466669796534633353558712907105964
Directory /workspace/24.hmac_stress_all/latest

Test location /workspace/coverage/default/24.hmac_stress_all_with_rand_reset.112133504370789752851212232923606193533155693241782946173886211721462678827256
Short name T541
Test name
Test status
Simulation time 80460760838 ps
CPU time 703.93 seconds
Started Nov 22 01:10:03 PM PST 23
Finished Nov 22 01:21:52 PM PST 23
Peak memory 209352 kb
Host smart-24d1d7aa-9de2-43fa-9837-05fe2647443c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=112133504370789752851212232923606193533155693241782946173886211721462678827256 -assert nopostproc +UVM_TE
STNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 24.hmac_stress_all_with_rand_reset.112133504370789752851212232923606193533155693241782946173886211721462678827256
Directory /workspace/24.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.hmac_test_hmac_vectors.27805130087350298182396931220253257086647791829878246495324811231604342026204
Short name T761
Test name
Test status
Simulation time 76314633 ps
CPU time 0.95 seconds
Started Nov 22 01:09:49 PM PST 23
Finished Nov 22 01:09:52 PM PST 23
Peak memory 195716 kb
Host smart-00321c3a-dcde-4185-b55a-6f0c6a45d346
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27805130087350298182396931220253257086647791829878246
495324811231604342026204 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_test_hmac_vectors.27805130087350298182396931220253257086
647791829878246495324811231604342026204
Directory /workspace/24.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/24.hmac_test_sha_vectors.59539776702650252679179404775620792850042628606060808100582480572575921729315
Short name T318
Test name
Test status
Simulation time 63914107498 ps
CPU time 453.51 seconds
Started Nov 22 01:10:10 PM PST 23
Finished Nov 22 01:17:48 PM PST 23
Peak memory 198592 kb
Host smart-efde81f6-f48a-45bb-adc6-c8e272e59c94
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59539776702650252679179404775620792850042628606060808
100582480572575921729315 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_test_sha_vectors.5953977670265025267917940477562079285004
2628606060808100582480572575921729315
Directory /workspace/24.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/24.hmac_wipe_secret.2464605301201010206736581209751837111000513625192252175527075723874762029176
Short name T784
Test name
Test status
Simulation time 8070750677 ps
CPU time 63.32 seconds
Started Nov 22 01:10:03 PM PST 23
Finished Nov 22 01:11:11 PM PST 23
Peak memory 198588 kb
Host smart-68e5165f-89b5-4545-b010-d67a9d0c359a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464605301201010206736581209751837111000513625192252175527075723874762029176 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 24.hmac_wipe_secret.2464605301201010206736581209751837111000513625192252175527075723874762029176
Directory /workspace/24.hmac_wipe_secret/latest

Test location /workspace/coverage/default/25.hmac_alert_test.98515817124099054777581392940472485934521329606825434242466845592515227563777
Short name T267
Test name
Test status
Simulation time 18011528 ps
CPU time 0.54 seconds
Started Nov 22 01:09:59 PM PST 23
Finished Nov 22 01:10:01 PM PST 23
Peak memory 192884 kb
Host smart-18deb939-fb06-437f-9796-5f9ed665f6ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98515817124099054777581392940472485934521329606825434242466845592515227563777 -assert nopostpr
oc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 25.hmac_alert_test.98515817124099054777581392940472485934521329606825434242466845592515227563777
Directory /workspace/25.hmac_alert_test/latest

Test location /workspace/coverage/default/25.hmac_back_pressure.73816476942680455568304323672502799871109989725480889225714367429370833845465
Short name T659
Test name
Test status
Simulation time 2592169506 ps
CPU time 48.62 seconds
Started Nov 22 01:10:24 PM PST 23
Finished Nov 22 01:11:17 PM PST 23
Peak memory 231192 kb
Host smart-3f4fb473-cbfd-4b51-982d-5f0b6dd4758b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=73816476942680455568304323672502799871109989725480889225714367429370833845465 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 25.hmac_back_pressure.73816476942680455568304323672502799871109989725480889225714367429370833845465
Directory /workspace/25.hmac_back_pressure/latest

Test location /workspace/coverage/default/25.hmac_burst_wr.103393360342931180291441258588340635131428402351295151957424959468186303005822
Short name T218
Test name
Test status
Simulation time 4504100639 ps
CPU time 37.23 seconds
Started Nov 22 01:10:14 PM PST 23
Finished Nov 22 01:10:55 PM PST 23
Peak memory 198576 kb
Host smart-b6f34e24-9380-4a41-895d-41588d1524c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103393360342931180291441258588340635131428402351295151957424959468186303005822 -assert nopostproc +UVM_TESTNAME=hmac_bas
e_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 25.hmac_burst_wr.103393360342931180291441258588340635131428402351295151957424959468186303005822
Directory /workspace/25.hmac_burst_wr/latest

Test location /workspace/coverage/default/25.hmac_datapath_stress.38621401632601009758456935317058380358023304965081994025028327281524192980457
Short name T435
Test name
Test status
Simulation time 4863401336 ps
CPU time 145.68 seconds
Started Nov 22 01:10:09 PM PST 23
Finished Nov 22 01:12:39 PM PST 23
Peak memory 198384 kb
Host smart-b737a7b0-7b2b-4164-a327-75be019612bf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=38621401632601009758456935317058380358023304965081994025028327281524192980457 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 25.hmac_datapath_stress.38621401632601009758456935317058380358023304965081994025028327281524192980457
Directory /workspace/25.hmac_datapath_stress/latest

Test location /workspace/coverage/default/25.hmac_error.25376134022125274130464782961173077965290067985628361113720308976683303693868
Short name T356
Test name
Test status
Simulation time 26556692074 ps
CPU time 194.12 seconds
Started Nov 22 01:10:00 PM PST 23
Finished Nov 22 01:13:16 PM PST 23
Peak memory 198616 kb
Host smart-b3cdaa5d-dcdb-40be-876b-c1de8ab1148e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25376134022125274130464782961173077965290067985628361113720308976683303693868 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 25.hmac_error.25376134022125274130464782961173077965290067985628361113720308976683303693868
Directory /workspace/25.hmac_error/latest

Test location /workspace/coverage/default/25.hmac_long_msg.45118840860249919218183690350207318195519014112014098463870250190477050969021
Short name T608
Test name
Test status
Simulation time 14959266997 ps
CPU time 116.42 seconds
Started Nov 22 01:10:07 PM PST 23
Finished Nov 22 01:12:07 PM PST 23
Peak memory 198576 kb
Host smart-3124c9c1-c049-416f-b0ce-9bd6d2526bbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45118840860249919218183690350207318195519014112014098463870250190477050969021 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 25.hmac_long_msg.45118840860249919218183690350207318195519014112014098463870250190477050969021
Directory /workspace/25.hmac_long_msg/latest

Test location /workspace/coverage/default/25.hmac_smoke.8536273592887965087837132995456093441867526280342813822878990008641236875212
Short name T365
Test name
Test status
Simulation time 631560191 ps
CPU time 4.08 seconds
Started Nov 22 01:10:00 PM PST 23
Finished Nov 22 01:10:06 PM PST 23
Peak memory 198540 kb
Host smart-af0ef4aa-0c94-4e4d-9477-3c133e3b29ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8536273592887965087837132995456093441867526280342813822878990008641236875212 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 25.hmac_smoke.8536273592887965087837132995456093441867526280342813822878990008641236875212
Directory /workspace/25.hmac_smoke/latest

Test location /workspace/coverage/default/25.hmac_stress_all.39328989763930829754478344653074574617461789780030938670897255458183142181355
Short name T357
Test name
Test status
Simulation time 146644856361 ps
CPU time 1146.89 seconds
Started Nov 22 01:10:18 PM PST 23
Finished Nov 22 01:29:27 PM PST 23
Peak memory 210752 kb
Host smart-86fdb9fe-733b-41ad-845d-994f3d82de98
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393289897639308297544783
44653074574617461789780030938670897255458183142181355 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_stress_all.39328989763930829754478
344653074574617461789780030938670897255458183142181355
Directory /workspace/25.hmac_stress_all/latest

Test location /workspace/coverage/default/25.hmac_stress_all_with_rand_reset.81603354321386534511695875039806183672641163912477111043451485977302192081777
Short name T304
Test name
Test status
Simulation time 80460760838 ps
CPU time 712.05 seconds
Started Nov 22 01:10:18 PM PST 23
Finished Nov 22 01:22:13 PM PST 23
Peak memory 208292 kb
Host smart-ee9a1b6c-5b95-4fc8-80df-3153c4ea6063
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=81603354321386534511695875039806183672641163912477111043451485977302192081777 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 25.hmac_stress_all_with_rand_reset.81603354321386534511695875039806183672641163912477111043451485977302192081777
Directory /workspace/25.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.hmac_test_hmac_vectors.75025503940848755917313280550835251767537915313633106226909487153531450101181
Short name T213
Test name
Test status
Simulation time 76314633 ps
CPU time 0.9 seconds
Started Nov 22 01:10:10 PM PST 23
Finished Nov 22 01:10:15 PM PST 23
Peak memory 195808 kb
Host smart-6881f480-911c-4d22-a8cd-f707e00f39d4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75025503940848755917313280550835251767537915313633106
226909487153531450101181 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_test_hmac_vectors.75025503940848755917313280550835251767
537915313633106226909487153531450101181
Directory /workspace/25.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/25.hmac_test_sha_vectors.71687761351075497440746573412729349926184380122385380737578889698283506023481
Short name T778
Test name
Test status
Simulation time 63914107498 ps
CPU time 432.97 seconds
Started Nov 22 01:10:12 PM PST 23
Finished Nov 22 01:17:29 PM PST 23
Peak memory 198372 kb
Host smart-ba4b7bf0-3b59-472b-9f85-611a967be0eb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71687761351075497440746573412729349926184380122385380
737578889698283506023481 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_test_sha_vectors.7168776135107549744074657341272934992618
4380122385380737578889698283506023481
Directory /workspace/25.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/25.hmac_wipe_secret.106951098509576267501968228352652393823364585236978018178507436377978047171365
Short name T526
Test name
Test status
Simulation time 8070750677 ps
CPU time 61.16 seconds
Started Nov 22 01:10:13 PM PST 23
Finished Nov 22 01:11:19 PM PST 23
Peak memory 198608 kb
Host smart-87e1df14-7b0d-42f1-8e83-aed262d0a042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106951098509576267501968228352652393823364585236978018178507436377978047171365 -assert nopostproc +UVM_TESTNAME=hmac_bas
e_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 25.hmac_wipe_secret.106951098509576267501968228352652393823364585236978018178507436377978047171365
Directory /workspace/25.hmac_wipe_secret/latest

Test location /workspace/coverage/default/26.hmac_alert_test.99427870103913086168150382555023450721219761867868058670692314827423481601643
Short name T741
Test name
Test status
Simulation time 18011528 ps
CPU time 0.53 seconds
Started Nov 22 01:10:20 PM PST 23
Finished Nov 22 01:10:24 PM PST 23
Peak memory 192888 kb
Host smart-2cb23bb7-5ed1-48ee-9666-4d27d07af6e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99427870103913086168150382555023450721219761867868058670692314827423481601643 -assert nopostpr
oc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 26.hmac_alert_test.99427870103913086168150382555023450721219761867868058670692314827423481601643
Directory /workspace/26.hmac_alert_test/latest

Test location /workspace/coverage/default/26.hmac_back_pressure.34499573425543370845632114215944544699238593676790091555613012573085263066130
Short name T348
Test name
Test status
Simulation time 2592169506 ps
CPU time 47.5 seconds
Started Nov 22 01:10:13 PM PST 23
Finished Nov 22 01:11:05 PM PST 23
Peak memory 231380 kb
Host smart-339b140a-5776-469b-a8d3-9dfd42d92d73
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=34499573425543370845632114215944544699238593676790091555613012573085263066130 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 26.hmac_back_pressure.34499573425543370845632114215944544699238593676790091555613012573085263066130
Directory /workspace/26.hmac_back_pressure/latest

Test location /workspace/coverage/default/26.hmac_burst_wr.15904435818418933736549679297972620432676548750492646658214019720273336450659
Short name T657
Test name
Test status
Simulation time 4504100639 ps
CPU time 36.75 seconds
Started Nov 22 01:10:10 PM PST 23
Finished Nov 22 01:10:51 PM PST 23
Peak memory 198568 kb
Host smart-44a0e903-be25-40bd-a04c-cf4f0d38af88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15904435818418933736549679297972620432676548750492646658214019720273336450659 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.hmac_burst_wr.15904435818418933736549679297972620432676548750492646658214019720273336450659
Directory /workspace/26.hmac_burst_wr/latest

Test location /workspace/coverage/default/26.hmac_datapath_stress.54181282135246648728499324311717098597792769593154684515510526661936177972780
Short name T301
Test name
Test status
Simulation time 4863401336 ps
CPU time 143.42 seconds
Started Nov 22 01:10:17 PM PST 23
Finished Nov 22 01:12:43 PM PST 23
Peak memory 198588 kb
Host smart-ef6a8368-a96a-4665-badd-9e9db4545a0c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=54181282135246648728499324311717098597792769593154684515510526661936177972780 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 26.hmac_datapath_stress.54181282135246648728499324311717098597792769593154684515510526661936177972780
Directory /workspace/26.hmac_datapath_stress/latest

Test location /workspace/coverage/default/26.hmac_error.101128076996400245966150693647346859197055146890366243956543702379864918563628
Short name T327
Test name
Test status
Simulation time 26556692074 ps
CPU time 189.15 seconds
Started Nov 22 01:10:17 PM PST 23
Finished Nov 22 01:13:29 PM PST 23
Peak memory 198612 kb
Host smart-b48f6d4b-17be-4770-aaac-3dcc043518be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101128076996400245966150693647346859197055146890366243956543702379864918563628 -assert nopostproc +UVM_TESTNAME=hmac_bas
e_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 26.hmac_error.101128076996400245966150693647346859197055146890366243956543702379864918563628
Directory /workspace/26.hmac_error/latest

Test location /workspace/coverage/default/26.hmac_long_msg.69629942478621521501037604939979860355327474079549538371693257079743315870955
Short name T663
Test name
Test status
Simulation time 14959266997 ps
CPU time 114.88 seconds
Started Nov 22 01:10:18 PM PST 23
Finished Nov 22 01:12:15 PM PST 23
Peak memory 198436 kb
Host smart-bbf99432-b8c4-4f0c-a661-1c6ea4c74b24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69629942478621521501037604939979860355327474079549538371693257079743315870955 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.hmac_long_msg.69629942478621521501037604939979860355327474079549538371693257079743315870955
Directory /workspace/26.hmac_long_msg/latest

Test location /workspace/coverage/default/26.hmac_smoke.40652852441373626540790620325784609599673982579681261560166391456215311098960
Short name T684
Test name
Test status
Simulation time 631560191 ps
CPU time 4.13 seconds
Started Nov 22 01:10:13 PM PST 23
Finished Nov 22 01:10:22 PM PST 23
Peak memory 198552 kb
Host smart-d2a5522b-8983-481e-99a5-85e3cc453bab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40652852441373626540790620325784609599673982579681261560166391456215311098960 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 26.hmac_smoke.40652852441373626540790620325784609599673982579681261560166391456215311098960
Directory /workspace/26.hmac_smoke/latest

Test location /workspace/coverage/default/26.hmac_stress_all.65769500036318427083881844945983482351725483651801742935446409218395228287012
Short name T734
Test name
Test status
Simulation time 146644856361 ps
CPU time 1132.15 seconds
Started Nov 22 01:10:21 PM PST 23
Finished Nov 22 01:29:17 PM PST 23
Peak memory 210856 kb
Host smart-9f5fe605-821f-4795-a87e-ac52decc9f0a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657695000363184270838818
44945983482351725483651801742935446409218395228287012 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_stress_all.65769500036318427083881
844945983482351725483651801742935446409218395228287012
Directory /workspace/26.hmac_stress_all/latest

Test location /workspace/coverage/default/26.hmac_stress_all_with_rand_reset.99791044490855793897067187259338814478543768675328811736692998266002549957760
Short name T450
Test name
Test status
Simulation time 80460760838 ps
CPU time 696.72 seconds
Started Nov 22 01:10:21 PM PST 23
Finished Nov 22 01:22:01 PM PST 23
Peak memory 209360 kb
Host smart-8f1d2b5e-e741-4214-a75a-1e9c7df3cd9c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=99791044490855793897067187259338814478543768675328811736692998266002549957760 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 26.hmac_stress_all_with_rand_reset.99791044490855793897067187259338814478543768675328811736692998266002549957760
Directory /workspace/26.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.hmac_test_hmac_vectors.87083196937261390679208130001458736386531147553632243762266824284201940092372
Short name T760
Test name
Test status
Simulation time 76314633 ps
CPU time 0.87 seconds
Started Nov 22 01:10:19 PM PST 23
Finished Nov 22 01:10:22 PM PST 23
Peak memory 195644 kb
Host smart-55cb8b59-f6e0-409f-bbc6-1b4aa8a896d8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87083196937261390679208130001458736386531147553632243
762266824284201940092372 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_test_hmac_vectors.87083196937261390679208130001458736386
531147553632243762266824284201940092372
Directory /workspace/26.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/26.hmac_test_sha_vectors.106175068102025947506400813046716844125529897274380181682538281678173395983354
Short name T344
Test name
Test status
Simulation time 63914107498 ps
CPU time 450.69 seconds
Started Nov 22 01:10:20 PM PST 23
Finished Nov 22 01:17:54 PM PST 23
Peak memory 198580 kb
Host smart-9cc85c86-0712-4b8a-abb5-a63b06f1bf91
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10617506810202594750640081304671684412552989727438018
1682538281678173395983354 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_test_sha_vectors.106175068102025947506400813046716844125
529897274380181682538281678173395983354
Directory /workspace/26.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/26.hmac_wipe_secret.99447835921748001620955944249974122731206043410163126484832752902759542433781
Short name T381
Test name
Test status
Simulation time 8070750677 ps
CPU time 61.72 seconds
Started Nov 22 01:10:18 PM PST 23
Finished Nov 22 01:11:22 PM PST 23
Peak memory 198456 kb
Host smart-7946bee2-fe93-416f-8796-41900de963b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99447835921748001620955944249974122731206043410163126484832752902759542433781 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 26.hmac_wipe_secret.99447835921748001620955944249974122731206043410163126484832752902759542433781
Directory /workspace/26.hmac_wipe_secret/latest

Test location /workspace/coverage/default/27.hmac_alert_test.109725179386195122707795331835195097697632389643907054483998790638167870776273
Short name T525
Test name
Test status
Simulation time 18011528 ps
CPU time 0.55 seconds
Started Nov 22 01:10:08 PM PST 23
Finished Nov 22 01:10:13 PM PST 23
Peak memory 192836 kb
Host smart-7968b39c-7478-44af-8579-f40487e83743
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109725179386195122707795331835195097697632389643907054483998790638167870776273 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 27.hmac_alert_test.109725179386195122707795331835195097697632389643907054483998790638167870776273
Directory /workspace/27.hmac_alert_test/latest

Test location /workspace/coverage/default/27.hmac_back_pressure.54120059821442630200682717286622280503623692138494678777315315619875834656125
Short name T599
Test name
Test status
Simulation time 2592169506 ps
CPU time 47.29 seconds
Started Nov 22 01:10:18 PM PST 23
Finished Nov 22 01:11:08 PM PST 23
Peak memory 231288 kb
Host smart-e358d7a6-c378-40a9-8f98-ed0779dbc296
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=54120059821442630200682717286622280503623692138494678777315315619875834656125 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 27.hmac_back_pressure.54120059821442630200682717286622280503623692138494678777315315619875834656125
Directory /workspace/27.hmac_back_pressure/latest

Test location /workspace/coverage/default/27.hmac_burst_wr.78160981019153980355051181186972719311964291941183535991464297585642854732450
Short name T596
Test name
Test status
Simulation time 4504100639 ps
CPU time 37.87 seconds
Started Nov 22 01:09:52 PM PST 23
Finished Nov 22 01:10:31 PM PST 23
Peak memory 198488 kb
Host smart-2630c445-11f8-4a5b-a9da-7d06bcf32194
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78160981019153980355051181186972719311964291941183535991464297585642854732450 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.hmac_burst_wr.78160981019153980355051181186972719311964291941183535991464297585642854732450
Directory /workspace/27.hmac_burst_wr/latest

Test location /workspace/coverage/default/27.hmac_datapath_stress.71970116177773384610431700863606417492116378185751205948296567933812229976042
Short name T3
Test name
Test status
Simulation time 4863401336 ps
CPU time 142.6 seconds
Started Nov 22 01:10:20 PM PST 23
Finished Nov 22 01:12:46 PM PST 23
Peak memory 198604 kb
Host smart-f72fa962-8f33-4793-8772-01f423dcc78a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=71970116177773384610431700863606417492116378185751205948296567933812229976042 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 27.hmac_datapath_stress.71970116177773384610431700863606417492116378185751205948296567933812229976042
Directory /workspace/27.hmac_datapath_stress/latest

Test location /workspace/coverage/default/27.hmac_error.34306631004050632655375220487412910388107880200514578451235227983868661226107
Short name T695
Test name
Test status
Simulation time 26556692074 ps
CPU time 188.27 seconds
Started Nov 22 01:10:18 PM PST 23
Finished Nov 22 01:13:29 PM PST 23
Peak memory 198504 kb
Host smart-26675bd5-a86d-4b84-a94d-f5e55affb731
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34306631004050632655375220487412910388107880200514578451235227983868661226107 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 27.hmac_error.34306631004050632655375220487412910388107880200514578451235227983868661226107
Directory /workspace/27.hmac_error/latest

Test location /workspace/coverage/default/27.hmac_long_msg.9868330276044161010297016973899098739213938957792370694433439561079173446118
Short name T319
Test name
Test status
Simulation time 14959266997 ps
CPU time 114.6 seconds
Started Nov 22 01:10:20 PM PST 23
Finished Nov 22 01:12:17 PM PST 23
Peak memory 198564 kb
Host smart-e9a4d29c-bf67-4c48-9e19-08592b4a3f79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9868330276044161010297016973899098739213938957792370694433439561079173446118 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 27.hmac_long_msg.9868330276044161010297016973899098739213938957792370694433439561079173446118
Directory /workspace/27.hmac_long_msg/latest

Test location /workspace/coverage/default/27.hmac_smoke.30442340353952712491693206962768166794913485857557586840652854455536669235985
Short name T177
Test name
Test status
Simulation time 631560191 ps
CPU time 4.06 seconds
Started Nov 22 01:10:20 PM PST 23
Finished Nov 22 01:10:27 PM PST 23
Peak memory 198520 kb
Host smart-0f7a6278-098c-4e8d-b837-92941033a216
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30442340353952712491693206962768166794913485857557586840652854455536669235985 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 27.hmac_smoke.30442340353952712491693206962768166794913485857557586840652854455536669235985
Directory /workspace/27.hmac_smoke/latest

Test location /workspace/coverage/default/27.hmac_stress_all.16480254573533513043044051907848050821369188421613200165344479681355008685997
Short name T542
Test name
Test status
Simulation time 146644856361 ps
CPU time 1155.68 seconds
Started Nov 22 01:09:41 PM PST 23
Finished Nov 22 01:28:59 PM PST 23
Peak memory 210800 kb
Host smart-83f3741d-a4e4-459a-9d8e-2a46f8bae27d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164802545735335130430440
51907848050821369188421613200165344479681355008685997 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_stress_all.16480254573533513043044
051907848050821369188421613200165344479681355008685997
Directory /workspace/27.hmac_stress_all/latest

Test location /workspace/coverage/default/27.hmac_stress_all_with_rand_reset.115791902306568742731111055237185825490030720928313036628853602249447401750066
Short name T247
Test name
Test status
Simulation time 80460760838 ps
CPU time 736.56 seconds
Started Nov 22 01:09:51 PM PST 23
Finished Nov 22 01:22:09 PM PST 23
Peak memory 209328 kb
Host smart-24ed46b7-6dfe-4010-b238-357d8b807985
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=115791902306568742731111055237185825490030720928313036628853602249447401750066 -assert nopostproc +UVM_TE
STNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 27.hmac_stress_all_with_rand_reset.115791902306568742731111055237185825490030720928313036628853602249447401750066
Directory /workspace/27.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.hmac_test_hmac_vectors.29371193925313917335599240478278063647085122588959595591938024334363404318974
Short name T588
Test name
Test status
Simulation time 76314633 ps
CPU time 0.95 seconds
Started Nov 22 01:10:21 PM PST 23
Finished Nov 22 01:10:26 PM PST 23
Peak memory 195756 kb
Host smart-52df2b60-6429-402d-8acf-c72256a8491d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29371193925313917335599240478278063647085122588959595
591938024334363404318974 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_test_hmac_vectors.29371193925313917335599240478278063647
085122588959595591938024334363404318974
Directory /workspace/27.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/27.hmac_test_sha_vectors.99118657321008629615155875600250369283848031651594287012638735493086246139334
Short name T660
Test name
Test status
Simulation time 63914107498 ps
CPU time 470.27 seconds
Started Nov 22 01:09:53 PM PST 23
Finished Nov 22 01:17:44 PM PST 23
Peak memory 198504 kb
Host smart-e154096d-64cf-41e8-a05e-f64d3804a607
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99118657321008629615155875600250369283848031651594287
012638735493086246139334 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_test_sha_vectors.9911865732100862961515587560025036928384
8031651594287012638735493086246139334
Directory /workspace/27.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/27.hmac_wipe_secret.70262692067773094231901061458363395024936526072277553085366957199438637747572
Short name T312
Test name
Test status
Simulation time 8070750677 ps
CPU time 61.64 seconds
Started Nov 22 01:09:41 PM PST 23
Finished Nov 22 01:10:45 PM PST 23
Peak memory 198604 kb
Host smart-fb7505ce-2bd7-4bf1-8527-4f1eb9cd29d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70262692067773094231901061458363395024936526072277553085366957199438637747572 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 27.hmac_wipe_secret.70262692067773094231901061458363395024936526072277553085366957199438637747572
Directory /workspace/27.hmac_wipe_secret/latest

Test location /workspace/coverage/default/28.hmac_alert_test.112303742789870239132138304857746760670902462498880114883162241383241828613830
Short name T469
Test name
Test status
Simulation time 18011528 ps
CPU time 0.55 seconds
Started Nov 22 01:10:24 PM PST 23
Finished Nov 22 01:10:28 PM PST 23
Peak memory 192680 kb
Host smart-8f49394f-1323-4cd1-b15a-14322393fb6d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112303742789870239132138304857746760670902462498880114883162241383241828613830 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 28.hmac_alert_test.112303742789870239132138304857746760670902462498880114883162241383241828613830
Directory /workspace/28.hmac_alert_test/latest

Test location /workspace/coverage/default/28.hmac_back_pressure.8891772403134359573438107317689098443173275973024060525015801913850234201298
Short name T373
Test name
Test status
Simulation time 2592169506 ps
CPU time 50.46 seconds
Started Nov 22 01:09:39 PM PST 23
Finished Nov 22 01:10:31 PM PST 23
Peak memory 231368 kb
Host smart-276eb7aa-a1c1-41bf-a36a-dd6c30226ea3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=8891772403134359573438107317689098443173275973024060525015801913850234201298 -assert nopostproc +UVM_TEST
NAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 28.hmac_back_pressure.8891772403134359573438107317689098443173275973024060525015801913850234201298
Directory /workspace/28.hmac_back_pressure/latest

Test location /workspace/coverage/default/28.hmac_burst_wr.50362062973706331564483166629855076287824744867140927671382190054981240734363
Short name T47
Test name
Test status
Simulation time 4504100639 ps
CPU time 36.48 seconds
Started Nov 22 01:10:01 PM PST 23
Finished Nov 22 01:10:40 PM PST 23
Peak memory 198396 kb
Host smart-7d60773d-4f2f-47a0-ad6a-513ba21ea631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50362062973706331564483166629855076287824744867140927671382190054981240734363 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.hmac_burst_wr.50362062973706331564483166629855076287824744867140927671382190054981240734363
Directory /workspace/28.hmac_burst_wr/latest

Test location /workspace/coverage/default/28.hmac_datapath_stress.34085144290103465225949585027112579840077848480277118194191900656678405373985
Short name T699
Test name
Test status
Simulation time 4863401336 ps
CPU time 148.3 seconds
Started Nov 22 01:09:44 PM PST 23
Finished Nov 22 01:12:15 PM PST 23
Peak memory 198440 kb
Host smart-f53b1d13-0e8f-45af-89a2-e9cfe103eab5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=34085144290103465225949585027112579840077848480277118194191900656678405373985 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 28.hmac_datapath_stress.34085144290103465225949585027112579840077848480277118194191900656678405373985
Directory /workspace/28.hmac_datapath_stress/latest

Test location /workspace/coverage/default/28.hmac_error.25491709158202520754165683718116333194442150278988030996977659732492004641621
Short name T361
Test name
Test status
Simulation time 26556692074 ps
CPU time 190.82 seconds
Started Nov 22 01:10:04 PM PST 23
Finished Nov 22 01:13:20 PM PST 23
Peak memory 198588 kb
Host smart-fd267381-0086-4735-9e4b-cfec30f26e92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25491709158202520754165683718116333194442150278988030996977659732492004641621 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 28.hmac_error.25491709158202520754165683718116333194442150278988030996977659732492004641621
Directory /workspace/28.hmac_error/latest

Test location /workspace/coverage/default/28.hmac_long_msg.79418964630603359443991603710811176956361026025377341656003078332241909107202
Short name T406
Test name
Test status
Simulation time 14959266997 ps
CPU time 120.14 seconds
Started Nov 22 01:09:42 PM PST 23
Finished Nov 22 01:11:44 PM PST 23
Peak memory 198552 kb
Host smart-99ad5f7e-1489-4c11-9080-e3e5b2f61d16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79418964630603359443991603710811176956361026025377341656003078332241909107202 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.hmac_long_msg.79418964630603359443991603710811176956361026025377341656003078332241909107202
Directory /workspace/28.hmac_long_msg/latest

Test location /workspace/coverage/default/28.hmac_smoke.59114569896105414662867238910338325158592464673184948771580498680752895713284
Short name T214
Test name
Test status
Simulation time 631560191 ps
CPU time 4 seconds
Started Nov 22 01:09:44 PM PST 23
Finished Nov 22 01:09:51 PM PST 23
Peak memory 198420 kb
Host smart-137188f6-82dc-4140-b568-848244135e78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59114569896105414662867238910338325158592464673184948771580498680752895713284 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 28.hmac_smoke.59114569896105414662867238910338325158592464673184948771580498680752895713284
Directory /workspace/28.hmac_smoke/latest

Test location /workspace/coverage/default/28.hmac_stress_all.35564246174382163348735840354633986766633501941593440411501525598719054721932
Short name T368
Test name
Test status
Simulation time 146644856361 ps
CPU time 1130.83 seconds
Started Nov 22 01:10:02 PM PST 23
Finished Nov 22 01:28:57 PM PST 23
Peak memory 210888 kb
Host smart-a8d97ef4-3fad-4b37-b87e-0bf6e8c4c0d1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355642461743821633487358
40354633986766633501941593440411501525598719054721932 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_stress_all.35564246174382163348735
840354633986766633501941593440411501525598719054721932
Directory /workspace/28.hmac_stress_all/latest

Test location /workspace/coverage/default/28.hmac_stress_all_with_rand_reset.14891694773824960723288805558413360591691047862667815062929295102318956391165
Short name T317
Test name
Test status
Simulation time 80460760838 ps
CPU time 710.61 seconds
Started Nov 22 01:10:13 PM PST 23
Finished Nov 22 01:22:08 PM PST 23
Peak memory 209332 kb
Host smart-11883bbc-92ce-4276-86fa-9e9580e509fe
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=14891694773824960723288805558413360591691047862667815062929295102318956391165 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 28.hmac_stress_all_with_rand_reset.14891694773824960723288805558413360591691047862667815062929295102318956391165
Directory /workspace/28.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.hmac_test_hmac_vectors.26503530036190472784548092998473695656561259712428708821530646743451064082194
Short name T513
Test name
Test status
Simulation time 76314633 ps
CPU time 0.91 seconds
Started Nov 22 01:09:57 PM PST 23
Finished Nov 22 01:10:00 PM PST 23
Peak memory 195784 kb
Host smart-4dc9dd59-a20a-4af4-a087-a0daba731d01
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26503530036190472784548092998473695656561259712428708
821530646743451064082194 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_test_hmac_vectors.26503530036190472784548092998473695656
561259712428708821530646743451064082194
Directory /workspace/28.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/28.hmac_test_sha_vectors.38363346012977679528561842438843874259956306687173456997382740709663851019482
Short name T316
Test name
Test status
Simulation time 63914107498 ps
CPU time 444.77 seconds
Started Nov 22 01:09:58 PM PST 23
Finished Nov 22 01:17:24 PM PST 23
Peak memory 198568 kb
Host smart-8da2760b-7e9c-4d6d-9e62-739413a3860b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38363346012977679528561842438843874259956306687173456
997382740709663851019482 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_test_sha_vectors.3836334601297767952856184243884387425995
6306687173456997382740709663851019482
Directory /workspace/28.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/28.hmac_wipe_secret.69397602953138332302753643640738883975139338894117589312692469477841581943344
Short name T272
Test name
Test status
Simulation time 8070750677 ps
CPU time 62.17 seconds
Started Nov 22 01:10:11 PM PST 23
Finished Nov 22 01:11:18 PM PST 23
Peak memory 198580 kb
Host smart-0eff01a9-3c44-4a9a-9cc4-29e00cae6053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69397602953138332302753643640738883975139338894117589312692469477841581943344 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 28.hmac_wipe_secret.69397602953138332302753643640738883975139338894117589312692469477841581943344
Directory /workspace/28.hmac_wipe_secret/latest

Test location /workspace/coverage/default/29.hmac_alert_test.16055472085482780520837567406820621347175563949457837103307381443245333172465
Short name T779
Test name
Test status
Simulation time 18011528 ps
CPU time 0.54 seconds
Started Nov 22 01:10:12 PM PST 23
Finished Nov 22 01:10:16 PM PST 23
Peak memory 192888 kb
Host smart-87dc2f40-68ee-41c5-bf69-d27b422b3061
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16055472085482780520837567406820621347175563949457837103307381443245333172465 -assert nopostpr
oc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 29.hmac_alert_test.16055472085482780520837567406820621347175563949457837103307381443245333172465
Directory /workspace/29.hmac_alert_test/latest

Test location /workspace/coverage/default/29.hmac_back_pressure.65022943849293824943145363960641007666272548221242541253291146947849584223824
Short name T766
Test name
Test status
Simulation time 2592169506 ps
CPU time 48.27 seconds
Started Nov 22 01:10:09 PM PST 23
Finished Nov 22 01:11:02 PM PST 23
Peak memory 231292 kb
Host smart-e011b558-b10f-4b87-beee-e18590f358bb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=65022943849293824943145363960641007666272548221242541253291146947849584223824 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 29.hmac_back_pressure.65022943849293824943145363960641007666272548221242541253291146947849584223824
Directory /workspace/29.hmac_back_pressure/latest

Test location /workspace/coverage/default/29.hmac_burst_wr.32282349680733555790527120421390327414898933811410561824403652623626434722836
Short name T66
Test name
Test status
Simulation time 4504100639 ps
CPU time 38.28 seconds
Started Nov 22 01:10:12 PM PST 23
Finished Nov 22 01:10:55 PM PST 23
Peak memory 198600 kb
Host smart-82a9d55e-7c3f-4504-be10-765fdc211481
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32282349680733555790527120421390327414898933811410561824403652623626434722836 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.hmac_burst_wr.32282349680733555790527120421390327414898933811410561824403652623626434722836
Directory /workspace/29.hmac_burst_wr/latest

Test location /workspace/coverage/default/29.hmac_datapath_stress.13693979880261802821550058842408311523715121638124473782896669406650956536920
Short name T839
Test name
Test status
Simulation time 4863401336 ps
CPU time 143.93 seconds
Started Nov 22 01:10:13 PM PST 23
Finished Nov 22 01:12:41 PM PST 23
Peak memory 198576 kb
Host smart-2893f625-05cd-4d8d-81a1-33361b06105e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=13693979880261802821550058842408311523715121638124473782896669406650956536920 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 29.hmac_datapath_stress.13693979880261802821550058842408311523715121638124473782896669406650956536920
Directory /workspace/29.hmac_datapath_stress/latest

Test location /workspace/coverage/default/29.hmac_error.34985088910700734563763727271180220772607170725089010447226570371617603688108
Short name T268
Test name
Test status
Simulation time 26556692074 ps
CPU time 189.61 seconds
Started Nov 22 01:10:01 PM PST 23
Finished Nov 22 01:13:13 PM PST 23
Peak memory 198616 kb
Host smart-d96bd7d1-e230-4cbf-8868-623f468c2501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34985088910700734563763727271180220772607170725089010447226570371617603688108 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 29.hmac_error.34985088910700734563763727271180220772607170725089010447226570371617603688108
Directory /workspace/29.hmac_error/latest

Test location /workspace/coverage/default/29.hmac_long_msg.86521151534584717957634248584244793451558730335606036018076977470076512056507
Short name T748
Test name
Test status
Simulation time 14959266997 ps
CPU time 118.42 seconds
Started Nov 22 01:10:10 PM PST 23
Finished Nov 22 01:12:13 PM PST 23
Peak memory 198520 kb
Host smart-5da46a87-db41-4904-8afb-df30d4efaec9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86521151534584717957634248584244793451558730335606036018076977470076512056507 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.hmac_long_msg.86521151534584717957634248584244793451558730335606036018076977470076512056507
Directory /workspace/29.hmac_long_msg/latest

Test location /workspace/coverage/default/29.hmac_smoke.26949809807466675461433801238200983894085813545081379888548208689382652208803
Short name T207
Test name
Test status
Simulation time 631560191 ps
CPU time 3.99 seconds
Started Nov 22 01:10:03 PM PST 23
Finished Nov 22 01:10:11 PM PST 23
Peak memory 198516 kb
Host smart-f8d136c9-721e-4da7-a593-61b7f8c89776
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26949809807466675461433801238200983894085813545081379888548208689382652208803 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 29.hmac_smoke.26949809807466675461433801238200983894085813545081379888548208689382652208803
Directory /workspace/29.hmac_smoke/latest

Test location /workspace/coverage/default/29.hmac_stress_all.89695898827523142578259056685757361817062507522227197622257342666010541354541
Short name T464
Test name
Test status
Simulation time 146644856361 ps
CPU time 1118.43 seconds
Started Nov 22 01:10:17 PM PST 23
Finished Nov 22 01:28:59 PM PST 23
Peak memory 210884 kb
Host smart-547c3ba9-1278-4d0c-8a88-7c7cae193328
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896958988275231425782590
56685757361817062507522227197622257342666010541354541 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_stress_all.89695898827523142578259
056685757361817062507522227197622257342666010541354541
Directory /workspace/29.hmac_stress_all/latest

Test location /workspace/coverage/default/29.hmac_stress_all_with_rand_reset.60829713480199638823033517515402248711267484795538610594575582991200001098474
Short name T331
Test name
Test status
Simulation time 80460760838 ps
CPU time 681.92 seconds
Started Nov 22 01:10:13 PM PST 23
Finished Nov 22 01:21:39 PM PST 23
Peak memory 209364 kb
Host smart-ecd1d360-e5bc-4629-bfa5-b8bb5d49400b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=60829713480199638823033517515402248711267484795538610594575582991200001098474 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 29.hmac_stress_all_with_rand_reset.60829713480199638823033517515402248711267484795538610594575582991200001098474
Directory /workspace/29.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.hmac_test_hmac_vectors.67506614704926521939315676808637448318316488446414934129561604726758555332356
Short name T820
Test name
Test status
Simulation time 76314633 ps
CPU time 0.91 seconds
Started Nov 22 01:10:14 PM PST 23
Finished Nov 22 01:10:19 PM PST 23
Peak memory 195576 kb
Host smart-364bb5ba-8926-496b-ba95-35922eb80aa6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67506614704926521939315676808637448318316488446414934
129561604726758555332356 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_test_hmac_vectors.67506614704926521939315676808637448318
316488446414934129561604726758555332356
Directory /workspace/29.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/29.hmac_test_sha_vectors.58754969073102928130662163496900683042583386615641589676597221653164996716674
Short name T370
Test name
Test status
Simulation time 63914107498 ps
CPU time 474.61 seconds
Started Nov 22 01:10:02 PM PST 23
Finished Nov 22 01:18:00 PM PST 23
Peak memory 198572 kb
Host smart-2d9284c8-8758-40be-aa4f-2ff23b8d112c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58754969073102928130662163496900683042583386615641589
676597221653164996716674 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_test_sha_vectors.5875496907310292813066216349690068304258
3386615641589676597221653164996716674
Directory /workspace/29.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/29.hmac_wipe_secret.69402788928122187507057648611293495797382257250859313563162985621002327681475
Short name T763
Test name
Test status
Simulation time 8070750677 ps
CPU time 63.31 seconds
Started Nov 22 01:10:24 PM PST 23
Finished Nov 22 01:11:31 PM PST 23
Peak memory 198416 kb
Host smart-80a3bb8f-075f-46cf-a2c1-a69f694aab6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69402788928122187507057648611293495797382257250859313563162985621002327681475 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 29.hmac_wipe_secret.69402788928122187507057648611293495797382257250859313563162985621002327681475
Directory /workspace/29.hmac_wipe_secret/latest

Test location /workspace/coverage/default/3.hmac_alert_test.33351284504102726559543569686360893141067467499213369493195721425736719421481
Short name T803
Test name
Test status
Simulation time 18011528 ps
CPU time 0.55 seconds
Started Nov 22 01:09:00 PM PST 23
Finished Nov 22 01:09:09 PM PST 23
Peak memory 192760 kb
Host smart-6fb9116e-3d23-4ebe-b56c-6dbaa0e109f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33351284504102726559543569686360893141067467499213369493195721425736719421481 -assert nopostpr
oc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 3.hmac_alert_test.33351284504102726559543569686360893141067467499213369493195721425736719421481
Directory /workspace/3.hmac_alert_test/latest

Test location /workspace/coverage/default/3.hmac_back_pressure.66099516442961804155506921206299502743440311103502786242160818868793699855963
Short name T644
Test name
Test status
Simulation time 2592169506 ps
CPU time 47.87 seconds
Started Nov 22 01:08:55 PM PST 23
Finished Nov 22 01:09:48 PM PST 23
Peak memory 231240 kb
Host smart-bd218ea2-ca86-42e3-8a40-73fbacd3af60
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=66099516442961804155506921206299502743440311103502786242160818868793699855963 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 3.hmac_back_pressure.66099516442961804155506921206299502743440311103502786242160818868793699855963
Directory /workspace/3.hmac_back_pressure/latest

Test location /workspace/coverage/default/3.hmac_burst_wr.103324663706212559969683652881989733259005689787357447224062280253890793195541
Short name T604
Test name
Test status
Simulation time 4504100639 ps
CPU time 38.22 seconds
Started Nov 22 01:08:58 PM PST 23
Finished Nov 22 01:09:46 PM PST 23
Peak memory 198412 kb
Host smart-30550aac-edd1-4630-b640-70394e4d3284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103324663706212559969683652881989733259005689787357447224062280253890793195541 -assert nopostproc +UVM_TESTNAME=hmac_bas
e_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 3.hmac_burst_wr.103324663706212559969683652881989733259005689787357447224062280253890793195541
Directory /workspace/3.hmac_burst_wr/latest

Test location /workspace/coverage/default/3.hmac_datapath_stress.15896443184865955237981485672677851789655751918049767339120263350493490850264
Short name T698
Test name
Test status
Simulation time 4863401336 ps
CPU time 140 seconds
Started Nov 22 01:08:55 PM PST 23
Finished Nov 22 01:11:20 PM PST 23
Peak memory 198476 kb
Host smart-5d056163-d6a2-4200-8c64-eb44b7dd4462
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=15896443184865955237981485672677851789655751918049767339120263350493490850264 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 3.hmac_datapath_stress.15896443184865955237981485672677851789655751918049767339120263350493490850264
Directory /workspace/3.hmac_datapath_stress/latest

Test location /workspace/coverage/default/3.hmac_error.107773590922546862486130155713622224844387058863409297699873766792777339233292
Short name T394
Test name
Test status
Simulation time 26556692074 ps
CPU time 183.83 seconds
Started Nov 22 01:08:55 PM PST 23
Finished Nov 22 01:12:03 PM PST 23
Peak memory 198440 kb
Host smart-3af2116d-9896-410e-ab42-3f7d179452e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107773590922546862486130155713622224844387058863409297699873766792777339233292 -assert nopostproc +UVM_TESTNAME=hmac_bas
e_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 3.hmac_error.107773590922546862486130155713622224844387058863409297699873766792777339233292
Directory /workspace/3.hmac_error/latest

Test location /workspace/coverage/default/3.hmac_long_msg.28303255594926733321300647709960413036607652051521075755260785934222475306995
Short name T706
Test name
Test status
Simulation time 14959266997 ps
CPU time 113.41 seconds
Started Nov 22 01:08:55 PM PST 23
Finished Nov 22 01:10:53 PM PST 23
Peak memory 198452 kb
Host smart-e48c592a-ea2d-4046-84cb-2ce4e6958b83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28303255594926733321300647709960413036607652051521075755260785934222475306995 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.hmac_long_msg.28303255594926733321300647709960413036607652051521075755260785934222475306995
Directory /workspace/3.hmac_long_msg/latest

Test location /workspace/coverage/default/3.hmac_sec_cm.62315133013416139388930904907273635085697055451526354054309020477929619631968
Short name T60
Test name
Test status
Simulation time 100939436 ps
CPU time 0.86 seconds
Started Nov 22 01:09:00 PM PST 23
Finished Nov 22 01:09:10 PM PST 23
Peak memory 215824 kb
Host smart-4f53f823-d23b-4ca1-9673-bfd0491f2436
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62315133013416139388930904907273635085697055451526354054309020477929619631968 -assert nopostpro
c +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 3.hmac_sec_cm.62315133013416139388930904907273635085697055451526354054309020477929619631968
Directory /workspace/3.hmac_sec_cm/latest

Test location /workspace/coverage/default/3.hmac_smoke.32727806216791692550195431840435389060751896563500154954942462127748336565373
Short name T647
Test name
Test status
Simulation time 631560191 ps
CPU time 4.11 seconds
Started Nov 22 01:08:55 PM PST 23
Finished Nov 22 01:09:04 PM PST 23
Peak memory 198384 kb
Host smart-7cc278a1-808c-4a62-b0ed-f58a6ca50d56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32727806216791692550195431840435389060751896563500154954942462127748336565373 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 3.hmac_smoke.32727806216791692550195431840435389060751896563500154954942462127748336565373
Directory /workspace/3.hmac_smoke/latest

Test location /workspace/coverage/default/3.hmac_stress_all.42132382536840739463944490222732170840855102806184029355428035274587455507936
Short name T781
Test name
Test status
Simulation time 146644856361 ps
CPU time 1112.09 seconds
Started Nov 22 01:08:54 PM PST 23
Finished Nov 22 01:27:31 PM PST 23
Peak memory 210640 kb
Host smart-016e6b7b-a92f-42c7-b7c6-a7dd135e3f14
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421323825368407394639444
90222732170840855102806184029355428035274587455507936 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all.421323825368407394639444
90222732170840855102806184029355428035274587455507936
Directory /workspace/3.hmac_stress_all/latest

Test location /workspace/coverage/default/3.hmac_stress_all_with_rand_reset.34638604594341067972923803899756958250773318075102469608398455490311390321089
Short name T743
Test name
Test status
Simulation time 80460760838 ps
CPU time 718.35 seconds
Started Nov 22 01:09:02 PM PST 23
Finished Nov 22 01:21:10 PM PST 23
Peak memory 210368 kb
Host smart-598881d3-3dda-46e5-b36b-e05b6babf327
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=34638604594341067972923803899756958250773318075102469608398455490311390321089 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 3.hmac_stress_all_with_rand_reset.34638604594341067972923803899756958250773318075102469608398455490311390321089
Directory /workspace/3.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.hmac_test_hmac_vectors.15673475807348628717975077217837947932497559049525017693678265513761565032993
Short name T536
Test name
Test status
Simulation time 76314633 ps
CPU time 0.9 seconds
Started Nov 22 01:08:54 PM PST 23
Finished Nov 22 01:09:00 PM PST 23
Peak memory 195596 kb
Host smart-5293b7c3-2826-47ac-8d68-2b2945a3ab93
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15673475807348628717975077217837947932497559049525017
693678265513761565032993 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac_vectors.156734758073486287179750772178379479324
97559049525017693678265513761565032993
Directory /workspace/3.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha_vectors.29484904238038271099162648718435457691225946316907523562903271427039306086925
Short name T707
Test name
Test status
Simulation time 63914107498 ps
CPU time 447.68 seconds
Started Nov 22 01:08:55 PM PST 23
Finished Nov 22 01:16:27 PM PST 23
Peak memory 198484 kb
Host smart-353022d7-e06e-47d1-9955-0e86436ece7e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29484904238038271099162648718435457691225946316907523
562903271427039306086925 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha_vectors.29484904238038271099162648718435457691225
946316907523562903271427039306086925
Directory /workspace/3.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/3.hmac_wipe_secret.102790510407951262642177168399434150439040202609147720212841463315832470648999
Short name T485
Test name
Test status
Simulation time 8070750677 ps
CPU time 61.21 seconds
Started Nov 22 01:08:38 PM PST 23
Finished Nov 22 01:09:50 PM PST 23
Peak memory 198588 kb
Host smart-cbd44f2a-f905-44f3-ad4e-f4f40ca04292
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102790510407951262642177168399434150439040202609147720212841463315832470648999 -assert nopostproc +UVM_TESTNAME=hmac_bas
e_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 3.hmac_wipe_secret.102790510407951262642177168399434150439040202609147720212841463315832470648999
Directory /workspace/3.hmac_wipe_secret/latest

Test location /workspace/coverage/default/30.hmac_alert_test.33007241300089897980477322966575421123765714640144082616687635871877360653754
Short name T809
Test name
Test status
Simulation time 18011528 ps
CPU time 0.56 seconds
Started Nov 22 01:10:02 PM PST 23
Finished Nov 22 01:10:06 PM PST 23
Peak memory 192880 kb
Host smart-44344d7c-9cb4-4c18-8460-8f00e80acb03
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33007241300089897980477322966575421123765714640144082616687635871877360653754 -assert nopostpr
oc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 30.hmac_alert_test.33007241300089897980477322966575421123765714640144082616687635871877360653754
Directory /workspace/30.hmac_alert_test/latest

Test location /workspace/coverage/default/30.hmac_back_pressure.59068633728318961890768301504227817012506308033971049470183437664078896774353
Short name T527
Test name
Test status
Simulation time 2592169506 ps
CPU time 47.22 seconds
Started Nov 22 01:10:11 PM PST 23
Finished Nov 22 01:11:03 PM PST 23
Peak memory 231376 kb
Host smart-29a9546d-745d-4bac-98ef-714f3ff0d6de
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=59068633728318961890768301504227817012506308033971049470183437664078896774353 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 30.hmac_back_pressure.59068633728318961890768301504227817012506308033971049470183437664078896774353
Directory /workspace/30.hmac_back_pressure/latest

Test location /workspace/coverage/default/30.hmac_burst_wr.79385687258655914285880448393838051031778178127428769829418936420068346399339
Short name T262
Test name
Test status
Simulation time 4504100639 ps
CPU time 36.39 seconds
Started Nov 22 01:10:46 PM PST 23
Finished Nov 22 01:11:24 PM PST 23
Peak memory 196300 kb
Host smart-b74e462c-2154-4bf6-8a06-9638570e0015
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79385687258655914285880448393838051031778178127428769829418936420068346399339 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 30.hmac_burst_wr.79385687258655914285880448393838051031778178127428769829418936420068346399339
Directory /workspace/30.hmac_burst_wr/latest

Test location /workspace/coverage/default/30.hmac_datapath_stress.104999306025353194265724200969029494018421277917512546780426663793927855818392
Short name T671
Test name
Test status
Simulation time 4863401336 ps
CPU time 139.45 seconds
Started Nov 22 01:10:11 PM PST 23
Finished Nov 22 01:12:35 PM PST 23
Peak memory 198588 kb
Host smart-3a564409-a970-4e7c-bf1a-5347154ac928
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=104999306025353194265724200969029494018421277917512546780426663793927855818392 -assert nopostproc +UVM_TE
STNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 30.hmac_datapath_stress.104999306025353194265724200969029494018421277917512546780426663793927855818392
Directory /workspace/30.hmac_datapath_stress/latest

Test location /workspace/coverage/default/30.hmac_error.60253627976806676684325091035695484665334989462433373888087474340154698211666
Short name T772
Test name
Test status
Simulation time 26556692074 ps
CPU time 179.59 seconds
Started Nov 22 01:10:19 PM PST 23
Finished Nov 22 01:13:21 PM PST 23
Peak memory 198460 kb
Host smart-d071223a-6299-4032-b585-00b615ad25fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60253627976806676684325091035695484665334989462433373888087474340154698211666 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 30.hmac_error.60253627976806676684325091035695484665334989462433373888087474340154698211666
Directory /workspace/30.hmac_error/latest

Test location /workspace/coverage/default/30.hmac_long_msg.2943667102679660103992900415701625213737262644982909826787419059514343127238
Short name T212
Test name
Test status
Simulation time 14959266997 ps
CPU time 114.66 seconds
Started Nov 22 01:10:19 PM PST 23
Finished Nov 22 01:12:16 PM PST 23
Peak memory 198404 kb
Host smart-f398db2a-31bf-41a0-862e-d3a221c276bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2943667102679660103992900415701625213737262644982909826787419059514343127238 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 30.hmac_long_msg.2943667102679660103992900415701625213737262644982909826787419059514343127238
Directory /workspace/30.hmac_long_msg/latest

Test location /workspace/coverage/default/30.hmac_smoke.51541592294588593030605458893620636614340725576568090073960778543555155158084
Short name T226
Test name
Test status
Simulation time 631560191 ps
CPU time 4.07 seconds
Started Nov 22 01:10:10 PM PST 23
Finished Nov 22 01:10:19 PM PST 23
Peak memory 198520 kb
Host smart-d93963cc-e52e-4f36-8dc2-a899ffb74903
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51541592294588593030605458893620636614340725576568090073960778543555155158084 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 30.hmac_smoke.51541592294588593030605458893620636614340725576568090073960778543555155158084
Directory /workspace/30.hmac_smoke/latest

Test location /workspace/coverage/default/30.hmac_stress_all.89086052744543597090868639121736678156408849513846235799130310413091262347621
Short name T352
Test name
Test status
Simulation time 146644856361 ps
CPU time 1104.38 seconds
Started Nov 22 01:09:53 PM PST 23
Finished Nov 22 01:28:18 PM PST 23
Peak memory 210888 kb
Host smart-115c81ec-0626-4859-a941-8b4ced5ede65
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890860527445435970908686
39121736678156408849513846235799130310413091262347621 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_stress_all.89086052744543597090868
639121736678156408849513846235799130310413091262347621
Directory /workspace/30.hmac_stress_all/latest

Test location /workspace/coverage/default/30.hmac_stress_all_with_rand_reset.27173695187197591064884827173448593602922347094577977307770371748086364983542
Short name T243
Test name
Test status
Simulation time 80460760838 ps
CPU time 697.22 seconds
Started Nov 22 01:10:05 PM PST 23
Finished Nov 22 01:21:47 PM PST 23
Peak memory 209328 kb
Host smart-230096b7-b7c0-4db2-b9e9-36136bc613ba
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=27173695187197591064884827173448593602922347094577977307770371748086364983542 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 30.hmac_stress_all_with_rand_reset.27173695187197591064884827173448593602922347094577977307770371748086364983542
Directory /workspace/30.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.hmac_test_hmac_vectors.111009019029683577809494822728994955199139293292885115702924496766369137999
Short name T217
Test name
Test status
Simulation time 76314633 ps
CPU time 0.99 seconds
Started Nov 22 01:10:46 PM PST 23
Finished Nov 22 01:10:48 PM PST 23
Peak memory 193520 kb
Host smart-112ef665-eda3-4f71-bb5b-0b180586da21
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11100901902968357780949482272899495519913929329288511
5702924496766369137999 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_test_hmac_vectors.1110090190296835778094948227289949551991
39293292885115702924496766369137999
Directory /workspace/30.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/30.hmac_test_sha_vectors.47245763383819849965963904351976030964329358019822404374515653149364969560775
Short name T569
Test name
Test status
Simulation time 63914107498 ps
CPU time 455.29 seconds
Started Nov 22 01:10:20 PM PST 23
Finished Nov 22 01:17:59 PM PST 23
Peak memory 198608 kb
Host smart-be6ba688-7ccd-4c69-8be9-9554a85953d4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47245763383819849965963904351976030964329358019822404
374515653149364969560775 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_test_sha_vectors.4724576338381984996596390435197603096432
9358019822404374515653149364969560775
Directory /workspace/30.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/30.hmac_wipe_secret.104601029734221718947754751317132552932127201487000707495280763258863590336153
Short name T459
Test name
Test status
Simulation time 8070750677 ps
CPU time 61.85 seconds
Started Nov 22 01:10:20 PM PST 23
Finished Nov 22 01:11:25 PM PST 23
Peak memory 198568 kb
Host smart-5cc21372-5327-41bf-b054-060945921792
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104601029734221718947754751317132552932127201487000707495280763258863590336153 -assert nopostproc +UVM_TESTNAME=hmac_bas
e_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 30.hmac_wipe_secret.104601029734221718947754751317132552932127201487000707495280763258863590336153
Directory /workspace/30.hmac_wipe_secret/latest

Test location /workspace/coverage/default/31.hmac_alert_test.69272773452459738588308383211577925578495087149886751000077668146115679515165
Short name T1
Test name
Test status
Simulation time 18011528 ps
CPU time 0.53 seconds
Started Nov 22 01:09:56 PM PST 23
Finished Nov 22 01:09:57 PM PST 23
Peak memory 192884 kb
Host smart-42583227-4a7c-443a-b25c-395cb833f8fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69272773452459738588308383211577925578495087149886751000077668146115679515165 -assert nopostpr
oc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 31.hmac_alert_test.69272773452459738588308383211577925578495087149886751000077668146115679515165
Directory /workspace/31.hmac_alert_test/latest

Test location /workspace/coverage/default/31.hmac_back_pressure.100991281630460911871469144235495388102884769438943081452359022665891234066502
Short name T586
Test name
Test status
Simulation time 2592169506 ps
CPU time 46.85 seconds
Started Nov 22 01:10:04 PM PST 23
Finished Nov 22 01:10:56 PM PST 23
Peak memory 231312 kb
Host smart-afe072ec-8d68-4070-9d26-20e0def6090f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=100991281630460911871469144235495388102884769438943081452359022665891234066502 -assert nopostproc +UVM_TE
STNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 31.hmac_back_pressure.100991281630460911871469144235495388102884769438943081452359022665891234066502
Directory /workspace/31.hmac_back_pressure/latest

Test location /workspace/coverage/default/31.hmac_burst_wr.111544253726754334845218119169963474876529355078998383870384532271528835179194
Short name T715
Test name
Test status
Simulation time 4504100639 ps
CPU time 37.79 seconds
Started Nov 22 01:09:58 PM PST 23
Finished Nov 22 01:10:37 PM PST 23
Peak memory 198576 kb
Host smart-5d5a8d73-8539-4bdd-a063-1bdf4baee71b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111544253726754334845218119169963474876529355078998383870384532271528835179194 -assert nopostproc +UVM_TESTNAME=hmac_bas
e_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 31.hmac_burst_wr.111544253726754334845218119169963474876529355078998383870384532271528835179194
Directory /workspace/31.hmac_burst_wr/latest

Test location /workspace/coverage/default/31.hmac_datapath_stress.13008963623838327158895641702726781805725406048240612818357945474205410653896
Short name T416
Test name
Test status
Simulation time 4863401336 ps
CPU time 144.49 seconds
Started Nov 22 01:10:00 PM PST 23
Finished Nov 22 01:12:27 PM PST 23
Peak memory 198488 kb
Host smart-701dfa25-6d34-4f9f-8bdc-56c14b24f4cc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=13008963623838327158895641702726781805725406048240612818357945474205410653896 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 31.hmac_datapath_stress.13008963623838327158895641702726781805725406048240612818357945474205410653896
Directory /workspace/31.hmac_datapath_stress/latest

Test location /workspace/coverage/default/31.hmac_error.53415171067551619676155509982544540372822606186055044929284117076005087515904
Short name T230
Test name
Test status
Simulation time 26556692074 ps
CPU time 194.37 seconds
Started Nov 22 01:09:59 PM PST 23
Finished Nov 22 01:13:15 PM PST 23
Peak memory 198604 kb
Host smart-6f3c31b9-c4b3-4570-83a6-3b89dd3ae719
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53415171067551619676155509982544540372822606186055044929284117076005087515904 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 31.hmac_error.53415171067551619676155509982544540372822606186055044929284117076005087515904
Directory /workspace/31.hmac_error/latest

Test location /workspace/coverage/default/31.hmac_long_msg.79587805388924867606398710479747499539771601323515731072754530832518726147659
Short name T97
Test name
Test status
Simulation time 14959266997 ps
CPU time 113.74 seconds
Started Nov 22 01:09:57 PM PST 23
Finished Nov 22 01:11:52 PM PST 23
Peak memory 198572 kb
Host smart-77832cfe-db29-4b34-a821-b464bdf7bcfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79587805388924867606398710479747499539771601323515731072754530832518726147659 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.hmac_long_msg.79587805388924867606398710479747499539771601323515731072754530832518726147659
Directory /workspace/31.hmac_long_msg/latest

Test location /workspace/coverage/default/31.hmac_smoke.100113441109875718075041914658820803100606567938920730311343635445395108775333
Short name T649
Test name
Test status
Simulation time 631560191 ps
CPU time 4.05 seconds
Started Nov 22 01:09:59 PM PST 23
Finished Nov 22 01:10:04 PM PST 23
Peak memory 198540 kb
Host smart-a572e178-ff14-4d7a-a650-d1820d2ea898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100113441109875718075041914658820803100606567938920730311343635445395108775333 -assert nopostproc +UVM_TESTNAME=hmac_bas
e_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 31.hmac_smoke.100113441109875718075041914658820803100606567938920730311343635445395108775333
Directory /workspace/31.hmac_smoke/latest

Test location /workspace/coverage/default/31.hmac_stress_all.6704271798862218803848612095161618656923399950654533037337195637628299910826
Short name T245
Test name
Test status
Simulation time 146644856361 ps
CPU time 1147.72 seconds
Started Nov 22 01:10:13 PM PST 23
Finished Nov 22 01:29:25 PM PST 23
Peak memory 210832 kb
Host smart-7a94a2cd-1abe-483d-9ca1-e73a5b03a584
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670427179886221880384861
2095161618656923399950654533037337195637628299910826 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_stress_all.670427179886221880384861
2095161618656923399950654533037337195637628299910826
Directory /workspace/31.hmac_stress_all/latest

Test location /workspace/coverage/default/31.hmac_stress_all_with_rand_reset.64537007547655539096035259478488571486725517051014101533863354361506619592936
Short name T366
Test name
Test status
Simulation time 80460760838 ps
CPU time 725.78 seconds
Started Nov 22 01:09:52 PM PST 23
Finished Nov 22 01:21:59 PM PST 23
Peak memory 209340 kb
Host smart-2463a950-ae58-4134-bb9e-7e61aa79bd19
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=64537007547655539096035259478488571486725517051014101533863354361506619592936 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 31.hmac_stress_all_with_rand_reset.64537007547655539096035259478488571486725517051014101533863354361506619592936
Directory /workspace/31.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.hmac_test_hmac_vectors.106483045720649744433379297012694954121924344752985535452748393808581916745830
Short name T224
Test name
Test status
Simulation time 76314633 ps
CPU time 0.89 seconds
Started Nov 22 01:09:59 PM PST 23
Finished Nov 22 01:10:02 PM PST 23
Peak memory 195776 kb
Host smart-5e9a6b2c-f7ca-4825-b289-3ad43764dd20
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10648304572064974443337929701269495412192434475298553
5452748393808581916745830 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_test_hmac_vectors.1064830457206497444333792970126949541
21924344752985535452748393808581916745830
Directory /workspace/31.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/31.hmac_test_sha_vectors.67920793370724906737809036390642260736053301355049050949146495758037129896072
Short name T412
Test name
Test status
Simulation time 63914107498 ps
CPU time 458.9 seconds
Started Nov 22 01:09:57 PM PST 23
Finished Nov 22 01:17:38 PM PST 23
Peak memory 198588 kb
Host smart-787109b3-e3af-4e16-bfc4-54f0adb1fe1e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67920793370724906737809036390642260736053301355049050
949146495758037129896072 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_test_sha_vectors.6792079337072490673780903639064226073605
3301355049050949146495758037129896072
Directory /workspace/31.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/31.hmac_wipe_secret.45781297382279374089785782650620108699307039284795632021991341659142434312360
Short name T426
Test name
Test status
Simulation time 8070750677 ps
CPU time 61.78 seconds
Started Nov 22 01:09:58 PM PST 23
Finished Nov 22 01:11:01 PM PST 23
Peak memory 198596 kb
Host smart-4c72319e-54f3-42ac-8ad1-93da1ff70344
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45781297382279374089785782650620108699307039284795632021991341659142434312360 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 31.hmac_wipe_secret.45781297382279374089785782650620108699307039284795632021991341659142434312360
Directory /workspace/31.hmac_wipe_secret/latest

Test location /workspace/coverage/default/32.hmac_alert_test.64369063152091724729343704096538598128703217048349414996513889579434984444784
Short name T583
Test name
Test status
Simulation time 18011528 ps
CPU time 0.55 seconds
Started Nov 22 01:10:11 PM PST 23
Finished Nov 22 01:10:16 PM PST 23
Peak memory 192864 kb
Host smart-dd5c17de-dd33-41b3-9e57-c377c4e6e5b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64369063152091724729343704096538598128703217048349414996513889579434984444784 -assert nopostpr
oc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 32.hmac_alert_test.64369063152091724729343704096538598128703217048349414996513889579434984444784
Directory /workspace/32.hmac_alert_test/latest

Test location /workspace/coverage/default/32.hmac_back_pressure.114280864635178667021299511190840907917649876255846092919762418026966864731257
Short name T41
Test name
Test status
Simulation time 2592169506 ps
CPU time 48.23 seconds
Started Nov 22 01:10:04 PM PST 23
Finished Nov 22 01:10:57 PM PST 23
Peak memory 231368 kb
Host smart-87a4d22b-d1c9-41c8-8b37-7c8d37ee4c42
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=114280864635178667021299511190840907917649876255846092919762418026966864731257 -assert nopostproc +UVM_TE
STNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 32.hmac_back_pressure.114280864635178667021299511190840907917649876255846092919762418026966864731257
Directory /workspace/32.hmac_back_pressure/latest

Test location /workspace/coverage/default/32.hmac_burst_wr.43246362433928268498023853428923435973079613062788459414214404055080497347555
Short name T466
Test name
Test status
Simulation time 4504100639 ps
CPU time 38.06 seconds
Started Nov 22 01:10:03 PM PST 23
Finished Nov 22 01:10:45 PM PST 23
Peak memory 198552 kb
Host smart-85135486-d04c-43ad-b0bd-7c9b9ec98d45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43246362433928268498023853428923435973079613062788459414214404055080497347555 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.hmac_burst_wr.43246362433928268498023853428923435973079613062788459414214404055080497347555
Directory /workspace/32.hmac_burst_wr/latest

Test location /workspace/coverage/default/32.hmac_datapath_stress.29413617955088163679260806965771554264888169270633827165222464168308791151793
Short name T2
Test name
Test status
Simulation time 4863401336 ps
CPU time 140.86 seconds
Started Nov 22 01:09:57 PM PST 23
Finished Nov 22 01:12:19 PM PST 23
Peak memory 198592 kb
Host smart-b4794ca1-aaab-41a7-8e42-100544617911
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=29413617955088163679260806965771554264888169270633827165222464168308791151793 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 32.hmac_datapath_stress.29413617955088163679260806965771554264888169270633827165222464168308791151793
Directory /workspace/32.hmac_datapath_stress/latest

Test location /workspace/coverage/default/32.hmac_error.105384469685889978149138559297151262172330691518854957743091176258138483440623
Short name T831
Test name
Test status
Simulation time 26556692074 ps
CPU time 192.77 seconds
Started Nov 22 01:10:04 PM PST 23
Finished Nov 22 01:13:22 PM PST 23
Peak memory 198588 kb
Host smart-9501dd35-3a57-4f8a-972e-34daaaeee495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105384469685889978149138559297151262172330691518854957743091176258138483440623 -assert nopostproc +UVM_TESTNAME=hmac_bas
e_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 32.hmac_error.105384469685889978149138559297151262172330691518854957743091176258138483440623
Directory /workspace/32.hmac_error/latest

Test location /workspace/coverage/default/32.hmac_long_msg.76996827977158367829506330345753077849624480597117751800853068001465390467774
Short name T638
Test name
Test status
Simulation time 14959266997 ps
CPU time 120.91 seconds
Started Nov 22 01:10:03 PM PST 23
Finished Nov 22 01:12:08 PM PST 23
Peak memory 198544 kb
Host smart-f2bad048-cc6f-4475-a321-10d7938cfb13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76996827977158367829506330345753077849624480597117751800853068001465390467774 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.hmac_long_msg.76996827977158367829506330345753077849624480597117751800853068001465390467774
Directory /workspace/32.hmac_long_msg/latest

Test location /workspace/coverage/default/32.hmac_smoke.41286268239060291152754344985721723370166935240217321260914924430833614041338
Short name T333
Test name
Test status
Simulation time 631560191 ps
CPU time 4.19 seconds
Started Nov 22 01:10:03 PM PST 23
Finished Nov 22 01:10:12 PM PST 23
Peak memory 198512 kb
Host smart-1ff6848a-a8c4-4944-be7c-1bf8ac5fbd4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41286268239060291152754344985721723370166935240217321260914924430833614041338 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 32.hmac_smoke.41286268239060291152754344985721723370166935240217321260914924430833614041338
Directory /workspace/32.hmac_smoke/latest

Test location /workspace/coverage/default/32.hmac_stress_all.6552381720600886805314599754438723177141942901228688362310703065684940488224
Short name T755
Test name
Test status
Simulation time 146644856361 ps
CPU time 1108.78 seconds
Started Nov 22 01:09:57 PM PST 23
Finished Nov 22 01:28:27 PM PST 23
Peak memory 210868 kb
Host smart-452319ba-05ff-4bb0-ac0a-93b25d9a73ec
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655238172060088680531459
9754438723177141942901228688362310703065684940488224 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_stress_all.655238172060088680531459
9754438723177141942901228688362310703065684940488224
Directory /workspace/32.hmac_stress_all/latest

Test location /workspace/coverage/default/32.hmac_stress_all_with_rand_reset.30407573094351004397643522373270116206105356117999952838061848248589837923728
Short name T815
Test name
Test status
Simulation time 80460760838 ps
CPU time 706.58 seconds
Started Nov 22 01:10:00 PM PST 23
Finished Nov 22 01:21:49 PM PST 23
Peak memory 209272 kb
Host smart-59691434-b8d4-4336-83a7-430c5dbd25ec
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=30407573094351004397643522373270116206105356117999952838061848248589837923728 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 32.hmac_stress_all_with_rand_reset.30407573094351004397643522373270116206105356117999952838061848248589837923728
Directory /workspace/32.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.hmac_test_hmac_vectors.64001556630389448212138555968453947203196457733631262015530687351604652647441
Short name T655
Test name
Test status
Simulation time 76314633 ps
CPU time 0.94 seconds
Started Nov 22 01:10:04 PM PST 23
Finished Nov 22 01:10:10 PM PST 23
Peak memory 195816 kb
Host smart-47b49e78-219e-42b8-ab1d-069917857d1c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64001556630389448212138555968453947203196457733631262
015530687351604652647441 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_test_hmac_vectors.64001556630389448212138555968453947203
196457733631262015530687351604652647441
Directory /workspace/32.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/32.hmac_test_sha_vectors.94657927521428174413216735051643106287666479507775772571734640242490614396955
Short name T185
Test name
Test status
Simulation time 63914107498 ps
CPU time 448.69 seconds
Started Nov 22 01:10:02 PM PST 23
Finished Nov 22 01:17:34 PM PST 23
Peak memory 198500 kb
Host smart-5440597a-e342-45ac-b226-15d65c54b62a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94657927521428174413216735051643106287666479507775772
571734640242490614396955 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_test_sha_vectors.9465792752142817441321673505164310628766
6479507775772571734640242490614396955
Directory /workspace/32.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/32.hmac_wipe_secret.21409581158715824625707439012465171879664818728709111813088010014588522613889
Short name T489
Test name
Test status
Simulation time 8070750677 ps
CPU time 64.88 seconds
Started Nov 22 01:10:07 PM PST 23
Finished Nov 22 01:11:16 PM PST 23
Peak memory 198440 kb
Host smart-5e969983-d108-4bc0-ac46-74f2b8607460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21409581158715824625707439012465171879664818728709111813088010014588522613889 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 32.hmac_wipe_secret.21409581158715824625707439012465171879664818728709111813088010014588522613889
Directory /workspace/32.hmac_wipe_secret/latest

Test location /workspace/coverage/default/33.hmac_alert_test.14191097253875739108657610430408845367309855780535891484661463123229803113256
Short name T429
Test name
Test status
Simulation time 18011528 ps
CPU time 0.59 seconds
Started Nov 22 01:10:18 PM PST 23
Finished Nov 22 01:10:21 PM PST 23
Peak memory 192780 kb
Host smart-651730e0-135e-4243-8a2f-4e1d0d3bf077
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14191097253875739108657610430408845367309855780535891484661463123229803113256 -assert nopostpr
oc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 33.hmac_alert_test.14191097253875739108657610430408845367309855780535891484661463123229803113256
Directory /workspace/33.hmac_alert_test/latest

Test location /workspace/coverage/default/33.hmac_back_pressure.84536719071284212880375552706600059106438697563879978027260230665584666907180
Short name T46
Test name
Test status
Simulation time 2592169506 ps
CPU time 46.48 seconds
Started Nov 22 01:10:13 PM PST 23
Finished Nov 22 01:11:04 PM PST 23
Peak memory 231156 kb
Host smart-c1dfbb14-13ce-424a-a9b6-fa9928d07834
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=84536719071284212880375552706600059106438697563879978027260230665584666907180 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 33.hmac_back_pressure.84536719071284212880375552706600059106438697563879978027260230665584666907180
Directory /workspace/33.hmac_back_pressure/latest

Test location /workspace/coverage/default/33.hmac_burst_wr.103613461750538851152384751699163582741058973387896099351307357585017340944933
Short name T12
Test name
Test status
Simulation time 4504100639 ps
CPU time 37.31 seconds
Started Nov 22 01:10:12 PM PST 23
Finished Nov 22 01:10:53 PM PST 23
Peak memory 198548 kb
Host smart-2308b74c-c973-4e47-a2f1-dfeed74a0a64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103613461750538851152384751699163582741058973387896099351307357585017340944933 -assert nopostproc +UVM_TESTNAME=hmac_bas
e_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 33.hmac_burst_wr.103613461750538851152384751699163582741058973387896099351307357585017340944933
Directory /workspace/33.hmac_burst_wr/latest

Test location /workspace/coverage/default/33.hmac_datapath_stress.79155172003929847050014880490924002778130588289409704712212996685964052845281
Short name T302
Test name
Test status
Simulation time 4863401336 ps
CPU time 143.43 seconds
Started Nov 22 01:10:03 PM PST 23
Finished Nov 22 01:12:32 PM PST 23
Peak memory 198604 kb
Host smart-93289bf9-be20-4329-a0a6-2ae2a7482532
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=79155172003929847050014880490924002778130588289409704712212996685964052845281 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 33.hmac_datapath_stress.79155172003929847050014880490924002778130588289409704712212996685964052845281
Directory /workspace/33.hmac_datapath_stress/latest

Test location /workspace/coverage/default/33.hmac_error.99985035062801273801259772670754580512131621116400633193383244400993652324608
Short name T375
Test name
Test status
Simulation time 26556692074 ps
CPU time 192.95 seconds
Started Nov 22 01:10:00 PM PST 23
Finished Nov 22 01:13:15 PM PST 23
Peak memory 198520 kb
Host smart-89c807d0-0125-42f7-8c79-b44aa3bec4a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99985035062801273801259772670754580512131621116400633193383244400993652324608 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 33.hmac_error.99985035062801273801259772670754580512131621116400633193383244400993652324608
Directory /workspace/33.hmac_error/latest

Test location /workspace/coverage/default/33.hmac_long_msg.37499862829091529528352815289325317819838592637379618241738230370206103521114
Short name T837
Test name
Test status
Simulation time 14959266997 ps
CPU time 114.41 seconds
Started Nov 22 01:10:13 PM PST 23
Finished Nov 22 01:12:12 PM PST 23
Peak memory 198488 kb
Host smart-d57fcd2f-1f8c-46ad-aeb3-859f8f094658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37499862829091529528352815289325317819838592637379618241738230370206103521114 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.hmac_long_msg.37499862829091529528352815289325317819838592637379618241738230370206103521114
Directory /workspace/33.hmac_long_msg/latest

Test location /workspace/coverage/default/33.hmac_smoke.28802995655517257126617149381535052228572025985486081366269374856852295009730
Short name T447
Test name
Test status
Simulation time 631560191 ps
CPU time 4.18 seconds
Started Nov 22 01:09:59 PM PST 23
Finished Nov 22 01:10:06 PM PST 23
Peak memory 198540 kb
Host smart-cdce7e7d-9266-4d48-bbd2-7feac4707a01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28802995655517257126617149381535052228572025985486081366269374856852295009730 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 33.hmac_smoke.28802995655517257126617149381535052228572025985486081366269374856852295009730
Directory /workspace/33.hmac_smoke/latest

Test location /workspace/coverage/default/33.hmac_stress_all.109565350562587886308427187386022795785012735415288246319228673696756443271762
Short name T397
Test name
Test status
Simulation time 146644856361 ps
CPU time 1149.54 seconds
Started Nov 22 01:10:14 PM PST 23
Finished Nov 22 01:29:27 PM PST 23
Peak memory 210820 kb
Host smart-4ed81a1a-f9e8-45a1-89b9-95a28462b54b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109565350562587886308427
187386022795785012735415288246319228673696756443271762 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_stress_all.1095653505625878863084
27187386022795785012735415288246319228673696756443271762
Directory /workspace/33.hmac_stress_all/latest

Test location /workspace/coverage/default/33.hmac_stress_all_with_rand_reset.111759849637907377967179076195132347519181665800285784774266997513232009899538
Short name T430
Test name
Test status
Simulation time 80460760838 ps
CPU time 694.23 seconds
Started Nov 22 01:10:13 PM PST 23
Finished Nov 22 01:21:51 PM PST 23
Peak memory 208984 kb
Host smart-0716012e-9d18-4638-afa1-f7a845811cc3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=111759849637907377967179076195132347519181665800285784774266997513232009899538 -assert nopostproc +UVM_TE
STNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 33.hmac_stress_all_with_rand_reset.111759849637907377967179076195132347519181665800285784774266997513232009899538
Directory /workspace/33.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.hmac_test_hmac_vectors.45458625286346272304483202887073698736236573313595306737424236222811391794517
Short name T292
Test name
Test status
Simulation time 76314633 ps
CPU time 0.96 seconds
Started Nov 22 01:10:16 PM PST 23
Finished Nov 22 01:10:20 PM PST 23
Peak memory 195812 kb
Host smart-a10ecf81-d143-4431-9e5b-c7ac8107ead8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45458625286346272304483202887073698736236573313595306
737424236222811391794517 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_test_hmac_vectors.45458625286346272304483202887073698736
236573313595306737424236222811391794517
Directory /workspace/33.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/33.hmac_test_sha_vectors.80175585061382627668558133353455305533757740688045732783306082596099698597506
Short name T690
Test name
Test status
Simulation time 63914107498 ps
CPU time 459.45 seconds
Started Nov 22 01:10:01 PM PST 23
Finished Nov 22 01:17:43 PM PST 23
Peak memory 198588 kb
Host smart-3033c7e7-7b19-4141-97b7-b3ec4e14818b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80175585061382627668558133353455305533757740688045732
783306082596099698597506 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_test_sha_vectors.8017558506138262766855813335345530553375
7740688045732783306082596099698597506
Directory /workspace/33.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/33.hmac_wipe_secret.34926972303865728763962835331368797189800794356556817713717188213465655071506
Short name T515
Test name
Test status
Simulation time 8070750677 ps
CPU time 64.17 seconds
Started Nov 22 01:09:56 PM PST 23
Finished Nov 22 01:11:02 PM PST 23
Peak memory 198612 kb
Host smart-c818c151-963c-4a89-b7fc-11de3f3c2a3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34926972303865728763962835331368797189800794356556817713717188213465655071506 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 33.hmac_wipe_secret.34926972303865728763962835331368797189800794356556817713717188213465655071506
Directory /workspace/33.hmac_wipe_secret/latest

Test location /workspace/coverage/default/34.hmac_alert_test.80653998100115404505726459919591772971243241757556241770234328767370193036063
Short name T282
Test name
Test status
Simulation time 18011528 ps
CPU time 0.56 seconds
Started Nov 22 01:11:03 PM PST 23
Finished Nov 22 01:11:05 PM PST 23
Peak memory 192652 kb
Host smart-1681e89a-930d-45f0-8a62-d821e391435e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80653998100115404505726459919591772971243241757556241770234328767370193036063 -assert nopostpr
oc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 34.hmac_alert_test.80653998100115404505726459919591772971243241757556241770234328767370193036063
Directory /workspace/34.hmac_alert_test/latest

Test location /workspace/coverage/default/34.hmac_back_pressure.28472607919432873834129134242932161549678784284331582510991686904268310195737
Short name T562
Test name
Test status
Simulation time 2592169506 ps
CPU time 49.74 seconds
Started Nov 22 01:10:18 PM PST 23
Finished Nov 22 01:11:10 PM PST 23
Peak memory 231268 kb
Host smart-81221d24-5af6-4061-9327-2a561c96e8b3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=28472607919432873834129134242932161549678784284331582510991686904268310195737 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 34.hmac_back_pressure.28472607919432873834129134242932161549678784284331582510991686904268310195737
Directory /workspace/34.hmac_back_pressure/latest

Test location /workspace/coverage/default/34.hmac_burst_wr.21090541419863358639703538716710403520450881143162954443286681547474143592212
Short name T472
Test name
Test status
Simulation time 4504100639 ps
CPU time 37.63 seconds
Started Nov 22 01:10:11 PM PST 23
Finished Nov 22 01:10:53 PM PST 23
Peak memory 198568 kb
Host smart-9965b2d8-84c0-4ae3-807a-00241a6fd993
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21090541419863358639703538716710403520450881143162954443286681547474143592212 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 34.hmac_burst_wr.21090541419863358639703538716710403520450881143162954443286681547474143592212
Directory /workspace/34.hmac_burst_wr/latest

Test location /workspace/coverage/default/34.hmac_datapath_stress.54589823423707386248440660646504432135128845607912914291760740852225095571314
Short name T408
Test name
Test status
Simulation time 4863401336 ps
CPU time 140.75 seconds
Started Nov 22 01:10:17 PM PST 23
Finished Nov 22 01:12:41 PM PST 23
Peak memory 198588 kb
Host smart-b0b99fbe-b35e-40bb-8e33-769428d0282d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=54589823423707386248440660646504432135128845607912914291760740852225095571314 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 34.hmac_datapath_stress.54589823423707386248440660646504432135128845607912914291760740852225095571314
Directory /workspace/34.hmac_datapath_stress/latest

Test location /workspace/coverage/default/34.hmac_error.66760575414639552684402520216718932308329653157627162589479186076813637655029
Short name T473
Test name
Test status
Simulation time 26556692074 ps
CPU time 183.67 seconds
Started Nov 22 01:10:20 PM PST 23
Finished Nov 22 01:13:27 PM PST 23
Peak memory 198460 kb
Host smart-fa9c5377-68e2-4b1f-8cf3-c72b2f9d4498
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66760575414639552684402520216718932308329653157627162589479186076813637655029 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 34.hmac_error.66760575414639552684402520216718932308329653157627162589479186076813637655029
Directory /workspace/34.hmac_error/latest

Test location /workspace/coverage/default/34.hmac_long_msg.84008408179118825753185269563556330105627351597445172901157592995460359744933
Short name T249
Test name
Test status
Simulation time 14959266997 ps
CPU time 118.25 seconds
Started Nov 22 01:10:12 PM PST 23
Finished Nov 22 01:12:14 PM PST 23
Peak memory 198596 kb
Host smart-9e044b17-a08a-4753-874a-d3d8e9c97754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84008408179118825753185269563556330105627351597445172901157592995460359744933 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 34.hmac_long_msg.84008408179118825753185269563556330105627351597445172901157592995460359744933
Directory /workspace/34.hmac_long_msg/latest

Test location /workspace/coverage/default/34.hmac_smoke.33005512141830752130243807603457247224665605565481121115192315066905793973557
Short name T726
Test name
Test status
Simulation time 631560191 ps
CPU time 4.21 seconds
Started Nov 22 01:10:12 PM PST 23
Finished Nov 22 01:10:20 PM PST 23
Peak memory 198516 kb
Host smart-4f2ff35b-ab15-4723-92e1-0c5f9ead7bc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33005512141830752130243807603457247224665605565481121115192315066905793973557 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 34.hmac_smoke.33005512141830752130243807603457247224665605565481121115192315066905793973557
Directory /workspace/34.hmac_smoke/latest

Test location /workspace/coverage/default/34.hmac_stress_all.44165071467927689897368580657710987947353890969942528693745437819181162016581
Short name T239
Test name
Test status
Simulation time 146644856361 ps
CPU time 1122.78 seconds
Started Nov 22 01:10:20 PM PST 23
Finished Nov 22 01:29:06 PM PST 23
Peak memory 210860 kb
Host smart-506e0ef0-c647-44b1-8ac0-03d96a70759f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441650714679276898973685
80657710987947353890969942528693745437819181162016581 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_stress_all.44165071467927689897368
580657710987947353890969942528693745437819181162016581
Directory /workspace/34.hmac_stress_all/latest

Test location /workspace/coverage/default/34.hmac_stress_all_with_rand_reset.47112551719165057856615956333443669037540847081798195389669981633303919829725
Short name T627
Test name
Test status
Simulation time 80460760838 ps
CPU time 697.06 seconds
Started Nov 22 01:10:18 PM PST 23
Finished Nov 22 01:21:58 PM PST 23
Peak memory 209360 kb
Host smart-c4666e0b-c301-48c6-8a33-d40a9befbd0e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=47112551719165057856615956333443669037540847081798195389669981633303919829725 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 34.hmac_stress_all_with_rand_reset.47112551719165057856615956333443669037540847081798195389669981633303919829725
Directory /workspace/34.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.hmac_test_hmac_vectors.42213076295309438988032108106489962972816342038487091946034362205708160156455
Short name T470
Test name
Test status
Simulation time 76314633 ps
CPU time 0.89 seconds
Started Nov 22 01:10:18 PM PST 23
Finished Nov 22 01:10:21 PM PST 23
Peak memory 195800 kb
Host smart-3ca7ba13-3d30-4f2b-8cee-858c9ca212ee
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42213076295309438988032108106489962972816342038487091
946034362205708160156455 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_test_hmac_vectors.42213076295309438988032108106489962972
816342038487091946034362205708160156455
Directory /workspace/34.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/34.hmac_test_sha_vectors.94325875561803430832154917707234442460048419989970818459556695364531896758348
Short name T801
Test name
Test status
Simulation time 63914107498 ps
CPU time 455.54 seconds
Started Nov 22 01:10:20 PM PST 23
Finished Nov 22 01:17:58 PM PST 23
Peak memory 198608 kb
Host smart-8d7b81ee-64ef-4da3-9929-9c3e38e45a58
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94325875561803430832154917707234442460048419989970818
459556695364531896758348 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_test_sha_vectors.9432587556180343083215491770723444246004
8419989970818459556695364531896758348
Directory /workspace/34.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/34.hmac_wipe_secret.98107590390788344626939319707271205585140036409110554430239258701964437188770
Short name T563
Test name
Test status
Simulation time 8070750677 ps
CPU time 59.07 seconds
Started Nov 22 01:10:20 PM PST 23
Finished Nov 22 01:11:22 PM PST 23
Peak memory 198460 kb
Host smart-3289b138-2358-4a52-b41e-2001592274ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98107590390788344626939319707271205585140036409110554430239258701964437188770 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 34.hmac_wipe_secret.98107590390788344626939319707271205585140036409110554430239258701964437188770
Directory /workspace/34.hmac_wipe_secret/latest

Test location /workspace/coverage/default/35.hmac_alert_test.63983113614797305350653062928367973760757759773049062215456994370077601573473
Short name T712
Test name
Test status
Simulation time 18011528 ps
CPU time 0.53 seconds
Started Nov 22 01:10:20 PM PST 23
Finished Nov 22 01:10:24 PM PST 23
Peak memory 192836 kb
Host smart-9ade6655-dc49-4883-be8c-c35b9f1bfe86
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63983113614797305350653062928367973760757759773049062215456994370077601573473 -assert nopostpr
oc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 35.hmac_alert_test.63983113614797305350653062928367973760757759773049062215456994370077601573473
Directory /workspace/35.hmac_alert_test/latest

Test location /workspace/coverage/default/35.hmac_back_pressure.3472754044265880805051203445915196116045739713570530636298762957643974935017
Short name T618
Test name
Test status
Simulation time 2592169506 ps
CPU time 44.05 seconds
Started Nov 22 01:10:46 PM PST 23
Finished Nov 22 01:11:32 PM PST 23
Peak memory 230852 kb
Host smart-4c7d64f8-5a08-4000-9f10-45c3e03edaed
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3472754044265880805051203445915196116045739713570530636298762957643974935017 -assert nopostproc +UVM_TEST
NAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 35.hmac_back_pressure.3472754044265880805051203445915196116045739713570530636298762957643974935017
Directory /workspace/35.hmac_back_pressure/latest

Test location /workspace/coverage/default/35.hmac_burst_wr.73258505432207062220337563970775621819533353227333187780376916295351354313962
Short name T196
Test name
Test status
Simulation time 4504100639 ps
CPU time 37.5 seconds
Started Nov 22 01:10:20 PM PST 23
Finished Nov 22 01:11:01 PM PST 23
Peak memory 198548 kb
Host smart-01732108-982c-44e2-98ae-89e58efd2557
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73258505432207062220337563970775621819533353227333187780376916295351354313962 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 35.hmac_burst_wr.73258505432207062220337563970775621819533353227333187780376916295351354313962
Directory /workspace/35.hmac_burst_wr/latest

Test location /workspace/coverage/default/35.hmac_datapath_stress.96798244720171238906258974273182881074579411725164708209267129369824379797570
Short name T816
Test name
Test status
Simulation time 4863401336 ps
CPU time 144.46 seconds
Started Nov 22 01:11:03 PM PST 23
Finished Nov 22 01:13:29 PM PST 23
Peak memory 198360 kb
Host smart-cda504d2-ae86-4496-b563-f351cca10a83
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=96798244720171238906258974273182881074579411725164708209267129369824379797570 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 35.hmac_datapath_stress.96798244720171238906258974273182881074579411725164708209267129369824379797570
Directory /workspace/35.hmac_datapath_stress/latest

Test location /workspace/coverage/default/35.hmac_error.30935150922427318755256515705004269798481366895068961888260041216410883239439
Short name T591
Test name
Test status
Simulation time 26556692074 ps
CPU time 197.81 seconds
Started Nov 22 01:10:06 PM PST 23
Finished Nov 22 01:13:28 PM PST 23
Peak memory 198532 kb
Host smart-2093263c-29df-4dce-a66b-9ac94b3e6167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30935150922427318755256515705004269798481366895068961888260041216410883239439 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 35.hmac_error.30935150922427318755256515705004269798481366895068961888260041216410883239439
Directory /workspace/35.hmac_error/latest

Test location /workspace/coverage/default/35.hmac_long_msg.72500817233080890719015945350397402804057922886977147142268514260761046629843
Short name T584
Test name
Test status
Simulation time 14959266997 ps
CPU time 115.16 seconds
Started Nov 22 01:10:19 PM PST 23
Finished Nov 22 01:12:17 PM PST 23
Peak memory 198560 kb
Host smart-85aa5664-7780-40a5-aaa9-fec36696f663
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72500817233080890719015945350397402804057922886977147142268514260761046629843 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 35.hmac_long_msg.72500817233080890719015945350397402804057922886977147142268514260761046629843
Directory /workspace/35.hmac_long_msg/latest

Test location /workspace/coverage/default/35.hmac_smoke.29495021576303224150835127800305961877749986513190657426791865848972672807496
Short name T529
Test name
Test status
Simulation time 631560191 ps
CPU time 4.16 seconds
Started Nov 22 01:10:21 PM PST 23
Finished Nov 22 01:10:29 PM PST 23
Peak memory 198520 kb
Host smart-0b74004d-2341-41bd-8189-a8a7fd4b2392
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29495021576303224150835127800305961877749986513190657426791865848972672807496 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 35.hmac_smoke.29495021576303224150835127800305961877749986513190657426791865848972672807496
Directory /workspace/35.hmac_smoke/latest

Test location /workspace/coverage/default/35.hmac_stress_all.54573531560388999044841958319090311921090991023771165535766239116052474091045
Short name T764
Test name
Test status
Simulation time 146644856361 ps
CPU time 1121 seconds
Started Nov 22 01:10:17 PM PST 23
Finished Nov 22 01:29:01 PM PST 23
Peak memory 210772 kb
Host smart-78663569-8c60-41f0-8bd6-cb11590bde09
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545735315603889990448419
58319090311921090991023771165535766239116052474091045 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_stress_all.54573531560388999044841
958319090311921090991023771165535766239116052474091045
Directory /workspace/35.hmac_stress_all/latest

Test location /workspace/coverage/default/35.hmac_stress_all_with_rand_reset.90271836409622688225415774869032500299653470959043280075028029090692987530344
Short name T478
Test name
Test status
Simulation time 80460760838 ps
CPU time 709.31 seconds
Started Nov 22 01:10:17 PM PST 23
Finished Nov 22 01:22:09 PM PST 23
Peak memory 209272 kb
Host smart-bf968425-a2f4-412c-8098-22442769647e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=90271836409622688225415774869032500299653470959043280075028029090692987530344 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 35.hmac_stress_all_with_rand_reset.90271836409622688225415774869032500299653470959043280075028029090692987530344
Directory /workspace/35.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.hmac_test_hmac_vectors.95153305408670779656892196783254390095910753643812089856057654361417617622315
Short name T409
Test name
Test status
Simulation time 76314633 ps
CPU time 0.92 seconds
Started Nov 22 01:10:21 PM PST 23
Finished Nov 22 01:10:25 PM PST 23
Peak memory 195756 kb
Host smart-1edfee97-7780-4784-8b12-df7b2eecc8da
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95153305408670779656892196783254390095910753643812089
856057654361417617622315 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_test_hmac_vectors.95153305408670779656892196783254390095
910753643812089856057654361417617622315
Directory /workspace/35.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/35.hmac_test_sha_vectors.30236475565622240345080072703027830474387961883183476330489217604646036435648
Short name T678
Test name
Test status
Simulation time 63914107498 ps
CPU time 460.45 seconds
Started Nov 22 01:10:19 PM PST 23
Finished Nov 22 01:18:02 PM PST 23
Peak memory 198520 kb
Host smart-bafd5818-29c6-4af1-b430-8e3b091229a4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30236475565622240345080072703027830474387961883183476
330489217604646036435648 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_test_sha_vectors.3023647556562224034508007270302783047438
7961883183476330489217604646036435648
Directory /workspace/35.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/35.hmac_wipe_secret.69710389331229469719371784432248380151572380303421564230206277611841851989012
Short name T340
Test name
Test status
Simulation time 8070750677 ps
CPU time 62.61 seconds
Started Nov 22 01:10:21 PM PST 23
Finished Nov 22 01:11:28 PM PST 23
Peak memory 198568 kb
Host smart-69c2fc70-6492-45d3-b7df-b7cb216df2f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69710389331229469719371784432248380151572380303421564230206277611841851989012 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 35.hmac_wipe_secret.69710389331229469719371784432248380151572380303421564230206277611841851989012
Directory /workspace/35.hmac_wipe_secret/latest

Test location /workspace/coverage/default/36.hmac_alert_test.17722437610351963507953673626585084889348747707186476069669971708138269576543
Short name T681
Test name
Test status
Simulation time 18011528 ps
CPU time 0.55 seconds
Started Nov 22 01:10:01 PM PST 23
Finished Nov 22 01:10:04 PM PST 23
Peak memory 192752 kb
Host smart-5c07a74c-df50-428d-9699-8f998aceef11
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17722437610351963507953673626585084889348747707186476069669971708138269576543 -assert nopostpr
oc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 36.hmac_alert_test.17722437610351963507953673626585084889348747707186476069669971708138269576543
Directory /workspace/36.hmac_alert_test/latest

Test location /workspace/coverage/default/36.hmac_back_pressure.85864399717023591619356497962591700559363044692173620671969862979202067324943
Short name T42
Test name
Test status
Simulation time 2592169506 ps
CPU time 49.06 seconds
Started Nov 22 01:10:09 PM PST 23
Finished Nov 22 01:11:02 PM PST 23
Peak memory 231332 kb
Host smart-83e9ebf1-b7d4-436a-a8fc-649d43b4f48f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=85864399717023591619356497962591700559363044692173620671969862979202067324943 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 36.hmac_back_pressure.85864399717023591619356497962591700559363044692173620671969862979202067324943
Directory /workspace/36.hmac_back_pressure/latest

Test location /workspace/coverage/default/36.hmac_burst_wr.96885825723640175595115063838142359974703455617913622601071698359314146875789
Short name T270
Test name
Test status
Simulation time 4504100639 ps
CPU time 37.27 seconds
Started Nov 22 01:10:19 PM PST 23
Finished Nov 22 01:10:59 PM PST 23
Peak memory 198548 kb
Host smart-2b48286e-be28-4391-9ff6-bc9b91fd89aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96885825723640175595115063838142359974703455617913622601071698359314146875789 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 36.hmac_burst_wr.96885825723640175595115063838142359974703455617913622601071698359314146875789
Directory /workspace/36.hmac_burst_wr/latest

Test location /workspace/coverage/default/36.hmac_datapath_stress.58918617721514706517025508527253425685172948111222006115029285109391000582642
Short name T574
Test name
Test status
Simulation time 4863401336 ps
CPU time 145.38 seconds
Started Nov 22 01:10:05 PM PST 23
Finished Nov 22 01:12:35 PM PST 23
Peak memory 198604 kb
Host smart-d04a4fb5-7b2b-4ed6-b9e7-a6374d38cbc3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=58918617721514706517025508527253425685172948111222006115029285109391000582642 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 36.hmac_datapath_stress.58918617721514706517025508527253425685172948111222006115029285109391000582642
Directory /workspace/36.hmac_datapath_stress/latest

Test location /workspace/coverage/default/36.hmac_error.5875882958705385501082834834147552360090670552809796756992083144281307854357
Short name T827
Test name
Test status
Simulation time 26556692074 ps
CPU time 201.12 seconds
Started Nov 22 01:10:05 PM PST 23
Finished Nov 22 01:13:31 PM PST 23
Peak memory 198620 kb
Host smart-8a4952a7-921e-4c44-9e70-3552902d78e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5875882958705385501082834834147552360090670552809796756992083144281307854357 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 36.hmac_error.5875882958705385501082834834147552360090670552809796756992083144281307854357
Directory /workspace/36.hmac_error/latest

Test location /workspace/coverage/default/36.hmac_long_msg.44675463336603721063929627366817304439310039261137961003626386987463878752537
Short name T640
Test name
Test status
Simulation time 14959266997 ps
CPU time 115.22 seconds
Started Nov 22 01:10:13 PM PST 23
Finished Nov 22 01:12:12 PM PST 23
Peak memory 198540 kb
Host smart-5c26ed73-c528-4342-aeed-983bfeb25227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44675463336603721063929627366817304439310039261137961003626386987463878752537 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 36.hmac_long_msg.44675463336603721063929627366817304439310039261137961003626386987463878752537
Directory /workspace/36.hmac_long_msg/latest

Test location /workspace/coverage/default/36.hmac_smoke.13246652459522921979696096314767068902975798272456146731128128217988714829894
Short name T339
Test name
Test status
Simulation time 631560191 ps
CPU time 4.05 seconds
Started Nov 22 01:10:08 PM PST 23
Finished Nov 22 01:10:16 PM PST 23
Peak memory 198532 kb
Host smart-7e5f0c73-7969-47c3-a7d7-954864d38ce5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13246652459522921979696096314767068902975798272456146731128128217988714829894 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 36.hmac_smoke.13246652459522921979696096314767068902975798272456146731128128217988714829894
Directory /workspace/36.hmac_smoke/latest

Test location /workspace/coverage/default/36.hmac_stress_all.41335339605643935253465550236536047104223491047914823930195590658629913390982
Short name T641
Test name
Test status
Simulation time 146644856361 ps
CPU time 1120.13 seconds
Started Nov 22 01:10:09 PM PST 23
Finished Nov 22 01:28:54 PM PST 23
Peak memory 210892 kb
Host smart-982b860f-a2be-4f4a-8c0d-a5088a252cc0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413353396056439352534655
50236536047104223491047914823930195590658629913390982 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_stress_all.41335339605643935253465
550236536047104223491047914823930195590658629913390982
Directory /workspace/36.hmac_stress_all/latest

Test location /workspace/coverage/default/36.hmac_stress_all_with_rand_reset.107641182739732501836697268705571365977822120481812011844736668759054013846965
Short name T686
Test name
Test status
Simulation time 80460760838 ps
CPU time 708.4 seconds
Started Nov 22 01:10:14 PM PST 23
Finished Nov 22 01:22:06 PM PST 23
Peak memory 209340 kb
Host smart-a068a3e8-d69e-409d-b7dd-7a8b5b702247
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=107641182739732501836697268705571365977822120481812011844736668759054013846965 -assert nopostproc +UVM_TE
STNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 36.hmac_stress_all_with_rand_reset.107641182739732501836697268705571365977822120481812011844736668759054013846965
Directory /workspace/36.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.hmac_test_hmac_vectors.63458431361675664986122005022145866936637558174001630908217214241941290459575
Short name T175
Test name
Test status
Simulation time 76314633 ps
CPU time 0.91 seconds
Started Nov 22 01:10:08 PM PST 23
Finished Nov 22 01:10:13 PM PST 23
Peak memory 195760 kb
Host smart-d28618fe-f518-49f4-a135-107a377680f4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63458431361675664986122005022145866936637558174001630
908217214241941290459575 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_test_hmac_vectors.63458431361675664986122005022145866936
637558174001630908217214241941290459575
Directory /workspace/36.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/36.hmac_test_sha_vectors.104240938893129612762313941366876444059194645067693248119689960533787068256742
Short name T322
Test name
Test status
Simulation time 63914107498 ps
CPU time 459.43 seconds
Started Nov 22 01:09:59 PM PST 23
Finished Nov 22 01:17:41 PM PST 23
Peak memory 198564 kb
Host smart-1fb2ac24-a607-4f08-a826-10d495ec9312
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10424093889312961276231394136687644405919464506769324
8119689960533787068256742 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_test_sha_vectors.104240938893129612762313941366876444059
194645067693248119689960533787068256742
Directory /workspace/36.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/36.hmac_wipe_secret.28836601319038790736965410476737305044417250457037244303060096028311623107337
Short name T242
Test name
Test status
Simulation time 8070750677 ps
CPU time 61.48 seconds
Started Nov 22 01:10:19 PM PST 23
Finished Nov 22 01:11:23 PM PST 23
Peak memory 198516 kb
Host smart-ce5186f4-e946-462b-8ef5-4b81f7e9339b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28836601319038790736965410476737305044417250457037244303060096028311623107337 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 36.hmac_wipe_secret.28836601319038790736965410476737305044417250457037244303060096028311623107337
Directory /workspace/36.hmac_wipe_secret/latest

Test location /workspace/coverage/default/37.hmac_alert_test.86083058883209046988379618157532001679975713301462336004506730853021617258800
Short name T389
Test name
Test status
Simulation time 18011528 ps
CPU time 0.56 seconds
Started Nov 22 01:10:00 PM PST 23
Finished Nov 22 01:10:03 PM PST 23
Peak memory 192804 kb
Host smart-ec579e22-1347-4446-bfc3-7899dc564b88
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86083058883209046988379618157532001679975713301462336004506730853021617258800 -assert nopostpr
oc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 37.hmac_alert_test.86083058883209046988379618157532001679975713301462336004506730853021617258800
Directory /workspace/37.hmac_alert_test/latest

Test location /workspace/coverage/default/37.hmac_back_pressure.95462103025943925256467647576315340714631203228689115965218785691663550290946
Short name T823
Test name
Test status
Simulation time 2592169506 ps
CPU time 49.29 seconds
Started Nov 22 01:10:06 PM PST 23
Finished Nov 22 01:11:00 PM PST 23
Peak memory 231244 kb
Host smart-327cbc3d-6661-4f1e-8488-b241929d6493
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=95462103025943925256467647576315340714631203228689115965218785691663550290946 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 37.hmac_back_pressure.95462103025943925256467647576315340714631203228689115965218785691663550290946
Directory /workspace/37.hmac_back_pressure/latest

Test location /workspace/coverage/default/37.hmac_burst_wr.58545959289604771895370579510239969719278965452140058808021699676354055193194
Short name T285
Test name
Test status
Simulation time 4504100639 ps
CPU time 37.46 seconds
Started Nov 22 01:10:08 PM PST 23
Finished Nov 22 01:10:50 PM PST 23
Peak memory 198552 kb
Host smart-66fc09c3-bb31-428b-bc23-1f079d2c4ff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58545959289604771895370579510239969719278965452140058808021699676354055193194 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.hmac_burst_wr.58545959289604771895370579510239969719278965452140058808021699676354055193194
Directory /workspace/37.hmac_burst_wr/latest

Test location /workspace/coverage/default/37.hmac_datapath_stress.63376414891223521080590911733740919079736174786168193918762514237227564271778
Short name T535
Test name
Test status
Simulation time 4863401336 ps
CPU time 147.45 seconds
Started Nov 22 01:09:58 PM PST 23
Finished Nov 22 01:12:26 PM PST 23
Peak memory 198516 kb
Host smart-cb0fcde3-1156-492d-88a4-669b2bbc7ecb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=63376414891223521080590911733740919079736174786168193918762514237227564271778 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 37.hmac_datapath_stress.63376414891223521080590911733740919079736174786168193918762514237227564271778
Directory /workspace/37.hmac_datapath_stress/latest

Test location /workspace/coverage/default/37.hmac_error.38319431368825336418378032585772101984089577507823596299429082348750856414553
Short name T275
Test name
Test status
Simulation time 26556692074 ps
CPU time 186.43 seconds
Started Nov 22 01:10:07 PM PST 23
Finished Nov 22 01:13:18 PM PST 23
Peak memory 198600 kb
Host smart-008e559e-fbd9-4fb6-89d0-e95e9a5777e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38319431368825336418378032585772101984089577507823596299429082348750856414553 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 37.hmac_error.38319431368825336418378032585772101984089577507823596299429082348750856414553
Directory /workspace/37.hmac_error/latest

Test location /workspace/coverage/default/37.hmac_long_msg.54197476285877931365639981483253965763487834051244156330241726654451623352535
Short name T716
Test name
Test status
Simulation time 14959266997 ps
CPU time 116.81 seconds
Started Nov 22 01:10:10 PM PST 23
Finished Nov 22 01:12:12 PM PST 23
Peak memory 198536 kb
Host smart-e2503484-7988-4301-90e2-106246417603
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54197476285877931365639981483253965763487834051244156330241726654451623352535 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.hmac_long_msg.54197476285877931365639981483253965763487834051244156330241726654451623352535
Directory /workspace/37.hmac_long_msg/latest

Test location /workspace/coverage/default/37.hmac_smoke.39193870780123273998833811880907556041591531406895218992939141570813927025861
Short name T829
Test name
Test status
Simulation time 631560191 ps
CPU time 4 seconds
Started Nov 22 01:10:01 PM PST 23
Finished Nov 22 01:10:08 PM PST 23
Peak memory 198400 kb
Host smart-6e3d787d-7de3-4806-986c-cf6f3800b928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39193870780123273998833811880907556041591531406895218992939141570813927025861 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 37.hmac_smoke.39193870780123273998833811880907556041591531406895218992939141570813927025861
Directory /workspace/37.hmac_smoke/latest

Test location /workspace/coverage/default/37.hmac_stress_all.74084091726972276741135098354785680743541074430044686268060161725484276738980
Short name T811
Test name
Test status
Simulation time 146644856361 ps
CPU time 1114.6 seconds
Started Nov 22 01:10:04 PM PST 23
Finished Nov 22 01:28:44 PM PST 23
Peak memory 210800 kb
Host smart-6c6dfcb4-c0c8-4356-9963-8bebdb0329a9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740840917269722767411350
98354785680743541074430044686268060161725484276738980 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_stress_all.74084091726972276741135
098354785680743541074430044686268060161725484276738980
Directory /workspace/37.hmac_stress_all/latest

Test location /workspace/coverage/default/37.hmac_stress_all_with_rand_reset.62248978679945803450216129127107020393932158173070647429711755285122496106143
Short name T505
Test name
Test status
Simulation time 80460760838 ps
CPU time 689.47 seconds
Started Nov 22 01:10:05 PM PST 23
Finished Nov 22 01:21:39 PM PST 23
Peak memory 209312 kb
Host smart-0e84028d-2712-4a5a-9190-027f5cd15bf8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=62248978679945803450216129127107020393932158173070647429711755285122496106143 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 37.hmac_stress_all_with_rand_reset.62248978679945803450216129127107020393932158173070647429711755285122496106143
Directory /workspace/37.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.hmac_test_hmac_vectors.5158672378737410268718819406262552964957609110250163900587978796657247087128
Short name T50
Test name
Test status
Simulation time 76314633 ps
CPU time 0.95 seconds
Started Nov 22 01:10:08 PM PST 23
Finished Nov 22 01:10:13 PM PST 23
Peak memory 195776 kb
Host smart-ee5605f6-8e9d-4c2f-8581-c9ca3bb07440
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51586723787374102687188194062625529649576091102501639
00587978796657247087128 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_test_hmac_vectors.515867237873741026871881940626255296495
7609110250163900587978796657247087128
Directory /workspace/37.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/37.hmac_test_sha_vectors.6001252141300033840856422514573673277626531137339715359778918225139955647767
Short name T817
Test name
Test status
Simulation time 63914107498 ps
CPU time 465.86 seconds
Started Nov 22 01:10:07 PM PST 23
Finished Nov 22 01:17:57 PM PST 23
Peak memory 198416 kb
Host smart-848fa299-9691-472d-87d8-24a768847654
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60012521413000338408564225145736732776265311373397153
59778918225139955647767 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_test_sha_vectors.60012521413000338408564225145736732776265
31137339715359778918225139955647767
Directory /workspace/37.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/37.hmac_wipe_secret.11625760185031261433015878131967278980095796279498740832169477404054692794716
Short name T866
Test name
Test status
Simulation time 8070750677 ps
CPU time 64.09 seconds
Started Nov 22 01:10:13 PM PST 23
Finished Nov 22 01:11:22 PM PST 23
Peak memory 198576 kb
Host smart-bb708bd8-f8ff-4cfc-a4f6-dc1bdda2ff95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11625760185031261433015878131967278980095796279498740832169477404054692794716 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 37.hmac_wipe_secret.11625760185031261433015878131967278980095796279498740832169477404054692794716
Directory /workspace/37.hmac_wipe_secret/latest

Test location /workspace/coverage/default/38.hmac_alert_test.27928901560570166258163917225511533889255383664787203561062509213837159739771
Short name T401
Test name
Test status
Simulation time 18011528 ps
CPU time 0.58 seconds
Started Nov 22 01:10:13 PM PST 23
Finished Nov 22 01:10:18 PM PST 23
Peak memory 192868 kb
Host smart-28759441-5adc-4276-82a0-59bfa79c3d5a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27928901560570166258163917225511533889255383664787203561062509213837159739771 -assert nopostpr
oc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 38.hmac_alert_test.27928901560570166258163917225511533889255383664787203561062509213837159739771
Directory /workspace/38.hmac_alert_test/latest

Test location /workspace/coverage/default/38.hmac_back_pressure.3237565318769489093609683473294605105954400450095115363200049420974594091724
Short name T796
Test name
Test status
Simulation time 2592169506 ps
CPU time 47.35 seconds
Started Nov 22 01:10:13 PM PST 23
Finished Nov 22 01:11:04 PM PST 23
Peak memory 230788 kb
Host smart-fac14617-9be7-4a49-97ea-ed8388e8077b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3237565318769489093609683473294605105954400450095115363200049420974594091724 -assert nopostproc +UVM_TEST
NAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 38.hmac_back_pressure.3237565318769489093609683473294605105954400450095115363200049420974594091724
Directory /workspace/38.hmac_back_pressure/latest

Test location /workspace/coverage/default/38.hmac_burst_wr.10718780008122249476378295301193623041862329723899008765884650609486050855755
Short name T492
Test name
Test status
Simulation time 4504100639 ps
CPU time 37.81 seconds
Started Nov 22 01:10:08 PM PST 23
Finished Nov 22 01:10:49 PM PST 23
Peak memory 198552 kb
Host smart-32aec42a-21f1-420e-ad59-4e83b1982bc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10718780008122249476378295301193623041862329723899008765884650609486050855755 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 38.hmac_burst_wr.10718780008122249476378295301193623041862329723899008765884650609486050855755
Directory /workspace/38.hmac_burst_wr/latest

Test location /workspace/coverage/default/38.hmac_datapath_stress.90343107831531533525087622011765337412526992992239769584030069573708385886170
Short name T436
Test name
Test status
Simulation time 4863401336 ps
CPU time 145.59 seconds
Started Nov 22 01:10:12 PM PST 23
Finished Nov 22 01:12:42 PM PST 23
Peak memory 198580 kb
Host smart-558ddc2d-3692-488d-ab5d-dfcf4e9244d1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=90343107831531533525087622011765337412526992992239769584030069573708385886170 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 38.hmac_datapath_stress.90343107831531533525087622011765337412526992992239769584030069573708385886170
Directory /workspace/38.hmac_datapath_stress/latest

Test location /workspace/coverage/default/38.hmac_error.80081231669848745755171287860859294996659322124277390065655762945268019713291
Short name T54
Test name
Test status
Simulation time 26556692074 ps
CPU time 193.85 seconds
Started Nov 22 01:10:23 PM PST 23
Finished Nov 22 01:13:41 PM PST 23
Peak memory 198416 kb
Host smart-42c0c7ee-3ad8-458e-b106-3789a3271529
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80081231669848745755171287860859294996659322124277390065655762945268019713291 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 38.hmac_error.80081231669848745755171287860859294996659322124277390065655762945268019713291
Directory /workspace/38.hmac_error/latest

Test location /workspace/coverage/default/38.hmac_long_msg.77676425987994394022500774002466739560159013993916290868118364929123470611116
Short name T420
Test name
Test status
Simulation time 14959266997 ps
CPU time 117.97 seconds
Started Nov 22 01:10:09 PM PST 23
Finished Nov 22 01:12:12 PM PST 23
Peak memory 198476 kb
Host smart-61f83f40-d68c-4abb-be99-562885625788
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77676425987994394022500774002466739560159013993916290868118364929123470611116 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 38.hmac_long_msg.77676425987994394022500774002466739560159013993916290868118364929123470611116
Directory /workspace/38.hmac_long_msg/latest

Test location /workspace/coverage/default/38.hmac_smoke.87698210905537612671628461309916932567617666712943153029491563227111479494738
Short name T861
Test name
Test status
Simulation time 631560191 ps
CPU time 4.22 seconds
Started Nov 22 01:10:11 PM PST 23
Finished Nov 22 01:10:19 PM PST 23
Peak memory 198496 kb
Host smart-bae774b4-7041-40cc-bb29-b3039d33ef12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87698210905537612671628461309916932567617666712943153029491563227111479494738 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 38.hmac_smoke.87698210905537612671628461309916932567617666712943153029491563227111479494738
Directory /workspace/38.hmac_smoke/latest

Test location /workspace/coverage/default/38.hmac_stress_all.94770749256054550584762903121688208553461661803755317605334448455680044362494
Short name T69
Test name
Test status
Simulation time 146644856361 ps
CPU time 1156.5 seconds
Started Nov 22 01:10:10 PM PST 23
Finished Nov 22 01:29:31 PM PST 23
Peak memory 210768 kb
Host smart-216fd6f8-1286-414a-8c7b-60e43c891d21
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947707492560545505847629
03121688208553461661803755317605334448455680044362494 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_stress_all.94770749256054550584762
903121688208553461661803755317605334448455680044362494
Directory /workspace/38.hmac_stress_all/latest

Test location /workspace/coverage/default/38.hmac_stress_all_with_rand_reset.89791693965549930112992631268694127939558344549880091188444568299246769743605
Short name T359
Test name
Test status
Simulation time 80460760838 ps
CPU time 698.79 seconds
Started Nov 22 01:10:10 PM PST 23
Finished Nov 22 01:21:53 PM PST 23
Peak memory 209360 kb
Host smart-aa03acdb-06de-4323-b042-61d0220f035e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=89791693965549930112992631268694127939558344549880091188444568299246769743605 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 38.hmac_stress_all_with_rand_reset.89791693965549930112992631268694127939558344549880091188444568299246769743605
Directory /workspace/38.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.hmac_test_hmac_vectors.94161656754508177189682611065965175304949599203777543133944070376338952951939
Short name T273
Test name
Test status
Simulation time 76314633 ps
CPU time 0.98 seconds
Started Nov 22 01:10:13 PM PST 23
Finished Nov 22 01:10:18 PM PST 23
Peak memory 195796 kb
Host smart-210754f8-c965-42df-b109-ce86f05f1d25
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94161656754508177189682611065965175304949599203777543
133944070376338952951939 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_test_hmac_vectors.94161656754508177189682611065965175304
949599203777543133944070376338952951939
Directory /workspace/38.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/38.hmac_test_sha_vectors.3063145419322057024229478813458744336013782374203176716452072518866165090621
Short name T11
Test name
Test status
Simulation time 63914107498 ps
CPU time 433.63 seconds
Started Nov 22 01:10:02 PM PST 23
Finished Nov 22 01:17:20 PM PST 23
Peak memory 198560 kb
Host smart-dab85e1c-6150-417e-bd8e-7912279064a8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30631454193220570242294788134587443360137823742031767
16452072518866165090621 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_test_sha_vectors.30631454193220570242294788134587443360137
82374203176716452072518866165090621
Directory /workspace/38.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/38.hmac_wipe_secret.60950335273789890316014029479057492015078830085266617909523661469055800926522
Short name T552
Test name
Test status
Simulation time 8070750677 ps
CPU time 61.33 seconds
Started Nov 22 01:10:04 PM PST 23
Finished Nov 22 01:11:11 PM PST 23
Peak memory 198556 kb
Host smart-ea665a04-e592-4fd2-b509-570407f7a152
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60950335273789890316014029479057492015078830085266617909523661469055800926522 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 38.hmac_wipe_secret.60950335273789890316014029479057492015078830085266617909523661469055800926522
Directory /workspace/38.hmac_wipe_secret/latest

Test location /workspace/coverage/default/39.hmac_alert_test.66370355038802804127739066755435744260362499978139244141565885868972300542276
Short name T617
Test name
Test status
Simulation time 18011528 ps
CPU time 0.55 seconds
Started Nov 22 01:10:06 PM PST 23
Finished Nov 22 01:10:11 PM PST 23
Peak memory 192756 kb
Host smart-52bc942c-aab7-40ae-b402-3938ab637857
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66370355038802804127739066755435744260362499978139244141565885868972300542276 -assert nopostpr
oc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 39.hmac_alert_test.66370355038802804127739066755435744260362499978139244141565885868972300542276
Directory /workspace/39.hmac_alert_test/latest

Test location /workspace/coverage/default/39.hmac_back_pressure.13861273585510356466291919181060429933196414867833905381211748366267684541014
Short name T34
Test name
Test status
Simulation time 2592169506 ps
CPU time 48.07 seconds
Started Nov 22 01:10:06 PM PST 23
Finished Nov 22 01:10:58 PM PST 23
Peak memory 231128 kb
Host smart-d5d6e704-0f83-4b91-a481-603dcdb4acc9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=13861273585510356466291919181060429933196414867833905381211748366267684541014 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 39.hmac_back_pressure.13861273585510356466291919181060429933196414867833905381211748366267684541014
Directory /workspace/39.hmac_back_pressure/latest

Test location /workspace/coverage/default/39.hmac_burst_wr.35577424728234525582439715446856424572041030184897770234842550418292743583038
Short name T384
Test name
Test status
Simulation time 4504100639 ps
CPU time 39.1 seconds
Started Nov 22 01:10:13 PM PST 23
Finished Nov 22 01:10:57 PM PST 23
Peak memory 198540 kb
Host smart-1869b69e-59ce-48dc-a561-74039cb04d87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35577424728234525582439715446856424572041030184897770234842550418292743583038 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 39.hmac_burst_wr.35577424728234525582439715446856424572041030184897770234842550418292743583038
Directory /workspace/39.hmac_burst_wr/latest

Test location /workspace/coverage/default/39.hmac_datapath_stress.84643814850501961266096646909425972951185307013881209292653285652074862580512
Short name T858
Test name
Test status
Simulation time 4863401336 ps
CPU time 139.87 seconds
Started Nov 22 01:10:05 PM PST 23
Finished Nov 22 01:12:30 PM PST 23
Peak memory 198556 kb
Host smart-01cafe6d-1bd5-4457-8c1f-758769bfcf2e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=84643814850501961266096646909425972951185307013881209292653285652074862580512 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 39.hmac_datapath_stress.84643814850501961266096646909425972951185307013881209292653285652074862580512
Directory /workspace/39.hmac_datapath_stress/latest

Test location /workspace/coverage/default/39.hmac_error.19297708668983406740514641896942666017595663706969808880854319149420686668426
Short name T632
Test name
Test status
Simulation time 26556692074 ps
CPU time 189.63 seconds
Started Nov 22 01:10:08 PM PST 23
Finished Nov 22 01:13:21 PM PST 23
Peak memory 198600 kb
Host smart-c0610241-191a-48c6-9511-8f05b5faf126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19297708668983406740514641896942666017595663706969808880854319149420686668426 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 39.hmac_error.19297708668983406740514641896942666017595663706969808880854319149420686668426
Directory /workspace/39.hmac_error/latest

Test location /workspace/coverage/default/39.hmac_long_msg.67740206753319185472381112698314521209023445387114938669487777445331834928964
Short name T804
Test name
Test status
Simulation time 14959266997 ps
CPU time 118.12 seconds
Started Nov 22 01:10:08 PM PST 23
Finished Nov 22 01:12:10 PM PST 23
Peak memory 198576 kb
Host smart-ba65e817-4dd5-44fa-8fe2-c531b89ce0b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67740206753319185472381112698314521209023445387114938669487777445331834928964 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 39.hmac_long_msg.67740206753319185472381112698314521209023445387114938669487777445331834928964
Directory /workspace/39.hmac_long_msg/latest

Test location /workspace/coverage/default/39.hmac_smoke.80640556501408697894735297691053522108014509670235515611907772433863086955109
Short name T636
Test name
Test status
Simulation time 631560191 ps
CPU time 3.96 seconds
Started Nov 22 01:10:14 PM PST 23
Finished Nov 22 01:10:22 PM PST 23
Peak memory 198312 kb
Host smart-b7b52f4d-ef0b-43da-83e8-c25355b441af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80640556501408697894735297691053522108014509670235515611907772433863086955109 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 39.hmac_smoke.80640556501408697894735297691053522108014509670235515611907772433863086955109
Directory /workspace/39.hmac_smoke/latest

Test location /workspace/coverage/default/39.hmac_stress_all.17050642116115340575291049250287252776560624392367684175646718659183755783183
Short name T252
Test name
Test status
Simulation time 146644856361 ps
CPU time 1149.52 seconds
Started Nov 22 01:10:09 PM PST 23
Finished Nov 22 01:29:23 PM PST 23
Peak memory 210776 kb
Host smart-81c15e01-0d4e-4f9f-b45b-42423a9fb4ef
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170506421161153405752910
49250287252776560624392367684175646718659183755783183 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_stress_all.17050642116115340575291
049250287252776560624392367684175646718659183755783183
Directory /workspace/39.hmac_stress_all/latest

Test location /workspace/coverage/default/39.hmac_stress_all_with_rand_reset.64282861643787670696855232969095972160342696920275446559594180039351738208428
Short name T825
Test name
Test status
Simulation time 80460760838 ps
CPU time 696.37 seconds
Started Nov 22 01:10:05 PM PST 23
Finished Nov 22 01:21:46 PM PST 23
Peak memory 209272 kb
Host smart-dbcfa117-8d39-47bd-9c14-4e7e3ca93b72
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=64282861643787670696855232969095972160342696920275446559594180039351738208428 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 39.hmac_stress_all_with_rand_reset.64282861643787670696855232969095972160342696920275446559594180039351738208428
Directory /workspace/39.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.hmac_test_hmac_vectors.78997802943005018724562484684204159493953235108579842575947204979998978662036
Short name T182
Test name
Test status
Simulation time 76314633 ps
CPU time 0.92 seconds
Started Nov 22 01:10:06 PM PST 23
Finished Nov 22 01:10:11 PM PST 23
Peak memory 195764 kb
Host smart-eebaacf0-65bf-4ee6-be5b-e0e97a149709
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78997802943005018724562484684204159493953235108579842
575947204979998978662036 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_test_hmac_vectors.78997802943005018724562484684204159493
953235108579842575947204979998978662036
Directory /workspace/39.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/39.hmac_test_sha_vectors.21908256328286257931833930155109989221105973626793893072608978984291444131874
Short name T594
Test name
Test status
Simulation time 63914107498 ps
CPU time 475.95 seconds
Started Nov 22 01:10:03 PM PST 23
Finished Nov 22 01:18:03 PM PST 23
Peak memory 198588 kb
Host smart-c4b5831f-38b4-4ee1-8d83-7e4c81ec0e1d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21908256328286257931833930155109989221105973626793893
072608978984291444131874 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_test_sha_vectors.2190825632828625793183393015510998922110
5973626793893072608978984291444131874
Directory /workspace/39.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/39.hmac_wipe_secret.37957428535924219651531645940335530277114081598827660802984230002777460262534
Short name T532
Test name
Test status
Simulation time 8070750677 ps
CPU time 61.47 seconds
Started Nov 22 01:10:02 PM PST 23
Finished Nov 22 01:11:07 PM PST 23
Peak memory 198616 kb
Host smart-c62b90be-a3c5-44ab-80da-64158af57e19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37957428535924219651531645940335530277114081598827660802984230002777460262534 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 39.hmac_wipe_secret.37957428535924219651531645940335530277114081598827660802984230002777460262534
Directory /workspace/39.hmac_wipe_secret/latest

Test location /workspace/coverage/default/4.hmac_alert_test.110378409693765838326357311426910103373065039628094133705148061490745906127560
Short name T838
Test name
Test status
Simulation time 18011528 ps
CPU time 0.55 seconds
Started Nov 22 01:09:06 PM PST 23
Finished Nov 22 01:09:14 PM PST 23
Peak memory 192800 kb
Host smart-0af5635a-fb2c-40b0-a735-d3fde9e626c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110378409693765838326357311426910103373065039628094133705148061490745906127560 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 4.hmac_alert_test.110378409693765838326357311426910103373065039628094133705148061490745906127560
Directory /workspace/4.hmac_alert_test/latest

Test location /workspace/coverage/default/4.hmac_back_pressure.34457372806626537771496820099390369720348946385365278019848850879174592772157
Short name T45
Test name
Test status
Simulation time 2592169506 ps
CPU time 48.55 seconds
Started Nov 22 01:09:03 PM PST 23
Finished Nov 22 01:10:00 PM PST 23
Peak memory 231328 kb
Host smart-80cedf70-88c8-429c-98d6-f43572ce3247
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=34457372806626537771496820099390369720348946385365278019848850879174592772157 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 4.hmac_back_pressure.34457372806626537771496820099390369720348946385365278019848850879174592772157
Directory /workspace/4.hmac_back_pressure/latest

Test location /workspace/coverage/default/4.hmac_burst_wr.100811979964100406089843346384601725125694264416118525521802195604215324924682
Short name T518
Test name
Test status
Simulation time 4504100639 ps
CPU time 37.27 seconds
Started Nov 22 01:09:07 PM PST 23
Finished Nov 22 01:09:52 PM PST 23
Peak memory 198484 kb
Host smart-dd9a16fb-21d4-4589-ad89-4c577105e42e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100811979964100406089843346384601725125694264416118525521802195604215324924682 -assert nopostproc +UVM_TESTNAME=hmac_bas
e_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 4.hmac_burst_wr.100811979964100406089843346384601725125694264416118525521802195604215324924682
Directory /workspace/4.hmac_burst_wr/latest

Test location /workspace/coverage/default/4.hmac_datapath_stress.84994326218104486496017931655388266116559502053972210327134697352531827327089
Short name T255
Test name
Test status
Simulation time 4863401336 ps
CPU time 148.92 seconds
Started Nov 22 01:09:03 PM PST 23
Finished Nov 22 01:11:40 PM PST 23
Peak memory 198548 kb
Host smart-722a5988-3ab0-4a65-b523-1041ca72ff89
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=84994326218104486496017931655388266116559502053972210327134697352531827327089 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 4.hmac_datapath_stress.84994326218104486496017931655388266116559502053972210327134697352531827327089
Directory /workspace/4.hmac_datapath_stress/latest

Test location /workspace/coverage/default/4.hmac_error.17568297894565355856150970383720564312288279324788424734480577120702139787013
Short name T253
Test name
Test status
Simulation time 26556692074 ps
CPU time 190.63 seconds
Started Nov 22 01:09:03 PM PST 23
Finished Nov 22 01:12:22 PM PST 23
Peak memory 198544 kb
Host smart-6b873f9c-3be1-4c26-98a9-9c4a3169553d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17568297894565355856150970383720564312288279324788424734480577120702139787013 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 4.hmac_error.17568297894565355856150970383720564312288279324788424734480577120702139787013
Directory /workspace/4.hmac_error/latest

Test location /workspace/coverage/default/4.hmac_long_msg.91839390754830344102821707305867083525001605089441880356982435548839854637680
Short name T793
Test name
Test status
Simulation time 14959266997 ps
CPU time 121.37 seconds
Started Nov 22 01:09:04 PM PST 23
Finished Nov 22 01:11:13 PM PST 23
Peak memory 198532 kb
Host smart-8b947945-0c80-4d4b-a8c3-bf7263a256a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91839390754830344102821707305867083525001605089441880356982435548839854637680 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 4.hmac_long_msg.91839390754830344102821707305867083525001605089441880356982435548839854637680
Directory /workspace/4.hmac_long_msg/latest

Test location /workspace/coverage/default/4.hmac_sec_cm.50573244111593990703848215216868200108252572949528878224348033565362357807451
Short name T63
Test name
Test status
Simulation time 100939436 ps
CPU time 0.88 seconds
Started Nov 22 01:09:01 PM PST 23
Finished Nov 22 01:09:12 PM PST 23
Peak memory 215916 kb
Host smart-a4d19493-a551-4eca-8958-686bc65123a4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50573244111593990703848215216868200108252572949528878224348033565362357807451 -assert nopostpro
c +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 4.hmac_sec_cm.50573244111593990703848215216868200108252572949528878224348033565362357807451
Directory /workspace/4.hmac_sec_cm/latest

Test location /workspace/coverage/default/4.hmac_smoke.39059591126586776330139815597971783960917765485692935015752100065509578471495
Short name T702
Test name
Test status
Simulation time 631560191 ps
CPU time 4.2 seconds
Started Nov 22 01:09:05 PM PST 23
Finished Nov 22 01:09:16 PM PST 23
Peak memory 198524 kb
Host smart-173baf24-16dd-46ee-9b20-250624386c0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39059591126586776330139815597971783960917765485692935015752100065509578471495 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 4.hmac_smoke.39059591126586776330139815597971783960917765485692935015752100065509578471495
Directory /workspace/4.hmac_smoke/latest

Test location /workspace/coverage/default/4.hmac_stress_all.19296554355199017682249081872316821145330109603727657099721937906980866746910
Short name T391
Test name
Test status
Simulation time 146644856361 ps
CPU time 1130.97 seconds
Started Nov 22 01:09:03 PM PST 23
Finished Nov 22 01:28:02 PM PST 23
Peak memory 210852 kb
Host smart-5735be44-6194-40ae-ad01-cc192578e920
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192965543551990176822490
81872316821145330109603727657099721937906980866746910 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all.192965543551990176822490
81872316821145330109603727657099721937906980866746910
Directory /workspace/4.hmac_stress_all/latest

Test location /workspace/coverage/default/4.hmac_stress_all_with_rand_reset.106392922588903113642919542248740291937596134136814485879076703358810508022183
Short name T289
Test name
Test status
Simulation time 80460760838 ps
CPU time 728.81 seconds
Started Nov 22 01:09:02 PM PST 23
Finished Nov 22 01:21:20 PM PST 23
Peak memory 209372 kb
Host smart-52edfe29-4b14-4922-8f89-2c86c286b230
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=106392922588903113642919542248740291937596134136814485879076703358810508022183 -assert nopostproc +UVM_TE
STNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 4.hmac_stress_all_with_rand_reset.106392922588903113642919542248740291937596134136814485879076703358810508022183
Directory /workspace/4.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.hmac_test_hmac_vectors.107619291229238758545993937431696410341382792823392562241677179210924537989956
Short name T819
Test name
Test status
Simulation time 76314633 ps
CPU time 0.92 seconds
Started Nov 22 01:09:06 PM PST 23
Finished Nov 22 01:09:15 PM PST 23
Peak memory 195732 kb
Host smart-17d447fa-ae44-4cbc-b84d-81077b09da43
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10761929122923875854599393743169641034138279282339256
2241677179210924537989956 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac_vectors.10761929122923875854599393743169641034
1382792823392562241677179210924537989956
Directory /workspace/4.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha_vectors.99197070674850879200626654544914646772479728846163773284209834887569605233808
Short name T220
Test name
Test status
Simulation time 63914107498 ps
CPU time 464.8 seconds
Started Nov 22 01:09:06 PM PST 23
Finished Nov 22 01:16:59 PM PST 23
Peak memory 198560 kb
Host smart-a6bd5d1d-e88a-4dbe-85e2-7cf521bac20c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99197070674850879200626654544914646772479728846163773
284209834887569605233808 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha_vectors.99197070674850879200626654544914646772479
728846163773284209834887569605233808
Directory /workspace/4.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/4.hmac_wipe_secret.31447273692401620011409077768786278444688441633066149435843034009196834780077
Short name T369
Test name
Test status
Simulation time 8070750677 ps
CPU time 62.47 seconds
Started Nov 22 01:09:17 PM PST 23
Finished Nov 22 01:10:21 PM PST 23
Peak memory 198460 kb
Host smart-c0b298c9-35f5-4255-ac0a-d41632dbb401
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31447273692401620011409077768786278444688441633066149435843034009196834780077 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 4.hmac_wipe_secret.31447273692401620011409077768786278444688441633066149435843034009196834780077
Directory /workspace/4.hmac_wipe_secret/latest

Test location /workspace/coverage/default/40.hmac_alert_test.13973829369980382918193928144287552341904557360910863505650969352571110416236
Short name T206
Test name
Test status
Simulation time 18011528 ps
CPU time 0.6 seconds
Started Nov 22 01:10:11 PM PST 23
Finished Nov 22 01:10:16 PM PST 23
Peak memory 192888 kb
Host smart-1ea003a1-caaa-4c20-af0d-5207212729ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13973829369980382918193928144287552341904557360910863505650969352571110416236 -assert nopostpr
oc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 40.hmac_alert_test.13973829369980382918193928144287552341904557360910863505650969352571110416236
Directory /workspace/40.hmac_alert_test/latest

Test location /workspace/coverage/default/40.hmac_back_pressure.16319871563909061394357442725608622144622106877046884732208399737162029874798
Short name T849
Test name
Test status
Simulation time 2592169506 ps
CPU time 48.82 seconds
Started Nov 22 01:10:04 PM PST 23
Finished Nov 22 01:10:58 PM PST 23
Peak memory 231316 kb
Host smart-2bcc4f0f-fbf7-4b1c-82a9-c7b7111700c0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=16319871563909061394357442725608622144622106877046884732208399737162029874798 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 40.hmac_back_pressure.16319871563909061394357442725608622144622106877046884732208399737162029874798
Directory /workspace/40.hmac_back_pressure/latest

Test location /workspace/coverage/default/40.hmac_burst_wr.40642661674596126480489676027682225192917104805188048484694378176128899817354
Short name T578
Test name
Test status
Simulation time 4504100639 ps
CPU time 38.04 seconds
Started Nov 22 01:10:13 PM PST 23
Finished Nov 22 01:10:55 PM PST 23
Peak memory 197876 kb
Host smart-dce5e5fb-5ab3-4254-99b0-04b15728ce19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40642661674596126480489676027682225192917104805188048484694378176128899817354 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.hmac_burst_wr.40642661674596126480489676027682225192917104805188048484694378176128899817354
Directory /workspace/40.hmac_burst_wr/latest

Test location /workspace/coverage/default/40.hmac_datapath_stress.67196856203731155819839286373712393264237788455602234559734451208452125279297
Short name T64
Test name
Test status
Simulation time 4863401336 ps
CPU time 146.11 seconds
Started Nov 22 01:10:07 PM PST 23
Finished Nov 22 01:12:37 PM PST 23
Peak memory 198440 kb
Host smart-def0887f-9970-4054-9786-3d09cc15ad56
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=67196856203731155819839286373712393264237788455602234559734451208452125279297 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 40.hmac_datapath_stress.67196856203731155819839286373712393264237788455602234559734451208452125279297
Directory /workspace/40.hmac_datapath_stress/latest

Test location /workspace/coverage/default/40.hmac_error.36785589856736320081820661277818612401948923560619257183508622888501393115825
Short name T776
Test name
Test status
Simulation time 26556692074 ps
CPU time 184.52 seconds
Started Nov 22 01:10:12 PM PST 23
Finished Nov 22 01:13:21 PM PST 23
Peak memory 198380 kb
Host smart-f4feb642-8e34-4f47-a86b-55b397f4a700
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36785589856736320081820661277818612401948923560619257183508622888501393115825 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 40.hmac_error.36785589856736320081820661277818612401948923560619257183508622888501393115825
Directory /workspace/40.hmac_error/latest

Test location /workspace/coverage/default/40.hmac_long_msg.114931137575605082155495996904770642478995931198124938089804970010713698746114
Short name T564
Test name
Test status
Simulation time 14959266997 ps
CPU time 119.79 seconds
Started Nov 22 01:10:07 PM PST 23
Finished Nov 22 01:12:11 PM PST 23
Peak memory 198576 kb
Host smart-e6bc837a-0955-412e-a6cd-26338f5e9916
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114931137575605082155495996904770642478995931198124938089804970010713698746114 -assert nopostproc +UVM_TESTNAME=hmac_bas
e_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 40.hmac_long_msg.114931137575605082155495996904770642478995931198124938089804970010713698746114
Directory /workspace/40.hmac_long_msg/latest

Test location /workspace/coverage/default/40.hmac_smoke.101413295436946743823166881644642588142508970903838183639860552865389266630710
Short name T237
Test name
Test status
Simulation time 631560191 ps
CPU time 4.31 seconds
Started Nov 22 01:10:20 PM PST 23
Finished Nov 22 01:10:28 PM PST 23
Peak memory 198500 kb
Host smart-8846a694-a395-4358-b256-c83234237feb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101413295436946743823166881644642588142508970903838183639860552865389266630710 -assert nopostproc +UVM_TESTNAME=hmac_bas
e_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 40.hmac_smoke.101413295436946743823166881644642588142508970903838183639860552865389266630710
Directory /workspace/40.hmac_smoke/latest

Test location /workspace/coverage/default/40.hmac_stress_all.11425477046229860366588155876742616663883486656729914398844468294224606421089
Short name T258
Test name
Test status
Simulation time 146644856361 ps
CPU time 1141.79 seconds
Started Nov 22 01:10:05 PM PST 23
Finished Nov 22 01:29:12 PM PST 23
Peak memory 210788 kb
Host smart-ac589961-d2ca-4070-9b3a-1c40a9e503f2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114254770462298603665881
55876742616663883486656729914398844468294224606421089 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_stress_all.11425477046229860366588
155876742616663883486656729914398844468294224606421089
Directory /workspace/40.hmac_stress_all/latest

Test location /workspace/coverage/default/40.hmac_stress_all_with_rand_reset.90317508437351172873328566987292232068960487604996938877824535032650954565497
Short name T732
Test name
Test status
Simulation time 80460760838 ps
CPU time 708.97 seconds
Started Nov 22 01:10:10 PM PST 23
Finished Nov 22 01:22:03 PM PST 23
Peak memory 209236 kb
Host smart-3387419f-2593-411f-957a-973f64c7f964
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=90317508437351172873328566987292232068960487604996938877824535032650954565497 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 40.hmac_stress_all_with_rand_reset.90317508437351172873328566987292232068960487604996938877824535032650954565497
Directory /workspace/40.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.hmac_test_hmac_vectors.70242648300598401734092982666455975526050094684351926372486483461487992592147
Short name T670
Test name
Test status
Simulation time 76314633 ps
CPU time 0.92 seconds
Started Nov 22 01:10:13 PM PST 23
Finished Nov 22 01:10:18 PM PST 23
Peak memory 195796 kb
Host smart-356ae2ba-16ec-4d7a-9fd3-999405234436
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70242648300598401734092982666455975526050094684351926
372486483461487992592147 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_test_hmac_vectors.70242648300598401734092982666455975526
050094684351926372486483461487992592147
Directory /workspace/40.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/40.hmac_test_sha_vectors.94263311714693840823431358882830514601613773521921492503141043090939891102295
Short name T700
Test name
Test status
Simulation time 63914107498 ps
CPU time 467.74 seconds
Started Nov 22 01:10:13 PM PST 23
Finished Nov 22 01:18:05 PM PST 23
Peak memory 198580 kb
Host smart-775b8b52-0dcd-42f8-be53-5d3f97185d02
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94263311714693840823431358882830514601613773521921492
503141043090939891102295 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_test_sha_vectors.9426331171469384082343135888283051460161
3773521921492503141043090939891102295
Directory /workspace/40.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/40.hmac_wipe_secret.54865561535109415035242781957786158929007702199695156473460887370377309244237
Short name T293
Test name
Test status
Simulation time 8070750677 ps
CPU time 61.85 seconds
Started Nov 22 01:10:05 PM PST 23
Finished Nov 22 01:11:12 PM PST 23
Peak memory 198556 kb
Host smart-aaab2873-9e13-4ae6-91e8-6f064afe7471
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54865561535109415035242781957786158929007702199695156473460887370377309244237 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 40.hmac_wipe_secret.54865561535109415035242781957786158929007702199695156473460887370377309244237
Directory /workspace/40.hmac_wipe_secret/latest

Test location /workspace/coverage/default/41.hmac_alert_test.9237643209486945306399593461584767441774636195103725858134146029825822115087
Short name T797
Test name
Test status
Simulation time 18011528 ps
CPU time 0.6 seconds
Started Nov 22 01:10:13 PM PST 23
Finished Nov 22 01:10:18 PM PST 23
Peak memory 192264 kb
Host smart-b8cd328f-c695-4b3e-8199-8096996b3fd8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9237643209486945306399593461584767441774636195103725858134146029825822115087 -assert nopostpro
c +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 41.hmac_alert_test.9237643209486945306399593461584767441774636195103725858134146029825822115087
Directory /workspace/41.hmac_alert_test/latest

Test location /workspace/coverage/default/41.hmac_back_pressure.113880906332335841344899868280331713791843509038472246950579145635819017716146
Short name T561
Test name
Test status
Simulation time 2592169506 ps
CPU time 45.76 seconds
Started Nov 22 01:09:59 PM PST 23
Finished Nov 22 01:10:48 PM PST 23
Peak memory 231396 kb
Host smart-8c6b7f99-f409-4616-9ba4-c86b716e78c0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=113880906332335841344899868280331713791843509038472246950579145635819017716146 -assert nopostproc +UVM_TE
STNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 41.hmac_back_pressure.113880906332335841344899868280331713791843509038472246950579145635819017716146
Directory /workspace/41.hmac_back_pressure/latest

Test location /workspace/coverage/default/41.hmac_burst_wr.34671216280304044014426829352119474859246023978384854706705732929047084390613
Short name T633
Test name
Test status
Simulation time 4504100639 ps
CPU time 38.05 seconds
Started Nov 22 01:10:09 PM PST 23
Finished Nov 22 01:10:51 PM PST 23
Peak memory 198380 kb
Host smart-55f73394-be6c-481a-ab45-6b6763240d97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34671216280304044014426829352119474859246023978384854706705732929047084390613 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.hmac_burst_wr.34671216280304044014426829352119474859246023978384854706705732929047084390613
Directory /workspace/41.hmac_burst_wr/latest

Test location /workspace/coverage/default/41.hmac_datapath_stress.4308992764256093075322019826385134427266542706423480256280490640974381380897
Short name T246
Test name
Test status
Simulation time 4863401336 ps
CPU time 146.56 seconds
Started Nov 22 01:10:06 PM PST 23
Finished Nov 22 01:12:37 PM PST 23
Peak memory 198340 kb
Host smart-4810decc-3ba7-4529-9f51-2a63be0cf055
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4308992764256093075322019826385134427266542706423480256280490640974381380897 -assert nopostproc +UVM_TEST
NAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 41.hmac_datapath_stress.4308992764256093075322019826385134427266542706423480256280490640974381380897
Directory /workspace/41.hmac_datapath_stress/latest

Test location /workspace/coverage/default/41.hmac_error.72539095009914189330499725755038764939911828199380449503956453515695081455689
Short name T654
Test name
Test status
Simulation time 26556692074 ps
CPU time 187.98 seconds
Started Nov 22 01:11:04 PM PST 23
Finished Nov 22 01:14:13 PM PST 23
Peak memory 198392 kb
Host smart-38d9ed9d-5e07-4db5-b710-291e62b97c3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72539095009914189330499725755038764939911828199380449503956453515695081455689 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 41.hmac_error.72539095009914189330499725755038764939911828199380449503956453515695081455689
Directory /workspace/41.hmac_error/latest

Test location /workspace/coverage/default/41.hmac_long_msg.85261416835974416824827810461292452806514152594498898421319517250634818695259
Short name T332
Test name
Test status
Simulation time 14959266997 ps
CPU time 119.02 seconds
Started Nov 22 01:10:02 PM PST 23
Finished Nov 22 01:12:06 PM PST 23
Peak memory 198592 kb
Host smart-b2fe15ab-da8d-40e5-82d6-3f5bd86b8a0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85261416835974416824827810461292452806514152594498898421319517250634818695259 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.hmac_long_msg.85261416835974416824827810461292452806514152594498898421319517250634818695259
Directory /workspace/41.hmac_long_msg/latest

Test location /workspace/coverage/default/41.hmac_smoke.89599420116364655569553546933137715738143779116689003402690616588549441481338
Short name T192
Test name
Test status
Simulation time 631560191 ps
CPU time 3.92 seconds
Started Nov 22 01:10:09 PM PST 23
Finished Nov 22 01:10:17 PM PST 23
Peak memory 198436 kb
Host smart-4012c747-5780-450b-baf9-5fb13772ccfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89599420116364655569553546933137715738143779116689003402690616588549441481338 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 41.hmac_smoke.89599420116364655569553546933137715738143779116689003402690616588549441481338
Directory /workspace/41.hmac_smoke/latest

Test location /workspace/coverage/default/41.hmac_stress_all.14926977895425314351323453436399867878315022632184523445195394960829635994662
Short name T658
Test name
Test status
Simulation time 146644856361 ps
CPU time 1163.35 seconds
Started Nov 22 01:10:06 PM PST 23
Finished Nov 22 01:29:34 PM PST 23
Peak memory 210728 kb
Host smart-497fd14f-23ec-4237-be42-430e6da02910
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149269778954253143513234
53436399867878315022632184523445195394960829635994662 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_stress_all.14926977895425314351323
453436399867878315022632184523445195394960829635994662
Directory /workspace/41.hmac_stress_all/latest

Test location /workspace/coverage/default/41.hmac_stress_all_with_rand_reset.93098255876101905555601926597380498515520796880351606869181308057221374950421
Short name T539
Test name
Test status
Simulation time 80460760838 ps
CPU time 701.96 seconds
Started Nov 22 01:10:08 PM PST 23
Finished Nov 22 01:21:54 PM PST 23
Peak memory 209320 kb
Host smart-91b47a60-fa52-47cb-883e-568d79a30c7c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=93098255876101905555601926597380498515520796880351606869181308057221374950421 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 41.hmac_stress_all_with_rand_reset.93098255876101905555601926597380498515520796880351606869181308057221374950421
Directory /workspace/41.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.hmac_test_hmac_vectors.108023658101334804400224574152508180711138152460440933747979775667084010458337
Short name T382
Test name
Test status
Simulation time 76314633 ps
CPU time 0.94 seconds
Started Nov 22 01:10:06 PM PST 23
Finished Nov 22 01:10:12 PM PST 23
Peak memory 195664 kb
Host smart-972ead32-d19e-400e-8ec0-a73cd5aa57ec
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10802365810133480440022457415250818071113815246044093
3747979775667084010458337 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_test_hmac_vectors.1080236581013348044002245741525081807
11138152460440933747979775667084010458337
Directory /workspace/41.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/41.hmac_test_sha_vectors.16581811141667366418094102550631471789117320752509406650157665723804123391405
Short name T500
Test name
Test status
Simulation time 63914107498 ps
CPU time 460.38 seconds
Started Nov 22 01:10:24 PM PST 23
Finished Nov 22 01:18:08 PM PST 23
Peak memory 198388 kb
Host smart-8bd4432f-c9a0-4c59-b451-d7ae22b0abd7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16581811141667366418094102550631471789117320752509406
650157665723804123391405 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_test_sha_vectors.1658181114166736641809410255063147178911
7320752509406650157665723804123391405
Directory /workspace/41.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/41.hmac_wipe_secret.33743428931650045945178571594783543722108511452239806296322062712223776895143
Short name T324
Test name
Test status
Simulation time 8070750677 ps
CPU time 63.4 seconds
Started Nov 22 01:10:10 PM PST 23
Finished Nov 22 01:11:17 PM PST 23
Peak memory 198580 kb
Host smart-924ffe93-a1fe-4354-ab79-15af6e390a58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33743428931650045945178571594783543722108511452239806296322062712223776895143 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 41.hmac_wipe_secret.33743428931650045945178571594783543722108511452239806296322062712223776895143
Directory /workspace/41.hmac_wipe_secret/latest

Test location /workspace/coverage/default/42.hmac_alert_test.73147034788074527351405044481914788830457708264200244347305302868822629029401
Short name T703
Test name
Test status
Simulation time 18011528 ps
CPU time 0.57 seconds
Started Nov 22 01:10:20 PM PST 23
Finished Nov 22 01:10:24 PM PST 23
Peak memory 192888 kb
Host smart-97713569-e865-4210-9f45-24c855dafc5f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73147034788074527351405044481914788830457708264200244347305302868822629029401 -assert nopostpr
oc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 42.hmac_alert_test.73147034788074527351405044481914788830457708264200244347305302868822629029401
Directory /workspace/42.hmac_alert_test/latest

Test location /workspace/coverage/default/42.hmac_back_pressure.100907042490828698378947877246565861389442496107335231737809105976534532856590
Short name T806
Test name
Test status
Simulation time 2592169506 ps
CPU time 47.44 seconds
Started Nov 22 01:10:12 PM PST 23
Finished Nov 22 01:11:04 PM PST 23
Peak memory 231400 kb
Host smart-a1069dbf-3d26-44e6-85ab-b88ae8946aa3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=100907042490828698378947877246565861389442496107335231737809105976534532856590 -assert nopostproc +UVM_TE
STNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 42.hmac_back_pressure.100907042490828698378947877246565861389442496107335231737809105976534532856590
Directory /workspace/42.hmac_back_pressure/latest

Test location /workspace/coverage/default/42.hmac_burst_wr.55242646744832736260245018926585788365439485981476868796743648612286793163786
Short name T859
Test name
Test status
Simulation time 4504100639 ps
CPU time 36.38 seconds
Started Nov 22 01:10:13 PM PST 23
Finished Nov 22 01:10:53 PM PST 23
Peak memory 198572 kb
Host smart-3d828487-f26e-4bc2-ba42-1835bd9e3ce8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55242646744832736260245018926585788365439485981476868796743648612286793163786 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 42.hmac_burst_wr.55242646744832736260245018926585788365439485981476868796743648612286793163786
Directory /workspace/42.hmac_burst_wr/latest

Test location /workspace/coverage/default/42.hmac_datapath_stress.12603306644589780877204465446954967066729470276960331404731341699020161919391
Short name T795
Test name
Test status
Simulation time 4863401336 ps
CPU time 143.84 seconds
Started Nov 22 01:10:13 PM PST 23
Finished Nov 22 01:12:41 PM PST 23
Peak memory 198596 kb
Host smart-140b3e2e-f16e-4fa1-bf91-a9fab73a61fe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=12603306644589780877204465446954967066729470276960331404731341699020161919391 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 42.hmac_datapath_stress.12603306644589780877204465446954967066729470276960331404731341699020161919391
Directory /workspace/42.hmac_datapath_stress/latest

Test location /workspace/coverage/default/42.hmac_error.29236928102921689280769780080723160021001890062433941690161993027516706503589
Short name T398
Test name
Test status
Simulation time 26556692074 ps
CPU time 185.56 seconds
Started Nov 22 01:10:18 PM PST 23
Finished Nov 22 01:13:27 PM PST 23
Peak memory 198456 kb
Host smart-c08f0218-4211-435c-bf05-47ed17da5fcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29236928102921689280769780080723160021001890062433941690161993027516706503589 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 42.hmac_error.29236928102921689280769780080723160021001890062433941690161993027516706503589
Directory /workspace/42.hmac_error/latest

Test location /workspace/coverage/default/42.hmac_long_msg.89597620232152347822532822326454497783785740161447464096105220327372259729920
Short name T271
Test name
Test status
Simulation time 14959266997 ps
CPU time 115.45 seconds
Started Nov 22 01:10:12 PM PST 23
Finished Nov 22 01:12:12 PM PST 23
Peak memory 198564 kb
Host smart-e1d70a82-3cb1-4cc1-bbc1-5ac9745e6db9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89597620232152347822532822326454497783785740161447464096105220327372259729920 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 42.hmac_long_msg.89597620232152347822532822326454497783785740161447464096105220327372259729920
Directory /workspace/42.hmac_long_msg/latest

Test location /workspace/coverage/default/42.hmac_smoke.61635939241949279044713466821413559873176275536057010084953582182649424626647
Short name T646
Test name
Test status
Simulation time 631560191 ps
CPU time 4.12 seconds
Started Nov 22 01:10:15 PM PST 23
Finished Nov 22 01:10:22 PM PST 23
Peak memory 198552 kb
Host smart-e89515fb-5ad9-4dec-9329-fdf143038f23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61635939241949279044713466821413559873176275536057010084953582182649424626647 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 42.hmac_smoke.61635939241949279044713466821413559873176275536057010084953582182649424626647
Directory /workspace/42.hmac_smoke/latest

Test location /workspace/coverage/default/42.hmac_stress_all_with_rand_reset.96074940444989407740423095148806595015865007380507729856453721316009664219744
Short name T543
Test name
Test status
Simulation time 80460760838 ps
CPU time 680.39 seconds
Started Nov 22 01:10:19 PM PST 23
Finished Nov 22 01:21:42 PM PST 23
Peak memory 209208 kb
Host smart-00e55d21-d3ff-4aa1-9c2d-31114a9771a0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=96074940444989407740423095148806595015865007380507729856453721316009664219744 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 42.hmac_stress_all_with_rand_reset.96074940444989407740423095148806595015865007380507729856453721316009664219744
Directory /workspace/42.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.hmac_test_hmac_vectors.90787418282493648834304860584152846056026715355133266670798064964828804420284
Short name T855
Test name
Test status
Simulation time 76314633 ps
CPU time 0.87 seconds
Started Nov 22 01:10:19 PM PST 23
Finished Nov 22 01:10:23 PM PST 23
Peak memory 195816 kb
Host smart-52d0afda-6245-49ca-90f6-91926cd7f275
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90787418282493648834304860584152846056026715355133266
670798064964828804420284 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_test_hmac_vectors.90787418282493648834304860584152846056
026715355133266670798064964828804420284
Directory /workspace/42.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/42.hmac_test_sha_vectors.8789904889562599177333992880904007298284329019511091005050986242222768624793
Short name T628
Test name
Test status
Simulation time 63914107498 ps
CPU time 460.37 seconds
Started Nov 22 01:10:18 PM PST 23
Finished Nov 22 01:18:01 PM PST 23
Peak memory 198600 kb
Host smart-55a79b22-bb8f-45ce-b748-ae15a20cde82
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87899048895625991773339928809040072982843290195110910
05050986242222768624793 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_test_sha_vectors.87899048895625991773339928809040072982843
29019511091005050986242222768624793
Directory /workspace/42.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/42.hmac_wipe_secret.51892356731169668878974102804360738893268822880924870249262671412360847320867
Short name T693
Test name
Test status
Simulation time 8070750677 ps
CPU time 62.42 seconds
Started Nov 22 01:10:17 PM PST 23
Finished Nov 22 01:11:22 PM PST 23
Peak memory 198612 kb
Host smart-112172c4-2eaa-4e80-97b2-1f5f8648918d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51892356731169668878974102804360738893268822880924870249262671412360847320867 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 42.hmac_wipe_secret.51892356731169668878974102804360738893268822880924870249262671412360847320867
Directory /workspace/42.hmac_wipe_secret/latest

Test location /workspace/coverage/default/43.hmac_alert_test.71230746744667759377514211881910542757805644200083131165621712601058771169152
Short name T506
Test name
Test status
Simulation time 18011528 ps
CPU time 0.55 seconds
Started Nov 22 01:10:16 PM PST 23
Finished Nov 22 01:10:20 PM PST 23
Peak memory 192804 kb
Host smart-bc30b26c-8484-439b-a4d9-f55f7ee3452e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71230746744667759377514211881910542757805644200083131165621712601058771169152 -assert nopostpr
oc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 43.hmac_alert_test.71230746744667759377514211881910542757805644200083131165621712601058771169152
Directory /workspace/43.hmac_alert_test/latest

Test location /workspace/coverage/default/43.hmac_back_pressure.26536505618322392271242954539427236952139361143691783195370898009778866459028
Short name T329
Test name
Test status
Simulation time 2592169506 ps
CPU time 46.35 seconds
Started Nov 22 01:10:19 PM PST 23
Finished Nov 22 01:11:08 PM PST 23
Peak memory 231376 kb
Host smart-3e14ddc2-7310-4cab-8254-fb8702413a7b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=26536505618322392271242954539427236952139361143691783195370898009778866459028 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 43.hmac_back_pressure.26536505618322392271242954539427236952139361143691783195370898009778866459028
Directory /workspace/43.hmac_back_pressure/latest

Test location /workspace/coverage/default/43.hmac_burst_wr.92850070124139544626364167311102860808594627517544483210024720222112750587562
Short name T211
Test name
Test status
Simulation time 4504100639 ps
CPU time 36.33 seconds
Started Nov 22 01:10:46 PM PST 23
Finished Nov 22 01:11:24 PM PST 23
Peak memory 198048 kb
Host smart-f16b05a6-8678-4134-8502-07b5a997a632
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92850070124139544626364167311102860808594627517544483210024720222112750587562 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 43.hmac_burst_wr.92850070124139544626364167311102860808594627517544483210024720222112750587562
Directory /workspace/43.hmac_burst_wr/latest

Test location /workspace/coverage/default/43.hmac_datapath_stress.93738676810131701485478985924046223183219218571469932788273267368705422201116
Short name T736
Test name
Test status
Simulation time 4863401336 ps
CPU time 137.6 seconds
Started Nov 22 01:10:46 PM PST 23
Finished Nov 22 01:13:05 PM PST 23
Peak memory 196528 kb
Host smart-c9769797-91ca-4f20-8d49-668760d451d7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=93738676810131701485478985924046223183219218571469932788273267368705422201116 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 43.hmac_datapath_stress.93738676810131701485478985924046223183219218571469932788273267368705422201116
Directory /workspace/43.hmac_datapath_stress/latest

Test location /workspace/coverage/default/43.hmac_error.112657995073331549619573390287942861985222109090529620072170803471074528618125
Short name T53
Test name
Test status
Simulation time 26556692074 ps
CPU time 194.27 seconds
Started Nov 22 01:10:20 PM PST 23
Finished Nov 22 01:13:37 PM PST 23
Peak memory 198568 kb
Host smart-da011c31-3904-406c-b07f-9b1bd6655863
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112657995073331549619573390287942861985222109090529620072170803471074528618125 -assert nopostproc +UVM_TESTNAME=hmac_bas
e_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 43.hmac_error.112657995073331549619573390287942861985222109090529620072170803471074528618125
Directory /workspace/43.hmac_error/latest

Test location /workspace/coverage/default/43.hmac_long_msg.56137599149894790921352743336465773222172905672570890512959536581960529467512
Short name T479
Test name
Test status
Simulation time 14959266997 ps
CPU time 115.81 seconds
Started Nov 22 01:10:46 PM PST 23
Finished Nov 22 01:12:43 PM PST 23
Peak memory 196216 kb
Host smart-b66b1d75-b028-4e79-964f-9ded88900d87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56137599149894790921352743336465773222172905672570890512959536581960529467512 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 43.hmac_long_msg.56137599149894790921352743336465773222172905672570890512959536581960529467512
Directory /workspace/43.hmac_long_msg/latest

Test location /workspace/coverage/default/43.hmac_smoke.12350321706225979215061445216229940343075709843722758207610228606545406985495
Short name T540
Test name
Test status
Simulation time 631560191 ps
CPU time 4.3 seconds
Started Nov 22 01:10:20 PM PST 23
Finished Nov 22 01:10:28 PM PST 23
Peak memory 198520 kb
Host smart-f013ad00-4317-42b3-9d85-f50c92b42c7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12350321706225979215061445216229940343075709843722758207610228606545406985495 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 43.hmac_smoke.12350321706225979215061445216229940343075709843722758207610228606545406985495
Directory /workspace/43.hmac_smoke/latest

Test location /workspace/coverage/default/43.hmac_stress_all.50747294054720109391715406758026077744073996732414399332448544382099623960436
Short name T508
Test name
Test status
Simulation time 146644856361 ps
CPU time 1170.33 seconds
Started Nov 22 01:10:21 PM PST 23
Finished Nov 22 01:29:55 PM PST 23
Peak memory 210888 kb
Host smart-56165f68-807a-4c15-aae9-fbd32661d218
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507472940547201093917154
06758026077744073996732414399332448544382099623960436 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_stress_all.50747294054720109391715
406758026077744073996732414399332448544382099623960436
Directory /workspace/43.hmac_stress_all/latest

Test location /workspace/coverage/default/43.hmac_stress_all_with_rand_reset.99361475850142516571296126632852947537481356528951061416180557629309221220379
Short name T264
Test name
Test status
Simulation time 80460760838 ps
CPU time 667.17 seconds
Started Nov 22 01:10:35 PM PST 23
Finished Nov 22 01:21:43 PM PST 23
Peak memory 209132 kb
Host smart-7c599400-3d81-4388-8087-1a38445ac857
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=99361475850142516571296126632852947537481356528951061416180557629309221220379 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 43.hmac_stress_all_with_rand_reset.99361475850142516571296126632852947537481356528951061416180557629309221220379
Directory /workspace/43.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.hmac_test_hmac_vectors.93385106571988043141972242966660887710576482050703196834695635222535022088431
Short name T609
Test name
Test status
Simulation time 76314633 ps
CPU time 0.9 seconds
Started Nov 22 01:10:19 PM PST 23
Finished Nov 22 01:10:22 PM PST 23
Peak memory 195728 kb
Host smart-3f4ef530-4998-4951-9196-b604b36f396b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93385106571988043141972242966660887710576482050703196
834695635222535022088431 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_test_hmac_vectors.93385106571988043141972242966660887710
576482050703196834695635222535022088431
Directory /workspace/43.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/43.hmac_test_sha_vectors.15926517690228556306860100193687541972204901389524316941032317970529838342672
Short name T174
Test name
Test status
Simulation time 63914107498 ps
CPU time 466.42 seconds
Started Nov 22 01:10:19 PM PST 23
Finished Nov 22 01:18:08 PM PST 23
Peak memory 198540 kb
Host smart-ab7a3097-b7c6-4043-b900-4ce048ead7d9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15926517690228556306860100193687541972204901389524316
941032317970529838342672 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_test_sha_vectors.1592651769022855630686010019368754197220
4901389524316941032317970529838342672
Directory /workspace/43.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/43.hmac_wipe_secret.95524633117877874904860274933115033735526960716138284400068130637744778190193
Short name T388
Test name
Test status
Simulation time 8070750677 ps
CPU time 62.05 seconds
Started Nov 22 01:10:18 PM PST 23
Finished Nov 22 01:11:22 PM PST 23
Peak memory 198516 kb
Host smart-8b1bb9b6-531f-476f-9e81-3c8a670db328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95524633117877874904860274933115033735526960716138284400068130637744778190193 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 43.hmac_wipe_secret.95524633117877874904860274933115033735526960716138284400068130637744778190193
Directory /workspace/43.hmac_wipe_secret/latest

Test location /workspace/coverage/default/44.hmac_alert_test.78097499523204751387883553867074718396904137179596201617184217643153744994121
Short name T689
Test name
Test status
Simulation time 18011528 ps
CPU time 0.54 seconds
Started Nov 22 01:10:21 PM PST 23
Finished Nov 22 01:10:26 PM PST 23
Peak memory 192864 kb
Host smart-81edd98e-007d-4e3a-ba5c-5652ebd6ff0c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78097499523204751387883553867074718396904137179596201617184217643153744994121 -assert nopostpr
oc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 44.hmac_alert_test.78097499523204751387883553867074718396904137179596201617184217643153744994121
Directory /workspace/44.hmac_alert_test/latest

Test location /workspace/coverage/default/44.hmac_back_pressure.21422329706406494068236642545903418202937323018066228202053656960211429160938
Short name T677
Test name
Test status
Simulation time 2592169506 ps
CPU time 48.14 seconds
Started Nov 22 01:10:16 PM PST 23
Finished Nov 22 01:11:07 PM PST 23
Peak memory 231376 kb
Host smart-640c561b-ae61-4116-8549-3a5da21daec1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=21422329706406494068236642545903418202937323018066228202053656960211429160938 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 44.hmac_back_pressure.21422329706406494068236642545903418202937323018066228202053656960211429160938
Directory /workspace/44.hmac_back_pressure/latest

Test location /workspace/coverage/default/44.hmac_burst_wr.19367435898954643507005577477594762845929714539453645345776673092564029859482
Short name T199
Test name
Test status
Simulation time 4504100639 ps
CPU time 38.4 seconds
Started Nov 22 01:10:20 PM PST 23
Finished Nov 22 01:11:02 PM PST 23
Peak memory 198596 kb
Host smart-13656ead-743f-4493-b392-0605d49f441a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19367435898954643507005577477594762845929714539453645345776673092564029859482 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 44.hmac_burst_wr.19367435898954643507005577477594762845929714539453645345776673092564029859482
Directory /workspace/44.hmac_burst_wr/latest

Test location /workspace/coverage/default/44.hmac_datapath_stress.9632776939310856068261182808935264195236027239027201638293570702321584395755
Short name T548
Test name
Test status
Simulation time 4863401336 ps
CPU time 145.93 seconds
Started Nov 22 01:10:21 PM PST 23
Finished Nov 22 01:12:50 PM PST 23
Peak memory 198608 kb
Host smart-b116381c-c86c-4b05-94d8-58cb3d003471
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=9632776939310856068261182808935264195236027239027201638293570702321584395755 -assert nopostproc +UVM_TEST
NAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 44.hmac_datapath_stress.9632776939310856068261182808935264195236027239027201638293570702321584395755
Directory /workspace/44.hmac_datapath_stress/latest

Test location /workspace/coverage/default/44.hmac_error.109041831790605795360952354246244781518771410927109944434555677877390917294688
Short name T520
Test name
Test status
Simulation time 26556692074 ps
CPU time 197.59 seconds
Started Nov 22 01:10:24 PM PST 23
Finished Nov 22 01:13:46 PM PST 23
Peak memory 198436 kb
Host smart-c3c62164-43db-4800-af21-c9876e601a56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109041831790605795360952354246244781518771410927109944434555677877390917294688 -assert nopostproc +UVM_TESTNAME=hmac_bas
e_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 44.hmac_error.109041831790605795360952354246244781518771410927109944434555677877390917294688
Directory /workspace/44.hmac_error/latest

Test location /workspace/coverage/default/44.hmac_long_msg.23433304765569150479416222679392363577768325224595963558548050257039140095860
Short name T572
Test name
Test status
Simulation time 14959266997 ps
CPU time 114.31 seconds
Started Nov 22 01:10:21 PM PST 23
Finished Nov 22 01:12:18 PM PST 23
Peak memory 198472 kb
Host smart-4dde5204-368c-495d-8ef5-2e98c360a04a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23433304765569150479416222679392363577768325224595963558548050257039140095860 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 44.hmac_long_msg.23433304765569150479416222679392363577768325224595963558548050257039140095860
Directory /workspace/44.hmac_long_msg/latest

Test location /workspace/coverage/default/44.hmac_smoke.63740111187068495303681008504602500946150778792079780930859658066001449945146
Short name T723
Test name
Test status
Simulation time 631560191 ps
CPU time 4.08 seconds
Started Nov 22 01:10:23 PM PST 23
Finished Nov 22 01:10:31 PM PST 23
Peak memory 198524 kb
Host smart-31442396-1e92-46ec-9cb5-7cbcbd91fe2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63740111187068495303681008504602500946150778792079780930859658066001449945146 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 44.hmac_smoke.63740111187068495303681008504602500946150778792079780930859658066001449945146
Directory /workspace/44.hmac_smoke/latest

Test location /workspace/coverage/default/44.hmac_stress_all.13196905329396389430739090556536387852128583893891538001461327344120904797279
Short name T383
Test name
Test status
Simulation time 146644856361 ps
CPU time 1114.01 seconds
Started Nov 22 01:10:20 PM PST 23
Finished Nov 22 01:28:58 PM PST 23
Peak memory 210780 kb
Host smart-4c96c6c7-0d46-44b8-a363-12bd6bc6075b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131969053293963894307390
90556536387852128583893891538001461327344120904797279 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_stress_all.13196905329396389430739
090556536387852128583893891538001461327344120904797279
Directory /workspace/44.hmac_stress_all/latest

Test location /workspace/coverage/default/44.hmac_stress_all_with_rand_reset.36460972567023060287113849197341943397536163604970690985451434980404437198632
Short name T386
Test name
Test status
Simulation time 80460760838 ps
CPU time 685.62 seconds
Started Nov 22 01:10:18 PM PST 23
Finished Nov 22 01:21:46 PM PST 23
Peak memory 209300 kb
Host smart-a42b7598-7699-47c7-8c25-eae2ba082a25
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=36460972567023060287113849197341943397536163604970690985451434980404437198632 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 44.hmac_stress_all_with_rand_reset.36460972567023060287113849197341943397536163604970690985451434980404437198632
Directory /workspace/44.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.hmac_test_hmac_vectors.64453612259294348720876382463331699795749417160924271643397816022068232126435
Short name T176
Test name
Test status
Simulation time 76314633 ps
CPU time 0.98 seconds
Started Nov 22 01:10:28 PM PST 23
Finished Nov 22 01:10:31 PM PST 23
Peak memory 195720 kb
Host smart-ac78a34c-0ff6-4ef9-a513-f1b8e991fb22
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64453612259294348720876382463331699795749417160924271
643397816022068232126435 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_test_hmac_vectors.64453612259294348720876382463331699795
749417160924271643397816022068232126435
Directory /workspace/44.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/44.hmac_test_sha_vectors.64628813223818073936354906416914413133787293085320935107494977095811366279851
Short name T651
Test name
Test status
Simulation time 63914107498 ps
CPU time 458.47 seconds
Started Nov 22 01:10:19 PM PST 23
Finished Nov 22 01:18:00 PM PST 23
Peak memory 198556 kb
Host smart-67d5144a-03c6-49d2-a858-07e1352f148a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64628813223818073936354906416914413133787293085320935
107494977095811366279851 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_test_sha_vectors.6462881322381807393635490641691441313378
7293085320935107494977095811366279851
Directory /workspace/44.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/44.hmac_wipe_secret.38152434271217213724069979938280939905744130732242397408437817776235535655298
Short name T488
Test name
Test status
Simulation time 8070750677 ps
CPU time 63.68 seconds
Started Nov 22 01:10:21 PM PST 23
Finished Nov 22 01:11:28 PM PST 23
Peak memory 198544 kb
Host smart-afbd17e2-bbd6-4bcc-becc-4e8bef65d985
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38152434271217213724069979938280939905744130732242397408437817776235535655298 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 44.hmac_wipe_secret.38152434271217213724069979938280939905744130732242397408437817776235535655298
Directory /workspace/44.hmac_wipe_secret/latest

Test location /workspace/coverage/default/45.hmac_alert_test.82273432404845294186186129020656445528207072521106125355599933458041836219099
Short name T771
Test name
Test status
Simulation time 18011528 ps
CPU time 0.54 seconds
Started Nov 22 01:10:27 PM PST 23
Finished Nov 22 01:10:30 PM PST 23
Peak memory 192884 kb
Host smart-bf4ae234-5b4f-4f39-bc63-ac685e1ed466
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82273432404845294186186129020656445528207072521106125355599933458041836219099 -assert nopostpr
oc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 45.hmac_alert_test.82273432404845294186186129020656445528207072521106125355599933458041836219099
Directory /workspace/45.hmac_alert_test/latest

Test location /workspace/coverage/default/45.hmac_back_pressure.36270073770667772990035197899694977546830211267718006960989989291127880170519
Short name T717
Test name
Test status
Simulation time 2592169506 ps
CPU time 49.47 seconds
Started Nov 22 01:10:22 PM PST 23
Finished Nov 22 01:11:16 PM PST 23
Peak memory 231424 kb
Host smart-01ace733-756d-4e2e-9df8-37c6dc2a7fb5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=36270073770667772990035197899694977546830211267718006960989989291127880170519 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 45.hmac_back_pressure.36270073770667772990035197899694977546830211267718006960989989291127880170519
Directory /workspace/45.hmac_back_pressure/latest

Test location /workspace/coverage/default/45.hmac_burst_wr.108459545769285379556962092893855769625379923073951997837557275978937172546030
Short name T205
Test name
Test status
Simulation time 4504100639 ps
CPU time 38.8 seconds
Started Nov 22 01:10:17 PM PST 23
Finished Nov 22 01:10:58 PM PST 23
Peak memory 198544 kb
Host smart-ebde25d2-1fad-4b68-b420-fd171e21151c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108459545769285379556962092893855769625379923073951997837557275978937172546030 -assert nopostproc +UVM_TESTNAME=hmac_bas
e_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 45.hmac_burst_wr.108459545769285379556962092893855769625379923073951997837557275978937172546030
Directory /workspace/45.hmac_burst_wr/latest

Test location /workspace/coverage/default/45.hmac_datapath_stress.70595002152144238964208866398527722800919979105446967473646509315906426133485
Short name T497
Test name
Test status
Simulation time 4863401336 ps
CPU time 148.1 seconds
Started Nov 22 01:10:20 PM PST 23
Finished Nov 22 01:12:52 PM PST 23
Peak memory 198544 kb
Host smart-cc8ecefc-61c4-4224-892e-ad2c8cf53b7e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=70595002152144238964208866398527722800919979105446967473646509315906426133485 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 45.hmac_datapath_stress.70595002152144238964208866398527722800919979105446967473646509315906426133485
Directory /workspace/45.hmac_datapath_stress/latest

Test location /workspace/coverage/default/45.hmac_error.46006637571663442468764447773901660839871414938526938876428169192335601542141
Short name T744
Test name
Test status
Simulation time 26556692074 ps
CPU time 194.27 seconds
Started Nov 22 01:10:21 PM PST 23
Finished Nov 22 01:13:38 PM PST 23
Peak memory 198596 kb
Host smart-e4b10464-d576-49db-a8f0-a313cf366f04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46006637571663442468764447773901660839871414938526938876428169192335601542141 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 45.hmac_error.46006637571663442468764447773901660839871414938526938876428169192335601542141
Directory /workspace/45.hmac_error/latest

Test location /workspace/coverage/default/45.hmac_long_msg.69849278480625734640214900277422058326003126922534317660517627320020305003582
Short name T792
Test name
Test status
Simulation time 14959266997 ps
CPU time 112.47 seconds
Started Nov 22 01:10:21 PM PST 23
Finished Nov 22 01:12:17 PM PST 23
Peak memory 198480 kb
Host smart-de7964a3-bd4c-4d5c-8d0a-c5a46bb4b680
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69849278480625734640214900277422058326003126922534317660517627320020305003582 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.hmac_long_msg.69849278480625734640214900277422058326003126922534317660517627320020305003582
Directory /workspace/45.hmac_long_msg/latest

Test location /workspace/coverage/default/45.hmac_smoke.113757793472071446461683241527015851463873188867781458502879229798554848707373
Short name T576
Test name
Test status
Simulation time 631560191 ps
CPU time 4.09 seconds
Started Nov 22 01:10:21 PM PST 23
Finished Nov 22 01:10:30 PM PST 23
Peak memory 198444 kb
Host smart-9318c270-ccc3-4406-aa11-e2a72f107f05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113757793472071446461683241527015851463873188867781458502879229798554848707373 -assert nopostproc +UVM_TESTNAME=hmac_bas
e_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 45.hmac_smoke.113757793472071446461683241527015851463873188867781458502879229798554848707373
Directory /workspace/45.hmac_smoke/latest

Test location /workspace/coverage/default/45.hmac_stress_all.84583802421945441334603218410596063407613045862728632365827139752382240721695
Short name T832
Test name
Test status
Simulation time 146644856361 ps
CPU time 1123.75 seconds
Started Nov 22 01:10:25 PM PST 23
Finished Nov 22 01:29:13 PM PST 23
Peak memory 210860 kb
Host smart-616bfcd8-8953-4e83-83e0-2435c32c248f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845838024219454413346032
18410596063407613045862728632365827139752382240721695 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_stress_all.84583802421945441334603
218410596063407613045862728632365827139752382240721695
Directory /workspace/45.hmac_stress_all/latest

Test location /workspace/coverage/default/45.hmac_stress_all_with_rand_reset.22286925708714667351289160500033056461297159657836878291968947126171832699762
Short name T411
Test name
Test status
Simulation time 80460760838 ps
CPU time 701.98 seconds
Started Nov 22 01:10:26 PM PST 23
Finished Nov 22 01:22:11 PM PST 23
Peak memory 208680 kb
Host smart-2f2d12cf-46cb-4955-8321-600d7c60e97e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=22286925708714667351289160500033056461297159657836878291968947126171832699762 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 45.hmac_stress_all_with_rand_reset.22286925708714667351289160500033056461297159657836878291968947126171832699762
Directory /workspace/45.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.hmac_test_hmac_vectors.34098720480020780109396115972272789919802951598468007952127449349713125900401
Short name T709
Test name
Test status
Simulation time 76314633 ps
CPU time 0.95 seconds
Started Nov 22 01:10:26 PM PST 23
Finished Nov 22 01:10:30 PM PST 23
Peak memory 195148 kb
Host smart-05a157c7-d554-453e-9b2c-2c0b4181494c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34098720480020780109396115972272789919802951598468007
952127449349713125900401 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_test_hmac_vectors.34098720480020780109396115972272789919
802951598468007952127449349713125900401
Directory /workspace/45.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/45.hmac_test_sha_vectors.83715115188210061562415086416376757924464200304032109197420725702056026690220
Short name T774
Test name
Test status
Simulation time 63914107498 ps
CPU time 461.06 seconds
Started Nov 22 01:10:18 PM PST 23
Finished Nov 22 01:18:02 PM PST 23
Peak memory 198588 kb
Host smart-61e455ad-1a9c-421b-8166-74e9f678f00f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83715115188210061562415086416376757924464200304032109
197420725702056026690220 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_test_sha_vectors.8371511518821006156241508641637675792446
4200304032109197420725702056026690220
Directory /workspace/45.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/45.hmac_wipe_secret.64723012890251436836341420058893888801080093931202670524498415228785834367478
Short name T367
Test name
Test status
Simulation time 8070750677 ps
CPU time 62.52 seconds
Started Nov 22 01:10:22 PM PST 23
Finished Nov 22 01:11:29 PM PST 23
Peak memory 198624 kb
Host smart-79fd8f31-fcfd-4ed7-ae63-e3dba278269d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64723012890251436836341420058893888801080093931202670524498415228785834367478 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 45.hmac_wipe_secret.64723012890251436836341420058893888801080093931202670524498415228785834367478
Directory /workspace/45.hmac_wipe_secret/latest

Test location /workspace/coverage/default/46.hmac_alert_test.42127419173969486262343513939597897741581439963376927151865570954024742409266
Short name T204
Test name
Test status
Simulation time 18011528 ps
CPU time 0.53 seconds
Started Nov 22 01:10:35 PM PST 23
Finished Nov 22 01:10:37 PM PST 23
Peak memory 192696 kb
Host smart-82371d77-0abd-486d-bb9c-7094021f55ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42127419173969486262343513939597897741581439963376927151865570954024742409266 -assert nopostpr
oc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 46.hmac_alert_test.42127419173969486262343513939597897741581439963376927151865570954024742409266
Directory /workspace/46.hmac_alert_test/latest

Test location /workspace/coverage/default/46.hmac_back_pressure.56597354835164782027882120849648015951422295958515255655720567837292827027280
Short name T35
Test name
Test status
Simulation time 2592169506 ps
CPU time 46.27 seconds
Started Nov 22 01:10:34 PM PST 23
Finished Nov 22 01:11:21 PM PST 23
Peak memory 231148 kb
Host smart-94dd6463-949c-45ec-90a2-225a3a8024f4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=56597354835164782027882120849648015951422295958515255655720567837292827027280 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 46.hmac_back_pressure.56597354835164782027882120849648015951422295958515255655720567837292827027280
Directory /workspace/46.hmac_back_pressure/latest

Test location /workspace/coverage/default/46.hmac_burst_wr.60671783833658307777097793071162922003418785402056676161254558854907773914644
Short name T813
Test name
Test status
Simulation time 4504100639 ps
CPU time 37.72 seconds
Started Nov 22 01:10:19 PM PST 23
Finished Nov 22 01:10:59 PM PST 23
Peak memory 198408 kb
Host smart-38ede26e-e531-4900-8d62-d39b226cc68e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60671783833658307777097793071162922003418785402056676161254558854907773914644 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.hmac_burst_wr.60671783833658307777097793071162922003418785402056676161254558854907773914644
Directory /workspace/46.hmac_burst_wr/latest

Test location /workspace/coverage/default/46.hmac_datapath_stress.72051905318370441452449766360391546286261118768882215748577306821352402437881
Short name T731
Test name
Test status
Simulation time 4863401336 ps
CPU time 140.18 seconds
Started Nov 22 01:10:29 PM PST 23
Finished Nov 22 01:12:51 PM PST 23
Peak memory 198564 kb
Host smart-e9f24858-aeee-4bbd-a981-5e41e608700c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=72051905318370441452449766360391546286261118768882215748577306821352402437881 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 46.hmac_datapath_stress.72051905318370441452449766360391546286261118768882215748577306821352402437881
Directory /workspace/46.hmac_datapath_stress/latest

Test location /workspace/coverage/default/46.hmac_error.1059962550074423254141004187120706672644848470596660324193532430036028182386
Short name T869
Test name
Test status
Simulation time 26556692074 ps
CPU time 184.96 seconds
Started Nov 22 01:10:34 PM PST 23
Finished Nov 22 01:13:39 PM PST 23
Peak memory 198360 kb
Host smart-0f4371cd-83bc-46d0-b4fc-ecd603220485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1059962550074423254141004187120706672644848470596660324193532430036028182386 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 46.hmac_error.1059962550074423254141004187120706672644848470596660324193532430036028182386
Directory /workspace/46.hmac_error/latest

Test location /workspace/coverage/default/46.hmac_long_msg.87686001313828830907641305202776608272874400640007943933794375954795355229628
Short name T178
Test name
Test status
Simulation time 14959266997 ps
CPU time 113.01 seconds
Started Nov 22 01:10:33 PM PST 23
Finished Nov 22 01:12:27 PM PST 23
Peak memory 198328 kb
Host smart-164415a0-4351-46ab-bdfb-9f7096daf044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87686001313828830907641305202776608272874400640007943933794375954795355229628 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.hmac_long_msg.87686001313828830907641305202776608272874400640007943933794375954795355229628
Directory /workspace/46.hmac_long_msg/latest

Test location /workspace/coverage/default/46.hmac_smoke.90999387408191825062824655741824042280297374925320649526536979889311154321914
Short name T346
Test name
Test status
Simulation time 631560191 ps
CPU time 4.15 seconds
Started Nov 22 01:10:28 PM PST 23
Finished Nov 22 01:10:34 PM PST 23
Peak memory 198520 kb
Host smart-eb04952b-5b57-4f37-9112-59f0cd364593
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90999387408191825062824655741824042280297374925320649526536979889311154321914 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 46.hmac_smoke.90999387408191825062824655741824042280297374925320649526536979889311154321914
Directory /workspace/46.hmac_smoke/latest

Test location /workspace/coverage/default/46.hmac_stress_all.78767961209241222794153961704545860297926662940748050629924645866874186589106
Short name T309
Test name
Test status
Simulation time 146644856361 ps
CPU time 1084.98 seconds
Started Nov 22 01:10:34 PM PST 23
Finished Nov 22 01:28:41 PM PST 23
Peak memory 210632 kb
Host smart-ccc38aa5-8185-4691-9c4a-3542323b84e6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787679612092412227941539
61704545860297926662940748050629924645866874186589106 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_stress_all.78767961209241222794153
961704545860297926662940748050629924645866874186589106
Directory /workspace/46.hmac_stress_all/latest

Test location /workspace/coverage/default/46.hmac_stress_all_with_rand_reset.74706903569015924796394874236563269162154464570833349506324429490471074343238
Short name T407
Test name
Test status
Simulation time 80460760838 ps
CPU time 703.91 seconds
Started Nov 22 01:10:26 PM PST 23
Finished Nov 22 01:22:13 PM PST 23
Peak memory 209232 kb
Host smart-885cd1d6-cb39-4faa-9c04-65a4612c92e6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=74706903569015924796394874236563269162154464570833349506324429490471074343238 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 46.hmac_stress_all_with_rand_reset.74706903569015924796394874236563269162154464570833349506324429490471074343238
Directory /workspace/46.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.hmac_test_hmac_vectors.2222812810962687927851011545955601173447837338685036316218730880371641426237
Short name T826
Test name
Test status
Simulation time 76314633 ps
CPU time 0.91 seconds
Started Nov 22 01:10:32 PM PST 23
Finished Nov 22 01:10:34 PM PST 23
Peak memory 195740 kb
Host smart-3ed23a07-4261-4a6f-a9a7-b6d8988ad86f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22228128109626879278510115459556011734478373386850363
16218730880371641426237 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_test_hmac_vectors.222281281096268792785101154595560117344
7837338685036316218730880371641426237
Directory /workspace/46.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/46.hmac_test_sha_vectors.82889905711072993610478962176763844277639793925082904231818188648010932813196
Short name T290
Test name
Test status
Simulation time 63914107498 ps
CPU time 465.72 seconds
Started Nov 22 01:10:31 PM PST 23
Finished Nov 22 01:18:18 PM PST 23
Peak memory 198560 kb
Host smart-5b91a914-a68f-4be0-9159-a2e434baaf97
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82889905711072993610478962176763844277639793925082904
231818188648010932813196 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_test_sha_vectors.8288990571107299361047896217676384427763
9793925082904231818188648010932813196
Directory /workspace/46.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/46.hmac_wipe_secret.105645266530832614957955080992932259829082453886573215864593888800568091325925
Short name T229
Test name
Test status
Simulation time 8070750677 ps
CPU time 63.85 seconds
Started Nov 22 01:10:21 PM PST 23
Finished Nov 22 01:11:30 PM PST 23
Peak memory 198560 kb
Host smart-be72b44e-b0ca-49c2-b28c-b888e6ace99c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105645266530832614957955080992932259829082453886573215864593888800568091325925 -assert nopostproc +UVM_TESTNAME=hmac_bas
e_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 46.hmac_wipe_secret.105645266530832614957955080992932259829082453886573215864593888800568091325925
Directory /workspace/46.hmac_wipe_secret/latest

Test location /workspace/coverage/default/47.hmac_alert_test.30907592749737408032133196038748816452566978908208634984351911216418310227916
Short name T251
Test name
Test status
Simulation time 18011528 ps
CPU time 0.55 seconds
Started Nov 22 01:10:47 PM PST 23
Finished Nov 22 01:10:49 PM PST 23
Peak memory 192856 kb
Host smart-c79a3b67-7137-4b48-b278-bcc06b771208
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30907592749737408032133196038748816452566978908208634984351911216418310227916 -assert nopostpr
oc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 47.hmac_alert_test.30907592749737408032133196038748816452566978908208634984351911216418310227916
Directory /workspace/47.hmac_alert_test/latest

Test location /workspace/coverage/default/47.hmac_back_pressure.91930892371221559135503275989590100022653367934383777519596240417763639950824
Short name T7
Test name
Test status
Simulation time 2592169506 ps
CPU time 48.02 seconds
Started Nov 22 01:10:31 PM PST 23
Finished Nov 22 01:11:20 PM PST 23
Peak memory 231364 kb
Host smart-23aba98e-0c31-43d0-baee-c58e3219b634
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=91930892371221559135503275989590100022653367934383777519596240417763639950824 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 47.hmac_back_pressure.91930892371221559135503275989590100022653367934383777519596240417763639950824
Directory /workspace/47.hmac_back_pressure/latest

Test location /workspace/coverage/default/47.hmac_burst_wr.77576876604477662690644743285999235811031191966578836738847123858821991028771
Short name T589
Test name
Test status
Simulation time 4504100639 ps
CPU time 37.6 seconds
Started Nov 22 01:10:32 PM PST 23
Finished Nov 22 01:11:10 PM PST 23
Peak memory 198548 kb
Host smart-0209f240-f792-4b7b-94a1-012d904bbae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77576876604477662690644743285999235811031191966578836738847123858821991028771 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.hmac_burst_wr.77576876604477662690644743285999235811031191966578836738847123858821991028771
Directory /workspace/47.hmac_burst_wr/latest

Test location /workspace/coverage/default/47.hmac_datapath_stress.28803275430585211424332574915600389763433203688471437144763099374270099174675
Short name T524
Test name
Test status
Simulation time 4863401336 ps
CPU time 143.91 seconds
Started Nov 22 01:10:27 PM PST 23
Finished Nov 22 01:12:54 PM PST 23
Peak memory 198488 kb
Host smart-a04903cb-c83a-4f59-995e-5a6836298f6a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=28803275430585211424332574915600389763433203688471437144763099374270099174675 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 47.hmac_datapath_stress.28803275430585211424332574915600389763433203688471437144763099374270099174675
Directory /workspace/47.hmac_datapath_stress/latest

Test location /workspace/coverage/default/47.hmac_error.74722078272829612481046271448337856550003123194742691079385084785915598252784
Short name T708
Test name
Test status
Simulation time 26556692074 ps
CPU time 197.19 seconds
Started Nov 22 01:10:33 PM PST 23
Finished Nov 22 01:13:51 PM PST 23
Peak memory 198588 kb
Host smart-96086be5-7668-41b3-96a2-f74c0a2c65d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74722078272829612481046271448337856550003123194742691079385084785915598252784 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 47.hmac_error.74722078272829612481046271448337856550003123194742691079385084785915598252784
Directory /workspace/47.hmac_error/latest

Test location /workspace/coverage/default/47.hmac_long_msg.114273136887642725886544652179266190547923595153241901113286948302761496351284
Short name T668
Test name
Test status
Simulation time 14959266997 ps
CPU time 117.79 seconds
Started Nov 22 01:10:34 PM PST 23
Finished Nov 22 01:12:33 PM PST 23
Peak memory 198404 kb
Host smart-000f4945-7924-4753-bc80-794af243eb14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114273136887642725886544652179266190547923595153241901113286948302761496351284 -assert nopostproc +UVM_TESTNAME=hmac_bas
e_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 47.hmac_long_msg.114273136887642725886544652179266190547923595153241901113286948302761496351284
Directory /workspace/47.hmac_long_msg/latest

Test location /workspace/coverage/default/47.hmac_smoke.66440737698538684524629298761630937119129381750181232347934498160187668302659
Short name T648
Test name
Test status
Simulation time 631560191 ps
CPU time 4.04 seconds
Started Nov 22 01:10:27 PM PST 23
Finished Nov 22 01:10:34 PM PST 23
Peak memory 198528 kb
Host smart-6bd76398-72c8-4d10-a558-cce92067bfb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66440737698538684524629298761630937119129381750181232347934498160187668302659 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 47.hmac_smoke.66440737698538684524629298761630937119129381750181232347934498160187668302659
Directory /workspace/47.hmac_smoke/latest

Test location /workspace/coverage/default/47.hmac_stress_all.99621601251495140082036472923374384106897043932829597362317754284571821586157
Short name T236
Test name
Test status
Simulation time 146644856361 ps
CPU time 1128.47 seconds
Started Nov 22 01:10:50 PM PST 23
Finished Nov 22 01:29:39 PM PST 23
Peak memory 210704 kb
Host smart-786ab377-5d56-4ffd-8c59-0cb62d354c85
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996216012514951400820364
72923374384106897043932829597362317754284571821586157 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_stress_all.99621601251495140082036
472923374384106897043932829597362317754284571821586157
Directory /workspace/47.hmac_stress_all/latest

Test location /workspace/coverage/default/47.hmac_stress_all_with_rand_reset.98232928154989405137019656927669070527858412042832525170086041737977401724619
Short name T600
Test name
Test status
Simulation time 80460760838 ps
CPU time 723.08 seconds
Started Nov 22 01:10:46 PM PST 23
Finished Nov 22 01:22:51 PM PST 23
Peak memory 209364 kb
Host smart-081ebb22-a3a8-4fd5-973d-67b2d13098be
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=98232928154989405137019656927669070527858412042832525170086041737977401724619 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 47.hmac_stress_all_with_rand_reset.98232928154989405137019656927669070527858412042832525170086041737977401724619
Directory /workspace/47.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.hmac_test_hmac_vectors.115647685502409597107419573996185362130005165903084617282768945755031387382268
Short name T559
Test name
Test status
Simulation time 76314633 ps
CPU time 0.9 seconds
Started Nov 22 01:10:35 PM PST 23
Finished Nov 22 01:10:37 PM PST 23
Peak memory 195756 kb
Host smart-ae662def-baa3-4aa3-bad4-ff53363ca1c1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11564768550240959710741957399618536213000516590308461
7282768945755031387382268 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_test_hmac_vectors.1156476855024095971074195739961853621
30005165903084617282768945755031387382268
Directory /workspace/47.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/47.hmac_test_sha_vectors.62906035997310649218820798635727675863359947613180093455388039705675073033256
Short name T573
Test name
Test status
Simulation time 63914107498 ps
CPU time 472.43 seconds
Started Nov 22 01:10:49 PM PST 23
Finished Nov 22 01:18:42 PM PST 23
Peak memory 198588 kb
Host smart-848b36ea-be87-4d82-bde6-570382ed90d3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62906035997310649218820798635727675863359947613180093
455388039705675073033256 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_test_sha_vectors.6290603599731064921882079863572767586335
9947613180093455388039705675073033256
Directory /workspace/47.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/47.hmac_wipe_secret.28882323534614158832031739198326375771775190868382393339121959687222375059695
Short name T341
Test name
Test status
Simulation time 8070750677 ps
CPU time 60.9 seconds
Started Nov 22 01:10:40 PM PST 23
Finished Nov 22 01:11:42 PM PST 23
Peak memory 198520 kb
Host smart-880b770b-db37-4adb-a252-d081b24cd257
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28882323534614158832031739198326375771775190868382393339121959687222375059695 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 47.hmac_wipe_secret.28882323534614158832031739198326375771775190868382393339121959687222375059695
Directory /workspace/47.hmac_wipe_secret/latest

Test location /workspace/coverage/default/48.hmac_alert_test.54432398695295918523471254814137786738213866530736287118112022667392779492980
Short name T57
Test name
Test status
Simulation time 18011528 ps
CPU time 0.6 seconds
Started Nov 22 01:11:05 PM PST 23
Finished Nov 22 01:11:08 PM PST 23
Peak memory 192844 kb
Host smart-fb4ced87-f245-4765-953d-17e3e3829173
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54432398695295918523471254814137786738213866530736287118112022667392779492980 -assert nopostpr
oc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 48.hmac_alert_test.54432398695295918523471254814137786738213866530736287118112022667392779492980
Directory /workspace/48.hmac_alert_test/latest

Test location /workspace/coverage/default/48.hmac_back_pressure.57170553656739674082936658202795404108485695206788335027027464651560672095669
Short name T718
Test name
Test status
Simulation time 2592169506 ps
CPU time 46.68 seconds
Started Nov 22 01:10:42 PM PST 23
Finished Nov 22 01:11:29 PM PST 23
Peak memory 231392 kb
Host smart-594bec57-1459-4bf0-b924-1d3f1b66efb3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=57170553656739674082936658202795404108485695206788335027027464651560672095669 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 48.hmac_back_pressure.57170553656739674082936658202795404108485695206788335027027464651560672095669
Directory /workspace/48.hmac_back_pressure/latest

Test location /workspace/coverage/default/48.hmac_burst_wr.28080980210080378283416516751034778057385187745513907120877803817179935696838
Short name T537
Test name
Test status
Simulation time 4504100639 ps
CPU time 38.28 seconds
Started Nov 22 01:10:43 PM PST 23
Finished Nov 22 01:11:22 PM PST 23
Peak memory 198536 kb
Host smart-ea003853-c9ca-4378-b2bf-d597bdb69257
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28080980210080378283416516751034778057385187745513907120877803817179935696838 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.hmac_burst_wr.28080980210080378283416516751034778057385187745513907120877803817179935696838
Directory /workspace/48.hmac_burst_wr/latest

Test location /workspace/coverage/default/48.hmac_datapath_stress.17153380845274996416422331417712310062758173191982290403546895885582612266799
Short name T38
Test name
Test status
Simulation time 4863401336 ps
CPU time 149.51 seconds
Started Nov 22 01:10:41 PM PST 23
Finished Nov 22 01:13:11 PM PST 23
Peak memory 198564 kb
Host smart-80f795be-6cd4-4761-81bf-c994040a81c1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=17153380845274996416422331417712310062758173191982290403546895885582612266799 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 48.hmac_datapath_stress.17153380845274996416422331417712310062758173191982290403546895885582612266799
Directory /workspace/48.hmac_datapath_stress/latest

Test location /workspace/coverage/default/48.hmac_error.99693347920154517548574180539396554721062460517778544685894882351378812970568
Short name T791
Test name
Test status
Simulation time 26556692074 ps
CPU time 191.25 seconds
Started Nov 22 01:11:04 PM PST 23
Finished Nov 22 01:14:17 PM PST 23
Peak memory 198548 kb
Host smart-864c61af-0e37-496a-8e21-bd5fbc0f896e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99693347920154517548574180539396554721062460517778544685894882351378812970568 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 48.hmac_error.99693347920154517548574180539396554721062460517778544685894882351378812970568
Directory /workspace/48.hmac_error/latest

Test location /workspace/coverage/default/48.hmac_long_msg.100481027588327905510352491942524069106886665041208376730824070147491842347223
Short name T287
Test name
Test status
Simulation time 14959266997 ps
CPU time 119.57 seconds
Started Nov 22 01:10:45 PM PST 23
Finished Nov 22 01:12:46 PM PST 23
Peak memory 198556 kb
Host smart-b6a7e975-83bd-4319-9955-f812122f766e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100481027588327905510352491942524069106886665041208376730824070147491842347223 -assert nopostproc +UVM_TESTNAME=hmac_bas
e_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 48.hmac_long_msg.100481027588327905510352491942524069106886665041208376730824070147491842347223
Directory /workspace/48.hmac_long_msg/latest

Test location /workspace/coverage/default/48.hmac_smoke.79054443898342348452160077348961700291824599769849822393266400720410973171437
Short name T183
Test name
Test status
Simulation time 631560191 ps
CPU time 4.27 seconds
Started Nov 22 01:10:42 PM PST 23
Finished Nov 22 01:10:47 PM PST 23
Peak memory 198524 kb
Host smart-2f971e3a-d830-46c7-a1e9-7d568d47db97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79054443898342348452160077348961700291824599769849822393266400720410973171437 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 48.hmac_smoke.79054443898342348452160077348961700291824599769849822393266400720410973171437
Directory /workspace/48.hmac_smoke/latest

Test location /workspace/coverage/default/48.hmac_stress_all.85201872361560910073329820228902333803963231997422649463291717321799701693862
Short name T720
Test name
Test status
Simulation time 146644856361 ps
CPU time 1171.87 seconds
Started Nov 22 01:10:44 PM PST 23
Finished Nov 22 01:30:17 PM PST 23
Peak memory 210872 kb
Host smart-42e5b4eb-fdf7-4415-9cba-1f96934c2e2e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852018723615609100733298
20228902333803963231997422649463291717321799701693862 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_stress_all.85201872361560910073329
820228902333803963231997422649463291717321799701693862
Directory /workspace/48.hmac_stress_all/latest

Test location /workspace/coverage/default/48.hmac_stress_all_with_rand_reset.51782927358744592556444530595884728119062805817982412012295537503414059834997
Short name T824
Test name
Test status
Simulation time 80460760838 ps
CPU time 686.09 seconds
Started Nov 22 01:10:59 PM PST 23
Finished Nov 22 01:22:27 PM PST 23
Peak memory 209276 kb
Host smart-26de45c0-b82d-48d0-842e-4b7512c1840f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=51782927358744592556444530595884728119062805817982412012295537503414059834997 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 48.hmac_stress_all_with_rand_reset.51782927358744592556444530595884728119062805817982412012295537503414059834997
Directory /workspace/48.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.hmac_test_hmac_vectors.73706545032681612804914470361557961802997276233727709730304036162937607379535
Short name T664
Test name
Test status
Simulation time 76314633 ps
CPU time 0.95 seconds
Started Nov 22 01:10:45 PM PST 23
Finished Nov 22 01:10:47 PM PST 23
Peak memory 195728 kb
Host smart-129c498e-c0a7-4ec6-a32a-aecf19e3ece4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73706545032681612804914470361557961802997276233727709
730304036162937607379535 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_test_hmac_vectors.73706545032681612804914470361557961802
997276233727709730304036162937607379535
Directory /workspace/48.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/48.hmac_test_sha_vectors.81343871402111972013586743572286185792644799075395839545048930734662083439602
Short name T847
Test name
Test status
Simulation time 63914107498 ps
CPU time 452.19 seconds
Started Nov 22 01:10:58 PM PST 23
Finished Nov 22 01:18:32 PM PST 23
Peak memory 198548 kb
Host smart-23761098-4590-453b-9751-4dfa9c7344f6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81343871402111972013586743572286185792644799075395839
545048930734662083439602 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_test_sha_vectors.8134387140211197201358674357228618579264
4799075395839545048930734662083439602
Directory /workspace/48.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/48.hmac_wipe_secret.101443001279979454761815441231919543292680238591839696996708492228573899282236
Short name T216
Test name
Test status
Simulation time 8070750677 ps
CPU time 60.76 seconds
Started Nov 22 01:10:44 PM PST 23
Finished Nov 22 01:11:46 PM PST 23
Peak memory 198376 kb
Host smart-e30c2750-97dc-4d61-a830-df3a3b190aea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101443001279979454761815441231919543292680238591839696996708492228573899282236 -assert nopostproc +UVM_TESTNAME=hmac_bas
e_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 48.hmac_wipe_secret.101443001279979454761815441231919543292680238591839696996708492228573899282236
Directory /workspace/48.hmac_wipe_secret/latest

Test location /workspace/coverage/default/49.hmac_alert_test.111988958076342761622625410720246012495697575868411091352092143800970363607293
Short name T56
Test name
Test status
Simulation time 18011528 ps
CPU time 0.55 seconds
Started Nov 22 01:10:21 PM PST 23
Finished Nov 22 01:10:25 PM PST 23
Peak memory 192800 kb
Host smart-43eb5096-2dec-4ac5-acd9-34b84ab86f84
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111988958076342761622625410720246012495697575868411091352092143800970363607293 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 49.hmac_alert_test.111988958076342761622625410720246012495697575868411091352092143800970363607293
Directory /workspace/49.hmac_alert_test/latest

Test location /workspace/coverage/default/49.hmac_back_pressure.26620030177374814849248439532560656539663653372967758094396469516327778351521
Short name T785
Test name
Test status
Simulation time 2592169506 ps
CPU time 47.48 seconds
Started Nov 22 01:10:51 PM PST 23
Finished Nov 22 01:11:40 PM PST 23
Peak memory 231356 kb
Host smart-5d42d3e2-3d62-497d-ae93-bd7d2b87d32d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=26620030177374814849248439532560656539663653372967758094396469516327778351521 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 49.hmac_back_pressure.26620030177374814849248439532560656539663653372967758094396469516327778351521
Directory /workspace/49.hmac_back_pressure/latest

Test location /workspace/coverage/default/49.hmac_burst_wr.62586325343467329312683711423882540416816917404622423679864421637139475168820
Short name T9
Test name
Test status
Simulation time 4504100639 ps
CPU time 38.06 seconds
Started Nov 22 01:10:20 PM PST 23
Finished Nov 22 01:11:01 PM PST 23
Peak memory 198596 kb
Host smart-3bc40897-fa41-4d7f-bda2-d20ac0b4c50f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62586325343467329312683711423882540416816917404622423679864421637139475168820 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.hmac_burst_wr.62586325343467329312683711423882540416816917404622423679864421637139475168820
Directory /workspace/49.hmac_burst_wr/latest

Test location /workspace/coverage/default/49.hmac_datapath_stress.29286011393439957779550802178157612057890166200204205083480959538311702269031
Short name T396
Test name
Test status
Simulation time 4863401336 ps
CPU time 142.03 seconds
Started Nov 22 01:10:22 PM PST 23
Finished Nov 22 01:12:48 PM PST 23
Peak memory 198528 kb
Host smart-eef7dc17-8168-43c3-a906-9cbb58d416ee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=29286011393439957779550802178157612057890166200204205083480959538311702269031 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 49.hmac_datapath_stress.29286011393439957779550802178157612057890166200204205083480959538311702269031
Directory /workspace/49.hmac_datapath_stress/latest

Test location /workspace/coverage/default/49.hmac_error.47159482849239404865995871651526447443276508817979101565300461775052896244359
Short name T704
Test name
Test status
Simulation time 26556692074 ps
CPU time 196.78 seconds
Started Nov 22 01:10:20 PM PST 23
Finished Nov 22 01:13:40 PM PST 23
Peak memory 198592 kb
Host smart-03df81c2-6594-41a3-95dc-7bf4f2fb928f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47159482849239404865995871651526447443276508817979101565300461775052896244359 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 49.hmac_error.47159482849239404865995871651526447443276508817979101565300461775052896244359
Directory /workspace/49.hmac_error/latest

Test location /workspace/coverage/default/49.hmac_long_msg.16797271217759142602000927192568341106950014117597548077903023601922373309081
Short name T8
Test name
Test status
Simulation time 14959266997 ps
CPU time 119.43 seconds
Started Nov 22 01:11:07 PM PST 23
Finished Nov 22 01:13:08 PM PST 23
Peak memory 198568 kb
Host smart-c60928e8-1789-4495-9624-8e64fe94765a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16797271217759142602000927192568341106950014117597548077903023601922373309081 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.hmac_long_msg.16797271217759142602000927192568341106950014117597548077903023601922373309081
Directory /workspace/49.hmac_long_msg/latest

Test location /workspace/coverage/default/49.hmac_smoke.30415590588285908129193909686194742828856515129892568061598006699762321484563
Short name T606
Test name
Test status
Simulation time 631560191 ps
CPU time 4.2 seconds
Started Nov 22 01:10:47 PM PST 23
Finished Nov 22 01:10:53 PM PST 23
Peak memory 198464 kb
Host smart-84906447-ebe0-4f6d-bea2-960995fe3a80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30415590588285908129193909686194742828856515129892568061598006699762321484563 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 49.hmac_smoke.30415590588285908129193909686194742828856515129892568061598006699762321484563
Directory /workspace/49.hmac_smoke/latest

Test location /workspace/coverage/default/49.hmac_stress_all.47870348970292464218291258431422461770064488361607325827008395360468240645519
Short name T770
Test name
Test status
Simulation time 146644856361 ps
CPU time 1153.12 seconds
Started Nov 22 01:10:20 PM PST 23
Finished Nov 22 01:29:36 PM PST 23
Peak memory 210840 kb
Host smart-62457514-21a3-4a1d-a4c3-e061db90b19e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478703489702924642182912
58431422461770064488361607325827008395360468240645519 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_stress_all.47870348970292464218291
258431422461770064488361607325827008395360468240645519
Directory /workspace/49.hmac_stress_all/latest

Test location /workspace/coverage/default/49.hmac_stress_all_with_rand_reset.91915319644327451801296002445800544833207547830966873415990674708441399099232
Short name T691
Test name
Test status
Simulation time 80460760838 ps
CPU time 678.74 seconds
Started Nov 22 01:10:35 PM PST 23
Finished Nov 22 01:21:55 PM PST 23
Peak memory 209132 kb
Host smart-bdec9b44-001f-48a8-8ea4-b7c4c190635d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=91915319644327451801296002445800544833207547830966873415990674708441399099232 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 49.hmac_stress_all_with_rand_reset.91915319644327451801296002445800544833207547830966873415990674708441399099232
Directory /workspace/49.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.hmac_test_hmac_vectors.105356565084436016870885958953805162120935221075387218497902125593203186634241
Short name T566
Test name
Test status
Simulation time 76314633 ps
CPU time 0.96 seconds
Started Nov 22 01:10:30 PM PST 23
Finished Nov 22 01:10:32 PM PST 23
Peak memory 195764 kb
Host smart-2438ea5b-281f-45a3-b482-cfc091350967
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10535656508443601687088595895380516212093522107538721
8497902125593203186634241 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_test_hmac_vectors.1053565650844360168708859589538051621
20935221075387218497902125593203186634241
Directory /workspace/49.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/49.hmac_test_sha_vectors.75272643476850334123904896570494213965742681165118248511649373985183581312965
Short name T620
Test name
Test status
Simulation time 63914107498 ps
CPU time 457.99 seconds
Started Nov 22 01:10:19 PM PST 23
Finished Nov 22 01:17:59 PM PST 23
Peak memory 198588 kb
Host smart-3478d5d4-1a59-4396-8c93-40cd78516db2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75272643476850334123904896570494213965742681165118248
511649373985183581312965 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_test_sha_vectors.7527264347685033412390489657049421396574
2681165118248511649373985183581312965
Directory /workspace/49.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/49.hmac_wipe_secret.8715783993600548235092957915381116042995445033108356735825999577431545715569
Short name T202
Test name
Test status
Simulation time 8070750677 ps
CPU time 62.33 seconds
Started Nov 22 01:10:22 PM PST 23
Finished Nov 22 01:11:28 PM PST 23
Peak memory 198596 kb
Host smart-c93e238e-f928-433d-896e-26d875af0851
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8715783993600548235092957915381116042995445033108356735825999577431545715569 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 49.hmac_wipe_secret.8715783993600548235092957915381116042995445033108356735825999577431545715569
Directory /workspace/49.hmac_wipe_secret/latest

Test location /workspace/coverage/default/5.hmac_alert_test.70167812996912863692034001754985434726841449514947290131847124389682750087602
Short name T605
Test name
Test status
Simulation time 18011528 ps
CPU time 0.59 seconds
Started Nov 22 01:08:59 PM PST 23
Finished Nov 22 01:09:09 PM PST 23
Peak memory 192808 kb
Host smart-2f1a0af1-596a-43f8-b24a-dde4d36ff8a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70167812996912863692034001754985434726841449514947290131847124389682750087602 -assert nopostpr
oc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 5.hmac_alert_test.70167812996912863692034001754985434726841449514947290131847124389682750087602
Directory /workspace/5.hmac_alert_test/latest

Test location /workspace/coverage/default/5.hmac_back_pressure.95805849916208574890019748301276939380235226954216799901433405441743906807367
Short name T696
Test name
Test status
Simulation time 2592169506 ps
CPU time 47.06 seconds
Started Nov 22 01:09:01 PM PST 23
Finished Nov 22 01:09:58 PM PST 23
Peak memory 231372 kb
Host smart-d52e59cd-67aa-4456-affa-53665001add4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=95805849916208574890019748301276939380235226954216799901433405441743906807367 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 5.hmac_back_pressure.95805849916208574890019748301276939380235226954216799901433405441743906807367
Directory /workspace/5.hmac_back_pressure/latest

Test location /workspace/coverage/default/5.hmac_burst_wr.44447655602031066151664666834859519013856785223879663073300887192483197255538
Short name T595
Test name
Test status
Simulation time 4504100639 ps
CPU time 37.14 seconds
Started Nov 22 01:09:06 PM PST 23
Finished Nov 22 01:09:52 PM PST 23
Peak memory 198484 kb
Host smart-f6694d90-3e03-47c7-bd75-bc50d6d1804c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44447655602031066151664666834859519013856785223879663073300887192483197255538 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.hmac_burst_wr.44447655602031066151664666834859519013856785223879663073300887192483197255538
Directory /workspace/5.hmac_burst_wr/latest

Test location /workspace/coverage/default/5.hmac_datapath_stress.26107434782798989915400179669719708032471931480996028596118775102589471287766
Short name T673
Test name
Test status
Simulation time 4863401336 ps
CPU time 137.04 seconds
Started Nov 22 01:09:02 PM PST 23
Finished Nov 22 01:11:28 PM PST 23
Peak memory 198560 kb
Host smart-4b7cf7e1-9890-4a96-8b0f-cc7f891cdb48
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=26107434782798989915400179669719708032471931480996028596118775102589471287766 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 5.hmac_datapath_stress.26107434782798989915400179669719708032471931480996028596118775102589471287766
Directory /workspace/5.hmac_datapath_stress/latest

Test location /workspace/coverage/default/5.hmac_error.16912149405375013751502762975831819933035473635820203151653887324657264635031
Short name T198
Test name
Test status
Simulation time 26556692074 ps
CPU time 197.37 seconds
Started Nov 22 01:09:16 PM PST 23
Finished Nov 22 01:12:35 PM PST 23
Peak memory 198472 kb
Host smart-4e4b0294-3f7d-437d-a86e-6e7f62c3a30e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16912149405375013751502762975831819933035473635820203151653887324657264635031 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 5.hmac_error.16912149405375013751502762975831819933035473635820203151653887324657264635031
Directory /workspace/5.hmac_error/latest

Test location /workspace/coverage/default/5.hmac_long_msg.7494369091633749435299231126535214597281536053317877638673005728793313478337
Short name T773
Test name
Test status
Simulation time 14959266997 ps
CPU time 120.48 seconds
Started Nov 22 01:09:02 PM PST 23
Finished Nov 22 01:11:12 PM PST 23
Peak memory 198548 kb
Host smart-806f502c-8454-4e41-b3d6-4864db9f3ca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7494369091633749435299231126535214597281536053317877638673005728793313478337 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 5.hmac_long_msg.7494369091633749435299231126535214597281536053317877638673005728793313478337
Directory /workspace/5.hmac_long_msg/latest

Test location /workspace/coverage/default/5.hmac_smoke.97488060874784902640494715680040593775342915647722734506890175302755584219365
Short name T565
Test name
Test status
Simulation time 631560191 ps
CPU time 4.34 seconds
Started Nov 22 01:09:03 PM PST 23
Finished Nov 22 01:09:16 PM PST 23
Peak memory 198500 kb
Host smart-c7bbd31f-d9e8-4c6f-9193-392a07128cfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97488060874784902640494715680040593775342915647722734506890175302755584219365 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 5.hmac_smoke.97488060874784902640494715680040593775342915647722734506890175302755584219365
Directory /workspace/5.hmac_smoke/latest

Test location /workspace/coverage/default/5.hmac_stress_all.115466650433249437947998728977021942351396373358525351531956734814506185239879
Short name T95
Test name
Test status
Simulation time 146644856361 ps
CPU time 1141.63 seconds
Started Nov 22 01:09:01 PM PST 23
Finished Nov 22 01:28:13 PM PST 23
Peak memory 210872 kb
Host smart-4a98a5ae-3d2e-466c-b514-9f548f6cd204
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115466650433249437947998
728977021942351396373358525351531956734814506185239879 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all.11546665043324943794799
8728977021942351396373358525351531956734814506185239879
Directory /workspace/5.hmac_stress_all/latest

Test location /workspace/coverage/default/5.hmac_stress_all_with_rand_reset.2119785381326098915695875536474947047077409158679274733493746239185905045541
Short name T468
Test name
Test status
Simulation time 80460760838 ps
CPU time 694.22 seconds
Started Nov 22 01:09:04 PM PST 23
Finished Nov 22 01:20:46 PM PST 23
Peak memory 209296 kb
Host smart-be3ea446-c57a-4a2e-a3f8-a798341e0899
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2119785381326098915695875536474947047077409158679274733493746239185905045541 -assert nopostproc +UVM_TEST
NAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 5.hmac_stress_all_with_rand_reset.2119785381326098915695875536474947047077409158679274733493746239185905045541
Directory /workspace/5.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.hmac_test_hmac_vectors.32989587857237825158680111022589606040437964451985792427043161072996511335921
Short name T244
Test name
Test status
Simulation time 76314633 ps
CPU time 0.9 seconds
Started Nov 22 01:09:01 PM PST 23
Finished Nov 22 01:09:12 PM PST 23
Peak memory 195788 kb
Host smart-541ea9e8-279a-44a9-863a-17a823fe3de0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32989587857237825158680111022589606040437964451985792
427043161072996511335921 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_test_hmac_vectors.329895878572378251586801110225896060404
37964451985792427043161072996511335921
Directory /workspace/5.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/5.hmac_test_sha_vectors.52735750017264627275886670428792181706909519903846557578496523778879350286360
Short name T310
Test name
Test status
Simulation time 63914107498 ps
CPU time 465.39 seconds
Started Nov 22 01:09:02 PM PST 23
Finished Nov 22 01:16:57 PM PST 23
Peak memory 198568 kb
Host smart-dd63004e-06cc-43c6-90c6-58f530e86f6b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52735750017264627275886670428792181706909519903846557
578496523778879350286360 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_test_sha_vectors.52735750017264627275886670428792181706909
519903846557578496523778879350286360
Directory /workspace/5.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/5.hmac_wipe_secret.58282092217968640742771566793397867814048054534031966290347141434895282474135
Short name T336
Test name
Test status
Simulation time 8070750677 ps
CPU time 60.03 seconds
Started Nov 22 01:09:04 PM PST 23
Finished Nov 22 01:10:12 PM PST 23
Peak memory 198588 kb
Host smart-bc79c849-2fe4-4173-8b32-5c41b5b3e461
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58282092217968640742771566793397867814048054534031966290347141434895282474135 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 5.hmac_wipe_secret.58282092217968640742771566793397867814048054534031966290347141434895282474135
Directory /workspace/5.hmac_wipe_secret/latest

Test location /workspace/coverage/default/50.hmac_stress_all_with_rand_reset.34628574015808944613953242129381329289932376840108529218465089154900500296886
Short name T593
Test name
Test status
Simulation time 80460760838 ps
CPU time 692.48 seconds
Started Nov 22 01:10:25 PM PST 23
Finished Nov 22 01:22:01 PM PST 23
Peak memory 209364 kb
Host smart-1e2b8d82-6c4c-42d6-93aa-382dacd16f52
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=34628574015808944613953242129381329289932376840108529218465089154900500296886 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 50.hmac_stress_all_with_rand_reset.34628574015808944613953242129381329289932376840108529218465089154900500296886
Directory /workspace/50.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/51.hmac_stress_all_with_rand_reset.76750896491341484788013281305240345305389427093393647688831434367479083536777
Short name T835
Test name
Test status
Simulation time 80460760838 ps
CPU time 716.61 seconds
Started Nov 22 01:10:22 PM PST 23
Finished Nov 22 01:22:24 PM PST 23
Peak memory 209380 kb
Host smart-6c07d139-f850-467a-bb7a-bbb6e8ff5a0d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=76750896491341484788013281305240345305389427093393647688831434367479083536777 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 51.hmac_stress_all_with_rand_reset.76750896491341484788013281305240345305389427093393647688831434367479083536777
Directory /workspace/51.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/52.hmac_stress_all_with_rand_reset.1114016636485112496940191474280699217165340122254091819790589510767593486481
Short name T334
Test name
Test status
Simulation time 80460760838 ps
CPU time 701.6 seconds
Started Nov 22 01:10:28 PM PST 23
Finished Nov 22 01:22:12 PM PST 23
Peak memory 210344 kb
Host smart-ca199793-2412-4946-92a0-6fb28219a0be
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1114016636485112496940191474280699217165340122254091819790589510767593486481 -assert nopostproc +UVM_TEST
NAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 52.hmac_stress_all_with_rand_reset.1114016636485112496940191474280699217165340122254091819790589510767593486481
Directory /workspace/52.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/53.hmac_stress_all_with_rand_reset.50685515067642796707758700682905191205679180472043102932097266386501104934718
Short name T735
Test name
Test status
Simulation time 80460760838 ps
CPU time 722.88 seconds
Started Nov 22 01:10:26 PM PST 23
Finished Nov 22 01:22:32 PM PST 23
Peak memory 209280 kb
Host smart-c528643c-7d38-4609-ac11-a0045591f8ce
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=50685515067642796707758700682905191205679180472043102932097266386501104934718 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 53.hmac_stress_all_with_rand_reset.50685515067642796707758700682905191205679180472043102932097266386501104934718
Directory /workspace/53.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/54.hmac_stress_all_with_rand_reset.80021684091456033172788729583364395450186366708914942127305338431844043560822
Short name T462
Test name
Test status
Simulation time 80460760838 ps
CPU time 703.64 seconds
Started Nov 22 01:10:30 PM PST 23
Finished Nov 22 01:22:15 PM PST 23
Peak memory 209336 kb
Host smart-65e820ff-eb1d-4e29-9682-8e14b4c003fe
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=80021684091456033172788729583364395450186366708914942127305338431844043560822 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 54.hmac_stress_all_with_rand_reset.80021684091456033172788729583364395450186366708914942127305338431844043560822
Directory /workspace/54.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/55.hmac_stress_all_with_rand_reset.97869414332760963576821351547303333680203866276349817645563697569092896161334
Short name T189
Test name
Test status
Simulation time 80460760838 ps
CPU time 746.03 seconds
Started Nov 22 01:10:20 PM PST 23
Finished Nov 22 01:22:50 PM PST 23
Peak memory 209364 kb
Host smart-12e576fc-6b98-462d-8b98-8a66106db49e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=97869414332760963576821351547303333680203866276349817645563697569092896161334 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 55.hmac_stress_all_with_rand_reset.97869414332760963576821351547303333680203866276349817645563697569092896161334
Directory /workspace/55.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/56.hmac_stress_all_with_rand_reset.35173680710290968246788818649338005364044394402968706272672626279573484708536
Short name T427
Test name
Test status
Simulation time 80460760838 ps
CPU time 702.55 seconds
Started Nov 22 01:10:26 PM PST 23
Finished Nov 22 01:22:12 PM PST 23
Peak memory 209304 kb
Host smart-7e23962a-f870-4b0c-83b9-4d666f7a15e4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=35173680710290968246788818649338005364044394402968706272672626279573484708536 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 56.hmac_stress_all_with_rand_reset.35173680710290968246788818649338005364044394402968706272672626279573484708536
Directory /workspace/56.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/57.hmac_stress_all_with_rand_reset.53112426528428675778222151785494080241103395260931331615560112128466691229328
Short name T431
Test name
Test status
Simulation time 80460760838 ps
CPU time 690.39 seconds
Started Nov 22 01:10:21 PM PST 23
Finished Nov 22 01:21:56 PM PST 23
Peak memory 209284 kb
Host smart-afb74e0e-70bd-496a-94cf-fefabd4ed542
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=53112426528428675778222151785494080241103395260931331615560112128466691229328 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 57.hmac_stress_all_with_rand_reset.53112426528428675778222151785494080241103395260931331615560112128466691229328
Directory /workspace/57.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/58.hmac_stress_all_with_rand_reset.60505866659178617628333129414270604727233111332820554893216113072727252303623
Short name T871
Test name
Test status
Simulation time 80460760838 ps
CPU time 710.52 seconds
Started Nov 22 01:10:20 PM PST 23
Finished Nov 22 01:22:14 PM PST 23
Peak memory 209364 kb
Host smart-466a55bf-8e62-407a-bd1d-b68d9a79ea18
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=60505866659178617628333129414270604727233111332820554893216113072727252303623 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 58.hmac_stress_all_with_rand_reset.60505866659178617628333129414270604727233111332820554893216113072727252303623
Directory /workspace/58.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/59.hmac_stress_all_with_rand_reset.60732001837249717676132840196503840888679874475470051559530723811466754292209
Short name T380
Test name
Test status
Simulation time 80460760838 ps
CPU time 666.77 seconds
Started Nov 22 01:10:34 PM PST 23
Finished Nov 22 01:21:43 PM PST 23
Peak memory 209132 kb
Host smart-c24b55ae-665b-4854-9046-9d41ef0f4a0a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=60732001837249717676132840196503840888679874475470051559530723811466754292209 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 59.hmac_stress_all_with_rand_reset.60732001837249717676132840196503840888679874475470051559530723811466754292209
Directory /workspace/59.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.hmac_alert_test.72175907899957859260094076759197585221771211137293417506167265765345291786111
Short name T477
Test name
Test status
Simulation time 18011528 ps
CPU time 0.56 seconds
Started Nov 22 01:09:00 PM PST 23
Finished Nov 22 01:09:11 PM PST 23
Peak memory 192828 kb
Host smart-ad7792b4-fa8b-4b0b-9c71-2683164a25b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72175907899957859260094076759197585221771211137293417506167265765345291786111 -assert nopostpr
oc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 6.hmac_alert_test.72175907899957859260094076759197585221771211137293417506167265765345291786111
Directory /workspace/6.hmac_alert_test/latest

Test location /workspace/coverage/default/6.hmac_back_pressure.5016687346034974554927930557232029663464511453655624786350330361589642539606
Short name T756
Test name
Test status
Simulation time 2592169506 ps
CPU time 50.63 seconds
Started Nov 22 01:09:06 PM PST 23
Finished Nov 22 01:10:04 PM PST 23
Peak memory 231352 kb
Host smart-95bc8aaf-58f3-42c8-93f9-39564ab937e4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=5016687346034974554927930557232029663464511453655624786350330361589642539606 -assert nopostproc +UVM_TEST
NAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 6.hmac_back_pressure.5016687346034974554927930557232029663464511453655624786350330361589642539606
Directory /workspace/6.hmac_back_pressure/latest

Test location /workspace/coverage/default/6.hmac_burst_wr.111905861463327876947538614207643842058628620165287795663680216964928997592252
Short name T422
Test name
Test status
Simulation time 4504100639 ps
CPU time 36.74 seconds
Started Nov 22 01:09:17 PM PST 23
Finished Nov 22 01:09:55 PM PST 23
Peak memory 198440 kb
Host smart-93503523-b8dd-43f9-ada5-a629cfd1228d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111905861463327876947538614207643842058628620165287795663680216964928997592252 -assert nopostproc +UVM_TESTNAME=hmac_bas
e_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 6.hmac_burst_wr.111905861463327876947538614207643842058628620165287795663680216964928997592252
Directory /workspace/6.hmac_burst_wr/latest

Test location /workspace/coverage/default/6.hmac_datapath_stress.42809285096747207046371003412343069760506872862727829385173724102562026944056
Short name T36
Test name
Test status
Simulation time 4863401336 ps
CPU time 147 seconds
Started Nov 22 01:09:01 PM PST 23
Finished Nov 22 01:11:38 PM PST 23
Peak memory 198608 kb
Host smart-1b1370b5-cc0b-42cb-9a00-d5e5d484af2a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=42809285096747207046371003412343069760506872862727829385173724102562026944056 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 6.hmac_datapath_stress.42809285096747207046371003412343069760506872862727829385173724102562026944056
Directory /workspace/6.hmac_datapath_stress/latest

Test location /workspace/coverage/default/6.hmac_error.41223825527688720963666687069380637777154842834040359093571558688493062648525
Short name T193
Test name
Test status
Simulation time 26556692074 ps
CPU time 191.76 seconds
Started Nov 22 01:09:01 PM PST 23
Finished Nov 22 01:12:23 PM PST 23
Peak memory 198440 kb
Host smart-0599a813-ade5-4a87-878e-242315805167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41223825527688720963666687069380637777154842834040359093571558688493062648525 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 6.hmac_error.41223825527688720963666687069380637777154842834040359093571558688493062648525
Directory /workspace/6.hmac_error/latest

Test location /workspace/coverage/default/6.hmac_long_msg.58657948053087571197926280756339075058938610000660226006037333713946255636560
Short name T300
Test name
Test status
Simulation time 14959266997 ps
CPU time 116.56 seconds
Started Nov 22 01:09:02 PM PST 23
Finished Nov 22 01:11:08 PM PST 23
Peak memory 198548 kb
Host smart-cbeee314-e90f-40ae-b09b-beeff34e2155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58657948053087571197926280756339075058938610000660226006037333713946255636560 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.hmac_long_msg.58657948053087571197926280756339075058938610000660226006037333713946255636560
Directory /workspace/6.hmac_long_msg/latest

Test location /workspace/coverage/default/6.hmac_smoke.38904603770344419767252904945844867526636498431329598618225018980427155269447
Short name T458
Test name
Test status
Simulation time 631560191 ps
CPU time 4.06 seconds
Started Nov 22 01:09:01 PM PST 23
Finished Nov 22 01:09:15 PM PST 23
Peak memory 198376 kb
Host smart-7633f658-c2e4-415b-b221-2d2150729b7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38904603770344419767252904945844867526636498431329598618225018980427155269447 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 6.hmac_smoke.38904603770344419767252904945844867526636498431329598618225018980427155269447
Directory /workspace/6.hmac_smoke/latest

Test location /workspace/coverage/default/6.hmac_stress_all.66826026590658095091899773808193422979083408093518321283634237271813438463265
Short name T721
Test name
Test status
Simulation time 146644856361 ps
CPU time 1131.66 seconds
Started Nov 22 01:09:05 PM PST 23
Finished Nov 22 01:28:04 PM PST 23
Peak memory 210852 kb
Host smart-9a41e0f0-c460-423a-b373-dec659267f45
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668260265906580950918997
73808193422979083408093518321283634237271813438463265 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all.668260265906580950918997
73808193422979083408093518321283634237271813438463265
Directory /workspace/6.hmac_stress_all/latest

Test location /workspace/coverage/default/6.hmac_stress_all_with_rand_reset.102660633856391511033245943850700737239500866111480013322187391092625808805290
Short name T519
Test name
Test status
Simulation time 80460760838 ps
CPU time 702.12 seconds
Started Nov 22 01:09:01 PM PST 23
Finished Nov 22 01:20:54 PM PST 23
Peak memory 209336 kb
Host smart-d1b409a3-628d-4420-89ea-afd7931413ca
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=102660633856391511033245943850700737239500866111480013322187391092625808805290 -assert nopostproc +UVM_TE
STNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 6.hmac_stress_all_with_rand_reset.102660633856391511033245943850700737239500866111480013322187391092625808805290
Directory /workspace/6.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.hmac_test_hmac_vectors.93777834175690192834957523451673512763133758121901306307186083043393162248525
Short name T399
Test name
Test status
Simulation time 76314633 ps
CPU time 0.91 seconds
Started Nov 22 01:09:02 PM PST 23
Finished Nov 22 01:09:12 PM PST 23
Peak memory 195764 kb
Host smart-444bf432-0248-4667-9922-c6211a6868cc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93777834175690192834957523451673512763133758121901306
307186083043393162248525 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_test_hmac_vectors.937778341756901928349575234516735127631
33758121901306307186083043393162248525
Directory /workspace/6.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/6.hmac_test_sha_vectors.47566200819789722894054846989064941271884262747542144445769956907238389067305
Short name T790
Test name
Test status
Simulation time 63914107498 ps
CPU time 470.68 seconds
Started Nov 22 01:09:02 PM PST 23
Finished Nov 22 01:17:02 PM PST 23
Peak memory 198572 kb
Host smart-f1debe0c-5fd9-400c-b61d-201baf04ab45
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47566200819789722894054846989064941271884262747542144
445769956907238389067305 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_test_sha_vectors.47566200819789722894054846989064941271884
262747542144445769956907238389067305
Directory /workspace/6.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/6.hmac_wipe_secret.20292673890514640582222456658970215564615513841559314493792749284642595372616
Short name T521
Test name
Test status
Simulation time 8070750677 ps
CPU time 64.91 seconds
Started Nov 22 01:09:00 PM PST 23
Finished Nov 22 01:10:15 PM PST 23
Peak memory 198600 kb
Host smart-aaa18d5f-60e4-4cf4-a9f7-9b0b297e2741
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20292673890514640582222456658970215564615513841559314493792749284642595372616 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 6.hmac_wipe_secret.20292673890514640582222456658970215564615513841559314493792749284642595372616
Directory /workspace/6.hmac_wipe_secret/latest

Test location /workspace/coverage/default/60.hmac_stress_all_with_rand_reset.58260435845483587082256745152934478835509043697983880986171408518298588752104
Short name T455
Test name
Test status
Simulation time 80460760838 ps
CPU time 689.55 seconds
Started Nov 22 01:10:35 PM PST 23
Finished Nov 22 01:22:06 PM PST 23
Peak memory 209132 kb
Host smart-b0184a29-801e-4acf-96b5-b1690130482b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=58260435845483587082256745152934478835509043697983880986171408518298588752104 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 60.hmac_stress_all_with_rand_reset.58260435845483587082256745152934478835509043697983880986171408518298588752104
Directory /workspace/60.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/61.hmac_stress_all_with_rand_reset.77753245208548570941234897064799249332891610606781996608114434180659036530318
Short name T603
Test name
Test status
Simulation time 80460760838 ps
CPU time 681.31 seconds
Started Nov 22 01:10:22 PM PST 23
Finished Nov 22 01:21:48 PM PST 23
Peak memory 209180 kb
Host smart-7b2ca52d-6c52-468e-8df8-bf6658b437a4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=77753245208548570941234897064799249332891610606781996608114434180659036530318 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 61.hmac_stress_all_with_rand_reset.77753245208548570941234897064799249332891610606781996608114434180659036530318
Directory /workspace/61.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/62.hmac_stress_all_with_rand_reset.44816294679163696005649400837504840230394217541496171027240521610918210365179
Short name T232
Test name
Test status
Simulation time 80460760838 ps
CPU time 725.79 seconds
Started Nov 22 01:10:25 PM PST 23
Finished Nov 22 01:22:34 PM PST 23
Peak memory 209232 kb
Host smart-b79b58b1-88e0-481a-ba13-800eaa4f4bbc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=44816294679163696005649400837504840230394217541496171027240521610918210365179 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 62.hmac_stress_all_with_rand_reset.44816294679163696005649400837504840230394217541496171027240521610918210365179
Directory /workspace/62.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/63.hmac_stress_all_with_rand_reset.90191807066699092206046074510643137846878768561971912412042169818340389439243
Short name T547
Test name
Test status
Simulation time 80460760838 ps
CPU time 663.71 seconds
Started Nov 22 01:10:34 PM PST 23
Finished Nov 22 01:21:39 PM PST 23
Peak memory 209132 kb
Host smart-9e2bbc59-74b4-485d-afb3-abbf62bc18dc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=90191807066699092206046074510643137846878768561971912412042169818340389439243 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 63.hmac_stress_all_with_rand_reset.90191807066699092206046074510643137846878768561971912412042169818340389439243
Directory /workspace/63.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/64.hmac_stress_all_with_rand_reset.55707874402733531582184450246215650282286039410807860158806820110799845640929
Short name T841
Test name
Test status
Simulation time 80460760838 ps
CPU time 716.63 seconds
Started Nov 22 01:10:30 PM PST 23
Finished Nov 22 01:22:28 PM PST 23
Peak memory 209336 kb
Host smart-4509c032-a95a-4d29-812b-baecfa54f48f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=55707874402733531582184450246215650282286039410807860158806820110799845640929 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 64.hmac_stress_all_with_rand_reset.55707874402733531582184450246215650282286039410807860158806820110799845640929
Directory /workspace/64.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/65.hmac_stress_all_with_rand_reset.102855550175131456105036140886002195596691898693919256771182938405341461413428
Short name T619
Test name
Test status
Simulation time 80460760838 ps
CPU time 682.67 seconds
Started Nov 22 01:10:33 PM PST 23
Finished Nov 22 01:21:57 PM PST 23
Peak memory 209140 kb
Host smart-892705c6-74bf-4bf4-b60c-1e6da3d6cd59
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=102855550175131456105036140886002195596691898693919256771182938405341461413428 -assert nopostproc +UVM_TE
STNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 65.hmac_stress_all_with_rand_reset.102855550175131456105036140886002195596691898693919256771182938405341461413428
Directory /workspace/65.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/66.hmac_stress_all_with_rand_reset.66852035809248356585815102975749031017905334602698240889052902346349185843595
Short name T724
Test name
Test status
Simulation time 80460760838 ps
CPU time 663.22 seconds
Started Nov 22 01:10:36 PM PST 23
Finished Nov 22 01:21:41 PM PST 23
Peak memory 209132 kb
Host smart-d6b485d3-e3e0-4683-8910-5a460c7e663e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=66852035809248356585815102975749031017905334602698240889052902346349185843595 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 66.hmac_stress_all_with_rand_reset.66852035809248356585815102975749031017905334602698240889052902346349185843595
Directory /workspace/66.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/67.hmac_stress_all_with_rand_reset.45821170602974778389496722413707265317175092580351424776281286934378580329746
Short name T587
Test name
Test status
Simulation time 80460760838 ps
CPU time 715.09 seconds
Started Nov 22 01:10:25 PM PST 23
Finished Nov 22 01:22:24 PM PST 23
Peak memory 209232 kb
Host smart-deb6c1dd-3c4b-4a92-a8e9-9f5b2aad9ec4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=45821170602974778389496722413707265317175092580351424776281286934378580329746 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 67.hmac_stress_all_with_rand_reset.45821170602974778389496722413707265317175092580351424776281286934378580329746
Directory /workspace/67.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/68.hmac_stress_all_with_rand_reset.66987583525677632963427351180022545264631576514788982343956858648527135775534
Short name T873
Test name
Test status
Simulation time 80460760838 ps
CPU time 704.8 seconds
Started Nov 22 01:10:39 PM PST 23
Finished Nov 22 01:22:25 PM PST 23
Peak memory 209252 kb
Host smart-4a14b32d-85ac-48a3-97ff-88a0cf521373
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=66987583525677632963427351180022545264631576514788982343956858648527135775534 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 68.hmac_stress_all_with_rand_reset.66987583525677632963427351180022545264631576514788982343956858648527135775534
Directory /workspace/68.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/69.hmac_stress_all_with_rand_reset.84555757874992508957442062951774849659547762210516635879412930099593246662247
Short name T257
Test name
Test status
Simulation time 80460760838 ps
CPU time 695.38 seconds
Started Nov 22 01:10:27 PM PST 23
Finished Nov 22 01:22:05 PM PST 23
Peak memory 209276 kb
Host smart-3884b11e-fc4f-4ea1-966c-98e06a1c5d76
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=84555757874992508957442062951774849659547762210516635879412930099593246662247 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 69.hmac_stress_all_with_rand_reset.84555757874992508957442062951774849659547762210516635879412930099593246662247
Directory /workspace/69.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.hmac_alert_test.56953665714105431823954546128291901620252538673993932299379578279809849674951
Short name T274
Test name
Test status
Simulation time 18011528 ps
CPU time 0.62 seconds
Started Nov 22 01:09:31 PM PST 23
Finished Nov 22 01:09:35 PM PST 23
Peak memory 191056 kb
Host smart-3033a002-10be-49b2-9315-384beaf38677
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56953665714105431823954546128291901620252538673993932299379578279809849674951 -assert nopostpr
oc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 7.hmac_alert_test.56953665714105431823954546128291901620252538673993932299379578279809849674951
Directory /workspace/7.hmac_alert_test/latest

Test location /workspace/coverage/default/7.hmac_back_pressure.78436018066819807543655038774745394910395671479444826234557639125423132615221
Short name T571
Test name
Test status
Simulation time 2592169506 ps
CPU time 48.57 seconds
Started Nov 22 01:09:06 PM PST 23
Finished Nov 22 01:10:03 PM PST 23
Peak memory 231352 kb
Host smart-1898f3cc-f22e-4d4c-bf06-2c958b59e91d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=78436018066819807543655038774745394910395671479444826234557639125423132615221 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 7.hmac_back_pressure.78436018066819807543655038774745394910395671479444826234557639125423132615221
Directory /workspace/7.hmac_back_pressure/latest

Test location /workspace/coverage/default/7.hmac_burst_wr.87009260938501135928968184013184633979496964270835098900431183102170206098140
Short name T634
Test name
Test status
Simulation time 4504100639 ps
CPU time 37.15 seconds
Started Nov 22 01:09:02 PM PST 23
Finished Nov 22 01:09:49 PM PST 23
Peak memory 198528 kb
Host smart-b0b6c45d-3370-4a1c-8cd3-92a77ee726bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87009260938501135928968184013184633979496964270835098900431183102170206098140 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.hmac_burst_wr.87009260938501135928968184013184633979496964270835098900431183102170206098140
Directory /workspace/7.hmac_burst_wr/latest

Test location /workspace/coverage/default/7.hmac_datapath_stress.96365165415530954114175206580686020626533567766301176009829095575444288099781
Short name T514
Test name
Test status
Simulation time 4863401336 ps
CPU time 145.15 seconds
Started Nov 22 01:09:01 PM PST 23
Finished Nov 22 01:11:37 PM PST 23
Peak memory 198588 kb
Host smart-ae696ba0-1565-4dab-9650-1747f91b7f15
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=96365165415530954114175206580686020626533567766301176009829095575444288099781 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 7.hmac_datapath_stress.96365165415530954114175206580686020626533567766301176009829095575444288099781
Directory /workspace/7.hmac_datapath_stress/latest

Test location /workspace/coverage/default/7.hmac_error.63263009098962652029015406098235724223020074064458728022549583728948789139149
Short name T810
Test name
Test status
Simulation time 26556692074 ps
CPU time 196.64 seconds
Started Nov 22 01:09:00 PM PST 23
Finished Nov 22 01:12:26 PM PST 23
Peak memory 198588 kb
Host smart-9affc716-540f-484c-ab28-fd27839330bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63263009098962652029015406098235724223020074064458728022549583728948789139149 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 7.hmac_error.63263009098962652029015406098235724223020074064458728022549583728948789139149
Directory /workspace/7.hmac_error/latest

Test location /workspace/coverage/default/7.hmac_long_msg.1062079787232286525676029024649048924278403217319691142073695635968030697279
Short name T313
Test name
Test status
Simulation time 14959266997 ps
CPU time 116.9 seconds
Started Nov 22 01:08:59 PM PST 23
Finished Nov 22 01:11:06 PM PST 23
Peak memory 198540 kb
Host smart-25f7f278-d5bf-4393-9442-691390b45969
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1062079787232286525676029024649048924278403217319691142073695635968030697279 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 7.hmac_long_msg.1062079787232286525676029024649048924278403217319691142073695635968030697279
Directory /workspace/7.hmac_long_msg/latest

Test location /workspace/coverage/default/7.hmac_smoke.37949611309712832811143691131388077348110564539337231327866101593079592598635
Short name T860
Test name
Test status
Simulation time 631560191 ps
CPU time 4.1 seconds
Started Nov 22 01:09:01 PM PST 23
Finished Nov 22 01:09:15 PM PST 23
Peak memory 198432 kb
Host smart-5c9efd39-1ab9-48e0-b8bb-bec6e8e99562
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37949611309712832811143691131388077348110564539337231327866101593079592598635 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 7.hmac_smoke.37949611309712832811143691131388077348110564539337231327866101593079592598635
Directory /workspace/7.hmac_smoke/latest

Test location /workspace/coverage/default/7.hmac_stress_all.96427775839019747161528855283653880798167475609761470605826570850099437273418
Short name T577
Test name
Test status
Simulation time 146644856361 ps
CPU time 1092.34 seconds
Started Nov 22 01:09:30 PM PST 23
Finished Nov 22 01:27:46 PM PST 23
Peak memory 209124 kb
Host smart-1f53b27d-0d93-4ccd-843d-712360c80d7e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964277758390197471615288
55283653880798167475609761470605826570850099437273418 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all.964277758390197471615288
55283653880798167475609761470605826570850099437273418
Directory /workspace/7.hmac_stress_all/latest

Test location /workspace/coverage/default/7.hmac_stress_all_with_rand_reset.65359551610101846296338311473174572784989487372836338337913376968907325299589
Short name T486
Test name
Test status
Simulation time 80460760838 ps
CPU time 726.85 seconds
Started Nov 22 01:09:09 PM PST 23
Finished Nov 22 01:21:23 PM PST 23
Peak memory 210252 kb
Host smart-80fc0177-dd12-45d2-bbec-eb9def7fa143
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=65359551610101846296338311473174572784989487372836338337913376968907325299589 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 7.hmac_stress_all_with_rand_reset.65359551610101846296338311473174572784989487372836338337913376968907325299589
Directory /workspace/7.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.hmac_test_hmac_vectors.21459346825209396052604836817109708216818108729781240447423001224199490897654
Short name T674
Test name
Test status
Simulation time 76314633 ps
CPU time 0.99 seconds
Started Nov 22 01:09:31 PM PST 23
Finished Nov 22 01:09:35 PM PST 23
Peak memory 193936 kb
Host smart-3bbbc57c-7800-4da8-b00e-7e863442875c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21459346825209396052604836817109708216818108729781240
447423001224199490897654 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_test_hmac_vectors.214593468252093960526048368171097082168
18108729781240447423001224199490897654
Directory /workspace/7.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/7.hmac_test_sha_vectors.16478279466196505700691232597865402694205133483992479996999047553130684206789
Short name T610
Test name
Test status
Simulation time 63914107498 ps
CPU time 443.55 seconds
Started Nov 22 01:09:02 PM PST 23
Finished Nov 22 01:16:35 PM PST 23
Peak memory 198560 kb
Host smart-91935feb-0973-4f51-8f7e-dab5d2bf3991
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16478279466196505700691232597865402694205133483992479
996999047553130684206789 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_test_sha_vectors.16478279466196505700691232597865402694205
133483992479996999047553130684206789
Directory /workspace/7.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/7.hmac_wipe_secret.74886935356918936964428063473646037806057208011921471542872961221058581569801
Short name T311
Test name
Test status
Simulation time 8070750677 ps
CPU time 61.87 seconds
Started Nov 22 01:09:03 PM PST 23
Finished Nov 22 01:10:13 PM PST 23
Peak memory 198592 kb
Host smart-69b014cb-0189-4038-9ed6-6a6f14f2ffd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74886935356918936964428063473646037806057208011921471542872961221058581569801 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 7.hmac_wipe_secret.74886935356918936964428063473646037806057208011921471542872961221058581569801
Directory /workspace/7.hmac_wipe_secret/latest

Test location /workspace/coverage/default/70.hmac_stress_all_with_rand_reset.31073392086577475120604030184214605292813055191604986939982540578229032719248
Short name T662
Test name
Test status
Simulation time 80460760838 ps
CPU time 695.62 seconds
Started Nov 22 01:10:34 PM PST 23
Finished Nov 22 01:22:11 PM PST 23
Peak memory 209180 kb
Host smart-50a5c8cc-d1ba-47dd-95ec-117af50d123a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=31073392086577475120604030184214605292813055191604986939982540578229032719248 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 70.hmac_stress_all_with_rand_reset.31073392086577475120604030184214605292813055191604986939982540578229032719248
Directory /workspace/70.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/71.hmac_stress_all_with_rand_reset.53591859020954172476710925895300604922618587540926653087128387454252859598500
Short name T186
Test name
Test status
Simulation time 80460760838 ps
CPU time 704.45 seconds
Started Nov 22 01:10:24 PM PST 23
Finished Nov 22 01:22:13 PM PST 23
Peak memory 209328 kb
Host smart-2bf8ec25-3e58-4688-ae20-c1d3a046245c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=53591859020954172476710925895300604922618587540926653087128387454252859598500 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 71.hmac_stress_all_with_rand_reset.53591859020954172476710925895300604922618587540926653087128387454252859598500
Directory /workspace/71.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/72.hmac_stress_all_with_rand_reset.1263555062136387710421478238562669868343923191304163614376000575700568109210
Short name T480
Test name
Test status
Simulation time 80460760838 ps
CPU time 707.95 seconds
Started Nov 22 01:10:22 PM PST 23
Finished Nov 22 01:22:15 PM PST 23
Peak memory 210324 kb
Host smart-af64369b-3d84-4325-ac80-c9670c2b8253
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1263555062136387710421478238562669868343923191304163614376000575700568109210 -assert nopostproc +UVM_TEST
NAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 72.hmac_stress_all_with_rand_reset.1263555062136387710421478238562669868343923191304163614376000575700568109210
Directory /workspace/72.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/73.hmac_stress_all_with_rand_reset.40852759512008803533422392488069216814285361810597476886711862479381503765655
Short name T298
Test name
Test status
Simulation time 80460760838 ps
CPU time 709 seconds
Started Nov 22 01:10:22 PM PST 23
Finished Nov 22 01:22:15 PM PST 23
Peak memory 209316 kb
Host smart-434ef444-42b8-4875-aa83-2d6606ba9874
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=40852759512008803533422392488069216814285361810597476886711862479381503765655 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 73.hmac_stress_all_with_rand_reset.40852759512008803533422392488069216814285361810597476886711862479381503765655
Directory /workspace/73.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/74.hmac_stress_all_with_rand_reset.23691463354623267941827222417160634167237884727971048600518511668994031430198
Short name T650
Test name
Test status
Simulation time 80460760838 ps
CPU time 715.65 seconds
Started Nov 22 01:10:29 PM PST 23
Finished Nov 22 01:22:27 PM PST 23
Peak memory 209196 kb
Host smart-92b34d43-3e21-432d-8f1e-d44f61082e37
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=23691463354623267941827222417160634167237884727971048600518511668994031430198 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 74.hmac_stress_all_with_rand_reset.23691463354623267941827222417160634167237884727971048600518511668994031430198
Directory /workspace/74.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/75.hmac_stress_all_with_rand_reset.45732403778404833327695627346705216648615225850733616589985961123661619787540
Short name T623
Test name
Test status
Simulation time 80460760838 ps
CPU time 685.16 seconds
Started Nov 22 01:10:34 PM PST 23
Finished Nov 22 01:22:01 PM PST 23
Peak memory 209180 kb
Host smart-971f595d-52d0-49d3-aca9-d990347e6727
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=45732403778404833327695627346705216648615225850733616589985961123661619787540 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 75.hmac_stress_all_with_rand_reset.45732403778404833327695627346705216648615225850733616589985961123661619787540
Directory /workspace/75.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/76.hmac_stress_all_with_rand_reset.52190745636869127865968844423414312765641525471359251318392426481803875954058
Short name T354
Test name
Test status
Simulation time 80460760838 ps
CPU time 677.74 seconds
Started Nov 22 01:10:27 PM PST 23
Finished Nov 22 01:21:48 PM PST 23
Peak memory 209208 kb
Host smart-e792f822-4f5f-4cea-acf4-7052968dc78f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=52190745636869127865968844423414312765641525471359251318392426481803875954058 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 76.hmac_stress_all_with_rand_reset.52190745636869127865968844423414312765641525471359251318392426481803875954058
Directory /workspace/76.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/77.hmac_stress_all_with_rand_reset.86629814603987271340794557429779930645013751545073484250561350649963411605097
Short name T705
Test name
Test status
Simulation time 80460760838 ps
CPU time 691.62 seconds
Started Nov 22 01:10:27 PM PST 23
Finished Nov 22 01:22:01 PM PST 23
Peak memory 209184 kb
Host smart-69683683-80cd-4566-853f-c7b75a2bf3de
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=86629814603987271340794557429779930645013751545073484250561350649963411605097 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 77.hmac_stress_all_with_rand_reset.86629814603987271340794557429779930645013751545073484250561350649963411605097
Directory /workspace/77.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/78.hmac_stress_all_with_rand_reset.57718341374862181362482105736470053546313296805086215616986764515648226337216
Short name T351
Test name
Test status
Simulation time 80460760838 ps
CPU time 692.7 seconds
Started Nov 22 01:10:50 PM PST 23
Finished Nov 22 01:22:23 PM PST 23
Peak memory 209312 kb
Host smart-161f99e3-6bdf-4498-9a79-ec09b39517b8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=57718341374862181362482105736470053546313296805086215616986764515648226337216 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 78.hmac_stress_all_with_rand_reset.57718341374862181362482105736470053546313296805086215616986764515648226337216
Directory /workspace/78.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/79.hmac_stress_all_with_rand_reset.44620190714123436437098286719531809244119803512239421560279503019435916915204
Short name T625
Test name
Test status
Simulation time 80460760838 ps
CPU time 719.41 seconds
Started Nov 22 01:10:46 PM PST 23
Finished Nov 22 01:22:47 PM PST 23
Peak memory 209340 kb
Host smart-503a6f8f-8888-4feb-b7f4-499c88ef7dba
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=44620190714123436437098286719531809244119803512239421560279503019435916915204 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 79.hmac_stress_all_with_rand_reset.44620190714123436437098286719531809244119803512239421560279503019435916915204
Directory /workspace/79.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.hmac_alert_test.67656242411660382621731319858383555193033345391395338015755368666299622601727
Short name T503
Test name
Test status
Simulation time 18011528 ps
CPU time 0.55 seconds
Started Nov 22 01:09:08 PM PST 23
Finished Nov 22 01:09:16 PM PST 23
Peak memory 192668 kb
Host smart-0ff5ab24-adcd-4f76-81a4-b3d318d36bb5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67656242411660382621731319858383555193033345391395338015755368666299622601727 -assert nopostpr
oc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 8.hmac_alert_test.67656242411660382621731319858383555193033345391395338015755368666299622601727
Directory /workspace/8.hmac_alert_test/latest

Test location /workspace/coverage/default/8.hmac_back_pressure.55019702249609381592142125581169003553885331203439642847781402864683101923822
Short name T680
Test name
Test status
Simulation time 2592169506 ps
CPU time 47.46 seconds
Started Nov 22 01:09:06 PM PST 23
Finished Nov 22 01:10:02 PM PST 23
Peak memory 231288 kb
Host smart-419c1375-9727-40ff-aa6b-4bdff779841a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=55019702249609381592142125581169003553885331203439642847781402864683101923822 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 8.hmac_back_pressure.55019702249609381592142125581169003553885331203439642847781402864683101923822
Directory /workspace/8.hmac_back_pressure/latest

Test location /workspace/coverage/default/8.hmac_burst_wr.73324806443303920979441089302922270898153464455327885176017166472825229448836
Short name T219
Test name
Test status
Simulation time 4504100639 ps
CPU time 37.53 seconds
Started Nov 22 01:09:09 PM PST 23
Finished Nov 22 01:09:54 PM PST 23
Peak memory 198464 kb
Host smart-f4cf90f6-464c-4373-8881-5e02040cb1dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73324806443303920979441089302922270898153464455327885176017166472825229448836 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.hmac_burst_wr.73324806443303920979441089302922270898153464455327885176017166472825229448836
Directory /workspace/8.hmac_burst_wr/latest

Test location /workspace/coverage/default/8.hmac_datapath_stress.26467592409751753895130234240945891471733603822104266535943401997578387503326
Short name T321
Test name
Test status
Simulation time 4863401336 ps
CPU time 138.09 seconds
Started Nov 22 01:09:31 PM PST 23
Finished Nov 22 01:11:52 PM PST 23
Peak memory 198076 kb
Host smart-13bbda64-3317-4e95-867f-8f12e37de8c8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=26467592409751753895130234240945891471733603822104266535943401997578387503326 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 8.hmac_datapath_stress.26467592409751753895130234240945891471733603822104266535943401997578387503326
Directory /workspace/8.hmac_datapath_stress/latest

Test location /workspace/coverage/default/8.hmac_error.94492905778275096092845179415811564811604913141392815314405899763845033656011
Short name T511
Test name
Test status
Simulation time 26556692074 ps
CPU time 198.63 seconds
Started Nov 22 01:09:04 PM PST 23
Finished Nov 22 01:12:31 PM PST 23
Peak memory 198484 kb
Host smart-0aea638a-c102-4fcb-964f-33d7a72354d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94492905778275096092845179415811564811604913141392815314405899763845033656011 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 8.hmac_error.94492905778275096092845179415811564811604913141392815314405899763845033656011
Directory /workspace/8.hmac_error/latest

Test location /workspace/coverage/default/8.hmac_long_msg.915729738693206309847164793579153587279248448322323154722264587284229979242
Short name T70
Test name
Test status
Simulation time 14959266997 ps
CPU time 118.28 seconds
Started Nov 22 01:09:03 PM PST 23
Finished Nov 22 01:11:10 PM PST 23
Peak memory 198488 kb
Host smart-a203cd28-267c-42c9-b50b-0fd13c5edb31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=915729738693206309847164793579153587279248448322323154722264587284229979242 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 8.hmac_long_msg.915729738693206309847164793579153587279248448322323154722264587284229979242
Directory /workspace/8.hmac_long_msg/latest

Test location /workspace/coverage/default/8.hmac_smoke.5838846977624379243195528132598382684066169816952806812880068010339994794478
Short name T452
Test name
Test status
Simulation time 631560191 ps
CPU time 4.14 seconds
Started Nov 22 01:09:02 PM PST 23
Finished Nov 22 01:09:16 PM PST 23
Peak memory 198516 kb
Host smart-89152382-d1c9-4889-b0a1-2a75c34e50d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5838846977624379243195528132598382684066169816952806812880068010339994794478 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 8.hmac_smoke.5838846977624379243195528132598382684066169816952806812880068010339994794478
Directory /workspace/8.hmac_smoke/latest

Test location /workspace/coverage/default/8.hmac_stress_all.111786735520791863819984973900887045529278395449255675089006910839105849811370
Short name T96
Test name
Test status
Simulation time 146644856361 ps
CPU time 1155.86 seconds
Started Nov 22 01:09:08 PM PST 23
Finished Nov 22 01:28:32 PM PST 23
Peak memory 210556 kb
Host smart-94994148-cad9-4d7c-96d1-8d97ad9486cf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111786735520791863819984
973900887045529278395449255675089006910839105849811370 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all.11178673552079186381998
4973900887045529278395449255675089006910839105849811370
Directory /workspace/8.hmac_stress_all/latest

Test location /workspace/coverage/default/8.hmac_stress_all_with_rand_reset.4747597768685600764860509069148009553829556154418285969254427958003210353753
Short name T440
Test name
Test status
Simulation time 80460760838 ps
CPU time 691.25 seconds
Started Nov 22 01:09:03 PM PST 23
Finished Nov 22 01:20:43 PM PST 23
Peak memory 209296 kb
Host smart-a28ea87a-7727-4c2e-9f31-4896e680f9c1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4747597768685600764860509069148009553829556154418285969254427958003210353753 -assert nopostproc +UVM_TEST
NAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 8.hmac_stress_all_with_rand_reset.4747597768685600764860509069148009553829556154418285969254427958003210353753
Directory /workspace/8.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.hmac_test_hmac_vectors.19792474398698117684169774996843764508635397180669010246874343051469662876331
Short name T679
Test name
Test status
Simulation time 76314633 ps
CPU time 0.97 seconds
Started Nov 22 01:09:04 PM PST 23
Finished Nov 22 01:09:13 PM PST 23
Peak memory 195768 kb
Host smart-9546202c-750d-449f-9722-582660fcc62f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19792474398698117684169774996843764508635397180669010
246874343051469662876331 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_test_hmac_vectors.197924743986981176841697749968437645086
35397180669010246874343051469662876331
Directory /workspace/8.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/8.hmac_test_sha_vectors.24102191450723606743110128874874974840745597394489692272340717175733092227515
Short name T844
Test name
Test status
Simulation time 63914107498 ps
CPU time 471.99 seconds
Started Nov 22 01:09:06 PM PST 23
Finished Nov 22 01:17:05 PM PST 23
Peak memory 198520 kb
Host smart-0b1b269f-5573-448e-984e-d6056e445400
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24102191450723606743110128874874974840745597394489692
272340717175733092227515 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_test_sha_vectors.24102191450723606743110128874874974840745
597394489692272340717175733092227515
Directory /workspace/8.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/8.hmac_wipe_secret.53958124148234105707741124872681083636461799846382230611904379605600212319311
Short name T445
Test name
Test status
Simulation time 8070750677 ps
CPU time 65.55 seconds
Started Nov 22 01:09:06 PM PST 23
Finished Nov 22 01:10:19 PM PST 23
Peak memory 198532 kb
Host smart-85a48a47-4712-413c-a23a-3767a837ead7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53958124148234105707741124872681083636461799846382230611904379605600212319311 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 8.hmac_wipe_secret.53958124148234105707741124872681083636461799846382230611904379605600212319311
Directory /workspace/8.hmac_wipe_secret/latest

Test location /workspace/coverage/default/80.hmac_stress_all_with_rand_reset.64484946058912696815442013404737641878640928048673306804461235982172311103208
Short name T523
Test name
Test status
Simulation time 80460760838 ps
CPU time 699.78 seconds
Started Nov 22 01:10:45 PM PST 23
Finished Nov 22 01:22:26 PM PST 23
Peak memory 209360 kb
Host smart-111e6115-c064-406c-a7d4-edf64ae84423
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=64484946058912696815442013404737641878640928048673306804461235982172311103208 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 80.hmac_stress_all_with_rand_reset.64484946058912696815442013404737641878640928048673306804461235982172311103208
Directory /workspace/80.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/81.hmac_stress_all_with_rand_reset.82947734395470532850185418811699796489536321912542253002151231893354209723752
Short name T808
Test name
Test status
Simulation time 80460760838 ps
CPU time 713.08 seconds
Started Nov 22 01:10:58 PM PST 23
Finished Nov 22 01:22:53 PM PST 23
Peak memory 209364 kb
Host smart-88fe36b6-9fb9-4fc6-b0a4-a40dd265ae59
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=82947734395470532850185418811699796489536321912542253002151231893354209723752 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 81.hmac_stress_all_with_rand_reset.82947734395470532850185418811699796489536321912542253002151231893354209723752
Directory /workspace/81.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/82.hmac_stress_all_with_rand_reset.67593259634799466891026231057457584911307635993213876571695830682382031880936
Short name T830
Test name
Test status
Simulation time 80460760838 ps
CPU time 688.92 seconds
Started Nov 22 01:10:46 PM PST 23
Finished Nov 22 01:22:16 PM PST 23
Peak memory 209360 kb
Host smart-23f9516d-2ece-4e2e-976b-34b60cbc75f5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=67593259634799466891026231057457584911307635993213876571695830682382031880936 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 82.hmac_stress_all_with_rand_reset.67593259634799466891026231057457584911307635993213876571695830682382031880936
Directory /workspace/82.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/83.hmac_stress_all_with_rand_reset.68815193371521727131554758030662188982918719783060866504110461273104001907711
Short name T400
Test name
Test status
Simulation time 80460760838 ps
CPU time 681.53 seconds
Started Nov 22 01:10:40 PM PST 23
Finished Nov 22 01:22:03 PM PST 23
Peak memory 209276 kb
Host smart-2d26c27a-d4a4-4ad6-8b85-053674972e8b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=68815193371521727131554758030662188982918719783060866504110461273104001907711 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 83.hmac_stress_all_with_rand_reset.68815193371521727131554758030662188982918719783060866504110461273104001907711
Directory /workspace/83.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/84.hmac_stress_all_with_rand_reset.14942025720493394033609687217475552383261069181542280815954525192108471561762
Short name T575
Test name
Test status
Simulation time 80460760838 ps
CPU time 701.26 seconds
Started Nov 22 01:10:44 PM PST 23
Finished Nov 22 01:22:26 PM PST 23
Peak memory 209340 kb
Host smart-b9c70eca-6569-46b0-90a7-9407db3834d6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=14942025720493394033609687217475552383261069181542280815954525192108471561762 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 84.hmac_stress_all_with_rand_reset.14942025720493394033609687217475552383261069181542280815954525192108471561762
Directory /workspace/84.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/85.hmac_stress_all_with_rand_reset.91262450200378849598451200945775894254351614455710370130591710318507394764703
Short name T846
Test name
Test status
Simulation time 80460760838 ps
CPU time 687.69 seconds
Started Nov 22 01:10:44 PM PST 23
Finished Nov 22 01:22:13 PM PST 23
Peak memory 209300 kb
Host smart-ec259414-50cd-4bf6-8015-8917d6628724
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=91262450200378849598451200945775894254351614455710370130591710318507394764703 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 85.hmac_stress_all_with_rand_reset.91262450200378849598451200945775894254351614455710370130591710318507394764703
Directory /workspace/85.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/86.hmac_stress_all_with_rand_reset.39101562049096300017597752681027989736737099601622865249728407702581162756083
Short name T865
Test name
Test status
Simulation time 80460760838 ps
CPU time 711.59 seconds
Started Nov 22 01:10:45 PM PST 23
Finished Nov 22 01:22:38 PM PST 23
Peak memory 209344 kb
Host smart-27ba77a9-0a16-44af-be00-cfee3c1de9b9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=39101562049096300017597752681027989736737099601622865249728407702581162756083 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 86.hmac_stress_all_with_rand_reset.39101562049096300017597752681027989736737099601622865249728407702581162756083
Directory /workspace/86.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/87.hmac_stress_all_with_rand_reset.11169251058064596935065623022542681203503840320776811937403388909730375880083
Short name T590
Test name
Test status
Simulation time 80460760838 ps
CPU time 687.96 seconds
Started Nov 22 01:10:39 PM PST 23
Finished Nov 22 01:22:09 PM PST 23
Peak memory 209232 kb
Host smart-f33977af-9300-407b-bad6-fbd947b53e73
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=11169251058064596935065623022542681203503840320776811937403388909730375880083 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 87.hmac_stress_all_with_rand_reset.11169251058064596935065623022542681203503840320776811937403388909730375880083
Directory /workspace/87.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/88.hmac_stress_all_with_rand_reset.15165844892229772258813409448212245561255012487387879224118126832399577990284
Short name T338
Test name
Test status
Simulation time 80460760838 ps
CPU time 699.03 seconds
Started Nov 22 01:10:35 PM PST 23
Finished Nov 22 01:22:16 PM PST 23
Peak memory 209272 kb
Host smart-48e85cd9-4474-427f-9e90-646b5f2ec991
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=15165844892229772258813409448212245561255012487387879224118126832399577990284 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 88.hmac_stress_all_with_rand_reset.15165844892229772258813409448212245561255012487387879224118126832399577990284
Directory /workspace/88.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/89.hmac_stress_all_with_rand_reset.45308118230823422471803213506319555159426150969328011805463035930228085305655
Short name T501
Test name
Test status
Simulation time 80460760838 ps
CPU time 715.38 seconds
Started Nov 22 01:10:48 PM PST 23
Finished Nov 22 01:22:45 PM PST 23
Peak memory 209332 kb
Host smart-e2c86575-f417-47bb-a326-ace65c8c320c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=45308118230823422471803213506319555159426150969328011805463035930228085305655 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 89.hmac_stress_all_with_rand_reset.45308118230823422471803213506319555159426150969328011805463035930228085305655
Directory /workspace/89.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.hmac_alert_test.4703504525780833953078535261277781327806913317041037554738189955591184400976
Short name T554
Test name
Test status
Simulation time 18011528 ps
CPU time 0.56 seconds
Started Nov 22 01:09:20 PM PST 23
Finished Nov 22 01:09:22 PM PST 23
Peak memory 192828 kb
Host smart-2aa58cbe-4f50-4269-a088-6b40f18356b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4703504525780833953078535261277781327806913317041037554738189955591184400976 -assert nopostpro
c +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 9.hmac_alert_test.4703504525780833953078535261277781327806913317041037554738189955591184400976
Directory /workspace/9.hmac_alert_test/latest

Test location /workspace/coverage/default/9.hmac_back_pressure.59286087351892044097921343481314923075718503648412219004106412008603346456498
Short name T821
Test name
Test status
Simulation time 2592169506 ps
CPU time 48.35 seconds
Started Nov 22 01:09:20 PM PST 23
Finished Nov 22 01:10:11 PM PST 23
Peak memory 231360 kb
Host smart-cdad07fe-5ab6-46c3-aed4-4fbe873b8633
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=59286087351892044097921343481314923075718503648412219004106412008603346456498 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 9.hmac_back_pressure.59286087351892044097921343481314923075718503648412219004106412008603346456498
Directory /workspace/9.hmac_back_pressure/latest

Test location /workspace/coverage/default/9.hmac_burst_wr.18396619621955334527469508948252701234475943839494613243398100360265459998839
Short name T235
Test name
Test status
Simulation time 4504100639 ps
CPU time 37.11 seconds
Started Nov 22 01:09:30 PM PST 23
Finished Nov 22 01:10:10 PM PST 23
Peak memory 198540 kb
Host smart-bd5cf35c-4a6a-42a7-9dd4-36fb0566e01a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18396619621955334527469508948252701234475943839494613243398100360265459998839 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.hmac_burst_wr.18396619621955334527469508948252701234475943839494613243398100360265459998839
Directory /workspace/9.hmac_burst_wr/latest

Test location /workspace/coverage/default/9.hmac_datapath_stress.18028486771151097783048507298982776349980020766008570108581996269849514217654
Short name T738
Test name
Test status
Simulation time 4863401336 ps
CPU time 146.88 seconds
Started Nov 22 01:09:22 PM PST 23
Finished Nov 22 01:11:51 PM PST 23
Peak memory 198604 kb
Host smart-9e445cdd-4114-451c-ac79-142d1eac11ee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=18028486771151097783048507298982776349980020766008570108581996269849514217654 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 9.hmac_datapath_stress.18028486771151097783048507298982776349980020766008570108581996269849514217654
Directory /workspace/9.hmac_datapath_stress/latest

Test location /workspace/coverage/default/9.hmac_error.78514807707110291100426964281995178644671574920315782080075800770189979809221
Short name T65
Test name
Test status
Simulation time 26556692074 ps
CPU time 200.06 seconds
Started Nov 22 01:09:19 PM PST 23
Finished Nov 22 01:12:40 PM PST 23
Peak memory 198600 kb
Host smart-dde2a7a4-fb95-4605-9bd3-d9c69b3131e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78514807707110291100426964281995178644671574920315782080075800770189979809221 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 9.hmac_error.78514807707110291100426964281995178644671574920315782080075800770189979809221
Directory /workspace/9.hmac_error/latest

Test location /workspace/coverage/default/9.hmac_long_msg.46861429617714581757296579839277064820873301529938004896860602521417187990086
Short name T360
Test name
Test status
Simulation time 14959266997 ps
CPU time 118.99 seconds
Started Nov 22 01:09:24 PM PST 23
Finished Nov 22 01:11:24 PM PST 23
Peak memory 198432 kb
Host smart-82c3e8d1-da45-4de5-b9ea-edc11d4978a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46861429617714581757296579839277064820873301529938004896860602521417187990086 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.hmac_long_msg.46861429617714581757296579839277064820873301529938004896860602521417187990086
Directory /workspace/9.hmac_long_msg/latest

Test location /workspace/coverage/default/9.hmac_smoke.103745993882702760986883523153643038114407828050113956417473768024250034339829
Short name T834
Test name
Test status
Simulation time 631560191 ps
CPU time 4.15 seconds
Started Nov 22 01:09:08 PM PST 23
Finished Nov 22 01:09:20 PM PST 23
Peak memory 198536 kb
Host smart-7ef08ff0-ca92-49fa-a5ed-ec2f911eeb64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103745993882702760986883523153643038114407828050113956417473768024250034339829 -assert nopostproc +UVM_TESTNAME=hmac_bas
e_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 9.hmac_smoke.103745993882702760986883523153643038114407828050113956417473768024250034339829
Directory /workspace/9.hmac_smoke/latest

Test location /workspace/coverage/default/9.hmac_stress_all.31003268961591283550063021048970180444322229226453944398718573236824572775699
Short name T581
Test name
Test status
Simulation time 146644856361 ps
CPU time 1198.75 seconds
Started Nov 22 01:09:20 PM PST 23
Finished Nov 22 01:29:20 PM PST 23
Peak memory 210852 kb
Host smart-9dd4c17d-a2a0-4ce7-9688-67966c9aba9b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310032689615912835500630
21048970180444322229226453944398718573236824572775699 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all.310032689615912835500630
21048970180444322229226453944398718573236824572775699
Directory /workspace/9.hmac_stress_all/latest

Test location /workspace/coverage/default/9.hmac_stress_all_with_rand_reset.58574396570019459612087917200565940257678116343029490604060136181218503706680
Short name T372
Test name
Test status
Simulation time 80460760838 ps
CPU time 718.66 seconds
Started Nov 22 01:09:19 PM PST 23
Finished Nov 22 01:21:19 PM PST 23
Peak memory 210348 kb
Host smart-b3901344-9356-43fc-831b-9a5c9d8b500f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=58574396570019459612087917200565940257678116343029490604060136181218503706680 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 9.hmac_stress_all_with_rand_reset.58574396570019459612087917200565940257678116343029490604060136181218503706680
Directory /workspace/9.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.hmac_test_hmac_vectors.77485681282235941883548365557660393830762458790106849642682184947298269342528
Short name T661
Test name
Test status
Simulation time 76314633 ps
CPU time 0.92 seconds
Started Nov 22 01:09:18 PM PST 23
Finished Nov 22 01:09:20 PM PST 23
Peak memory 195792 kb
Host smart-e29ba8be-eb73-448a-95aa-89cbe34839e8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77485681282235941883548365557660393830762458790106849
642682184947298269342528 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_test_hmac_vectors.774856812822359418835483655576603938307
62458790106849642682184947298269342528
Directory /workspace/9.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/9.hmac_test_sha_vectors.67022180481475177234553247512518476534303894735733137388714558241863102047026
Short name T476
Test name
Test status
Simulation time 63914107498 ps
CPU time 459.34 seconds
Started Nov 22 01:09:20 PM PST 23
Finished Nov 22 01:17:01 PM PST 23
Peak memory 198472 kb
Host smart-5b9fa5de-bc4a-466a-bc81-c575debce550
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67022180481475177234553247512518476534303894735733137
388714558241863102047026 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_test_sha_vectors.67022180481475177234553247512518476534303
894735733137388714558241863102047026
Directory /workspace/9.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/9.hmac_wipe_secret.22959853521550187033843410764285239341555857653690095875130897939885881977141
Short name T585
Test name
Test status
Simulation time 8070750677 ps
CPU time 62.29 seconds
Started Nov 22 01:09:21 PM PST 23
Finished Nov 22 01:10:26 PM PST 23
Peak memory 198504 kb
Host smart-4b9ccb7f-66f0-4d4d-b39f-6cbb8ccc2c73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22959853521550187033843410764285239341555857653690095875130897939885881977141 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 9.hmac_wipe_secret.22959853521550187033843410764285239341555857653690095875130897939885881977141
Directory /workspace/9.hmac_wipe_secret/latest

Test location /workspace/coverage/default/90.hmac_stress_all_with_rand_reset.78333542888040560827499368551437201387330336294730039377453970720936457397608
Short name T783
Test name
Test status
Simulation time 80460760838 ps
CPU time 671.14 seconds
Started Nov 22 01:10:44 PM PST 23
Finished Nov 22 01:21:56 PM PST 23
Peak memory 209208 kb
Host smart-61dfb759-b3ea-4d47-a3d1-9afc2a797d51
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=78333542888040560827499368551437201387330336294730039377453970720936457397608 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 90.hmac_stress_all_with_rand_reset.78333542888040560827499368551437201387330336294730039377453970720936457397608
Directory /workspace/90.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/91.hmac_stress_all_with_rand_reset.76352542817499473321112584765881119580170418720456143254372789711976742912895
Short name T451
Test name
Test status
Simulation time 80460760838 ps
CPU time 706.53 seconds
Started Nov 22 01:10:46 PM PST 23
Finished Nov 22 01:22:34 PM PST 23
Peak memory 209340 kb
Host smart-cf884667-0858-4446-bef3-91996cc36a70
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=76352542817499473321112584765881119580170418720456143254372789711976742912895 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 91.hmac_stress_all_with_rand_reset.76352542817499473321112584765881119580170418720456143254372789711976742912895
Directory /workspace/91.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/92.hmac_stress_all_with_rand_reset.10639317649605694648618343834444377142204659761160414402470079277530377604839
Short name T538
Test name
Test status
Simulation time 80460760838 ps
CPU time 665.59 seconds
Started Nov 22 01:10:42 PM PST 23
Finished Nov 22 01:21:49 PM PST 23
Peak memory 209364 kb
Host smart-d82870ad-f6c3-431c-b800-0077632d0f91
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=10639317649605694648618343834444377142204659761160414402470079277530377604839 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 92.hmac_stress_all_with_rand_reset.10639317649605694648618343834444377142204659761160414402470079277530377604839
Directory /workspace/92.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/93.hmac_stress_all_with_rand_reset.34080932287511793863572512326823911612212567990679560446723082821198677220181
Short name T402
Test name
Test status
Simulation time 80460760838 ps
CPU time 722.09 seconds
Started Nov 22 01:10:46 PM PST 23
Finished Nov 22 01:22:50 PM PST 23
Peak memory 209340 kb
Host smart-7d175371-e199-4d2f-a134-bcaec08f4c96
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=34080932287511793863572512326823911612212567990679560446723082821198677220181 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 93.hmac_stress_all_with_rand_reset.34080932287511793863572512326823911612212567990679560446723082821198677220181
Directory /workspace/93.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/94.hmac_stress_all_with_rand_reset.11463952703668014953961149465232983498385497509469443687306384864089741851412
Short name T403
Test name
Test status
Simulation time 80460760838 ps
CPU time 692.71 seconds
Started Nov 22 01:10:45 PM PST 23
Finished Nov 22 01:22:19 PM PST 23
Peak memory 209340 kb
Host smart-cccd40fb-63a3-494c-afdc-5d181c2403fd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=11463952703668014953961149465232983498385497509469443687306384864089741851412 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 94.hmac_stress_all_with_rand_reset.11463952703668014953961149465232983498385497509469443687306384864089741851412
Directory /workspace/94.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/95.hmac_stress_all_with_rand_reset.66841129568314432608563670030376094128633804366951928940513299972368638578942
Short name T851
Test name
Test status
Simulation time 80460760838 ps
CPU time 712.08 seconds
Started Nov 22 01:10:38 PM PST 23
Finished Nov 22 01:22:32 PM PST 23
Peak memory 209352 kb
Host smart-40d74aec-4fcb-4f0b-9be8-a072ab96ca44
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=66841129568314432608563670030376094128633804366951928940513299972368638578942 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 95.hmac_stress_all_with_rand_reset.66841129568314432608563670030376094128633804366951928940513299972368638578942
Directory /workspace/95.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/96.hmac_stress_all_with_rand_reset.11358868521583059850255482625904946928033466630788363040559864674488048258162
Short name T208
Test name
Test status
Simulation time 80460760838 ps
CPU time 716.17 seconds
Started Nov 22 01:10:35 PM PST 23
Finished Nov 22 01:22:33 PM PST 23
Peak memory 209248 kb
Host smart-7f9fc0e6-6ecb-4dd3-92a1-63b6b49777ed
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=11358868521583059850255482625904946928033466630788363040559864674488048258162 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 96.hmac_stress_all_with_rand_reset.11358868521583059850255482625904946928033466630788363040559864674488048258162
Directory /workspace/96.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/97.hmac_stress_all_with_rand_reset.58509318480690143042320308268989427562337299619571336229042299363884105580622
Short name T490
Test name
Test status
Simulation time 80460760838 ps
CPU time 703.2 seconds
Started Nov 22 01:11:06 PM PST 23
Finished Nov 22 01:22:52 PM PST 23
Peak memory 209368 kb
Host smart-0156c0eb-64f3-4367-acae-4a21a36d90dd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=58509318480690143042320308268989427562337299619571336229042299363884105580622 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 97.hmac_stress_all_with_rand_reset.58509318480690143042320308268989427562337299619571336229042299363884105580622
Directory /workspace/97.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/98.hmac_stress_all_with_rand_reset.100970627230632920540102532355813435347461002578883286436779957058032547615057
Short name T758
Test name
Test status
Simulation time 80460760838 ps
CPU time 716.13 seconds
Started Nov 22 01:10:49 PM PST 23
Finished Nov 22 01:22:47 PM PST 23
Peak memory 209340 kb
Host smart-07174f60-befa-4da7-9b46-6f64ed6956ce
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=100970627230632920540102532355813435347461002578883286436779957058032547615057 -assert nopostproc +UVM_TE
STNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 98.hmac_stress_all_with_rand_reset.100970627230632920540102532355813435347461002578883286436779957058032547615057
Directory /workspace/98.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/99.hmac_stress_all_with_rand_reset.88291654050889028885382086173076061926463074972912032986197342350373712091207
Short name T598
Test name
Test status
Simulation time 80460760838 ps
CPU time 685.96 seconds
Started Nov 22 01:10:55 PM PST 23
Finished Nov 22 01:22:23 PM PST 23
Peak memory 209196 kb
Host smart-ca749c99-b786-4f2b-b9b1-207d9c9464ef
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=88291654050889028885382086173076061926463074972912032986197342350373712091207 -assert nopostproc +UVM_TES
TNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 99.hmac_stress_all_with_rand_reset.88291654050889028885382086173076061926463074972912032986197342350373712091207
Directory /workspace/99.hmac_stress_all_with_rand_reset/latest
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