HMAC Simulation Results

Wednesday November 22 2023 20:02:38 UTC

GitHub Revision: 4002b28ec4

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 56541452733628775295814943325285397402671097056517970046183331126493552547969

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke hmac_smoke 4.350s 631.560us 50 50 100.00
V1 csr_hw_reset hmac_csr_hw_reset 0.720s 30.476us 5 5 100.00
V1 csr_rw hmac_csr_rw 0.710s 31.297us 20 20 100.00
V1 csr_bit_bash hmac_csr_bit_bash 6.490s 1.012ms 5 5 100.00
V1 csr_aliasing hmac_csr_aliasing 1.920s 179.635us 5 5 100.00
V1 csr_mem_rw_with_rand_reset hmac_csr_mem_rw_with_rand_reset 11.676m 129.656ms 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr hmac_csr_rw 0.710s 31.297us 20 20 100.00
hmac_csr_aliasing 1.920s 179.635us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 long_msg hmac_long_msg 2.023m 14.959ms 50 50 100.00
V2 back_pressure hmac_back_pressure 51.590s 2.592ms 50 50 100.00
V2 test_vectors hmac_test_sha_vectors 8.059m 63.914ms 50 50 100.00
hmac_test_hmac_vectors 0.990s 76.315us 50 50 100.00
V2 burst_wr hmac_burst_wr 39.100s 4.504ms 50 50 100.00
V2 datapath_stress hmac_datapath_stress 2.492m 4.863ms 50 50 100.00
V2 error hmac_error 3.352m 26.557ms 50 50 100.00
V2 wipe_secret hmac_wipe_secret 1.093m 8.071ms 50 50 100.00
V2 stress_all hmac_stress_all 19.979m 146.645ms 50 50 100.00
V2 alert_test hmac_alert_test 0.620s 18.012us 50 50 100.00
V2 intr_test hmac_intr_test 0.640s 22.994us 50 50 100.00
V2 tl_d_oob_addr_access hmac_tl_errors 2.390s 199.171us 20 20 100.00
V2 tl_d_illegal_access hmac_tl_errors 2.390s 199.171us 20 20 100.00
V2 tl_d_outstanding_access hmac_csr_hw_reset 0.720s 30.476us 5 5 100.00
hmac_csr_rw 0.710s 31.297us 20 20 100.00
hmac_csr_aliasing 1.920s 179.635us 5 5 100.00
hmac_same_csr_outstanding 1.160s 89.029us 20 20 100.00
V2 tl_d_partial_access hmac_csr_hw_reset 0.720s 30.476us 5 5 100.00
hmac_csr_rw 0.710s 31.297us 20 20 100.00
hmac_csr_aliasing 1.920s 179.635us 5 5 100.00
hmac_same_csr_outstanding 1.160s 89.029us 20 20 100.00
V2 TOTAL 590 590 100.00
V2S tl_intg_err hmac_sec_cm 0.910s 100.939us 5 5 100.00
hmac_tl_intg_err 1.900s 180.082us 20 20 100.00
V2S sec_cm_bus_integrity hmac_tl_intg_err 1.900s 180.082us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 write_config_and_secret_key_during_msg_wr hmac_smoke 4.350s 631.560us 50 50 100.00
V3 stress_all_with_rand_reset hmac_stress_all_with_rand_reset 12.434m 80.461ms 200 200 100.00
V3 TOTAL 200 200 100.00
TOTAL 920 920 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 13 13 13 100.00
V2S 2 2 2 100.00
V3 1 1 1 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.56 99.53 98.47 100.00 96.00 99.76 99.49 89.68

Past Results