Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	40878834	1			T12	5		T13	1		T15	5
all_values[1]	40878834	1			T12	5		T13	1		T15	5
all_values[2]	40878834	1			T12	5		T13	1		T15	5

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

122952

1

T12

7

T13

3

T15

11

auto[1]

122513550

1

T12

8

T15

4

T19

18

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

88947628

1

T12

12

T13

3

T15

7

auto[1]

33688874

1

T12

3

T15

8

T19

12

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	58798	1			T12	1		T13	1		T15	1
all_values[0]	auto[0]	auto[1]	1363	1			T12	1		T15	4		T19	3
all_values[0]	auto[1]	auto[0]	40647172	1			T12	3		T19	4		T47	3
all_values[0]	auto[1]	auto[1]	171501	1			T19	1		T47	1		T48	3
all_values[1]	auto[0]	auto[0]	19088	1			T12	3		T13	1		T15	1
all_values[1]	auto[0]	auto[1]	21157	1			T15	2		T47	1		T48	1
all_values[1]	auto[1]	auto[0]	23152157	1			T12	2		T15	2		T19	2
all_values[1]	auto[1]	auto[1]	17686432	1			T19	6		T47	4		T48	5
all_values[2]	auto[0]	auto[0]	18026	1			T12	2		T13	1		T15	1
all_values[2]	auto[0]	auto[1]	4520	1			T15	2		T19	1		T47	1
all_values[2]	auto[1]	auto[0]	25052387	1			T12	1		T15	2		T19	4
all_values[2]	auto[1]	auto[1]	15803901	1			T12	2		T19	1		T47	1